2007-06-06 15:42:06 +08:00
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//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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2007-12-30 04:36:04 +08:00
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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2007-06-06 15:42:06 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the interfaces that Mips uses to lower LLVM code into a
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// selection DAG.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mips-lower"
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#include "MipsISelLowering.h"
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2007-08-28 13:08:16 +08:00
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#include "MipsMachineFunction.h"
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2007-06-06 15:42:06 +08:00
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#include "MipsTargetMachine.h"
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2009-08-13 14:28:06 +08:00
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#include "MipsTargetObjectFile.h"
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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#include "MipsSubtarget.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/DerivedTypes.h"
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#include "llvm/Function.h"
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2008-07-22 02:52:34 +08:00
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#include "llvm/GlobalVariable.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/Intrinsics.h"
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#include "llvm/CallingConv.h"
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#include "llvm/CodeGen/CallingConvLower.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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2007-12-31 12:13:23 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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2007-06-06 15:42:06 +08:00
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#include "llvm/CodeGen/SelectionDAGISel.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/Support/Debug.h"
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2009-07-12 04:10:48 +08:00
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#include "llvm/Support/ErrorHandling.h"
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2007-06-06 15:42:06 +08:00
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using namespace llvm;
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2009-07-28 11:13:23 +08:00
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const char *MipsTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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2008-07-30 03:05:28 +08:00
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case MipsISD::JmpLink : return "MipsISD::JmpLink";
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case MipsISD::Hi : return "MipsISD::Hi";
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case MipsISD::Lo : return "MipsISD::Lo";
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case MipsISD::GPRel : return "MipsISD::GPRel";
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case MipsISD::Ret : return "MipsISD::Ret";
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case MipsISD::SelectCC : return "MipsISD::SelectCC";
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case MipsISD::FPSelectCC : return "MipsISD::FPSelectCC";
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case MipsISD::FPBrcond : return "MipsISD::FPBrcond";
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case MipsISD::FPCmp : return "MipsISD::FPCmp";
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2009-05-28 01:23:44 +08:00
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case MipsISD::FPRound : return "MipsISD::FPRound";
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2011-01-19 03:29:17 +08:00
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case MipsISD::MAdd : return "MipsISD::MAdd";
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case MipsISD::MAddu : return "MipsISD::MAddu";
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case MipsISD::MSub : return "MipsISD::MSub";
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case MipsISD::MSubu : return "MipsISD::MSubu";
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2008-07-30 03:05:28 +08:00
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default : return NULL;
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2007-06-06 15:42:06 +08:00
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}
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}
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MipsTargetLowering::
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2009-07-28 11:13:23 +08:00
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MipsTargetLowering(MipsTargetMachine &TM)
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2009-08-13 14:28:06 +08:00
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: TargetLowering(TM, new MipsTargetObjectFile()) {
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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Subtarget = &TM.getSubtarget<MipsSubtarget>();
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2007-06-06 15:42:06 +08:00
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// Mips does not have i1 type, so use i32 for
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2010-11-23 11:31:01 +08:00
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// setcc operations results (slt, sgt, ...).
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2008-11-23 23:47:28 +08:00
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setBooleanContents(ZeroOrOneBooleanContent);
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2007-06-06 15:42:06 +08:00
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// Set up the register classes
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2009-08-12 04:47:22 +08:00
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addRegisterClass(MVT::i32, Mips::CPURegsRegisterClass);
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addRegisterClass(MVT::f32, Mips::FGR32RegisterClass);
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2007-06-06 15:42:06 +08:00
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|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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// When dealing with single precision only, use libcalls
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2009-03-21 08:05:07 +08:00
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if (!Subtarget->isSingleFloat())
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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if (!Subtarget->isFP64bit())
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2009-08-12 04:47:22 +08:00
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addRegisterClass(MVT::f64, Mips::AFGR64RegisterClass);
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Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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2010-11-23 11:31:01 +08:00
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// Load extented operations for i1 types must be promoted
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2009-08-12 04:47:22 +08:00
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setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
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2007-06-06 15:42:06 +08:00
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2009-07-17 12:07:24 +08:00
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// MIPS doesn't have extending float->double load/store
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2009-08-12 04:47:22 +08:00
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setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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2009-07-17 10:28:12 +08:00
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2010-11-23 11:31:01 +08:00
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// Used by legalize types to correctly generate the setcc result.
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// Without this, every float setcc comes with a AND/OR with the result,
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// we don't want this, since the fpcmp result goes to a flag register,
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2008-08-01 02:31:28 +08:00
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// which is used implicitly by brcond and select operations.
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2009-08-12 04:47:22 +08:00
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AddPromotedToType(ISD::SETCC, MVT::i1, MVT::i32);
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2008-08-01 02:31:28 +08:00
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2008-07-09 12:15:08 +08:00
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// Mips Custom Operations
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
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setOperationAction(ISD::GlobalTLSAddress, MVT::i32, Custom);
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setOperationAction(ISD::JumpTable, MVT::i32, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
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setOperationAction(ISD::SELECT, MVT::f32, Custom);
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setOperationAction(ISD::SELECT, MVT::f64, Custom);
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setOperationAction(ISD::SELECT, MVT::i32, Custom);
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setOperationAction(ISD::SETCC, MVT::f32, Custom);
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setOperationAction(ISD::SETCC, MVT::f64, Custom);
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setOperationAction(ISD::BRCOND, MVT::Other, Custom);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i32, Custom);
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setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom);
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2010-02-07 05:00:02 +08:00
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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2008-07-09 12:15:08 +08:00
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2010-11-23 11:31:01 +08:00
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// We custom lower AND/OR to handle the case where the DAG contain 'ands/ors'
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// with operands comming from setcc fp comparions. This is necessary since
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2008-08-03 03:37:33 +08:00
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// the result from these setcc are in a flag registers (FCR31).
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::AND, MVT::i32, Custom);
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setOperationAction(ISD::OR, MVT::i32, Custom);
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2008-08-01 02:31:28 +08:00
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2008-07-09 12:15:08 +08:00
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// Operations not directly supported by Mips.
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::BR_JT, MVT::Other, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
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setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::CTPOP, MVT::i32, Expand);
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setOperationAction(ISD::CTTZ, MVT::i32, Expand);
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setOperationAction(ISD::ROTL, MVT::i32, Expand);
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2010-12-10 01:32:30 +08:00
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if (!Subtarget->isMips32r2())
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setOperationAction(ISD::ROTR, MVT::i32, Expand);
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f32, Expand);
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setOperationAction(ISD::FCOPYSIGN, MVT::f64, Expand);
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setOperationAction(ISD::FSIN, MVT::f32, Expand);
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2011-03-05 02:54:14 +08:00
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setOperationAction(ISD::FSIN, MVT::f64, Expand);
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::FCOS, MVT::f32, Expand);
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2011-03-05 02:54:14 +08:00
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setOperationAction(ISD::FCOS, MVT::f64, Expand);
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::FPOWI, MVT::f32, Expand);
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setOperationAction(ISD::FPOW, MVT::f32, Expand);
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setOperationAction(ISD::FLOG, MVT::f32, Expand);
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setOperationAction(ISD::FLOG2, MVT::f32, Expand);
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setOperationAction(ISD::FLOG10, MVT::f32, Expand);
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setOperationAction(ISD::FEXP, MVT::f32, Expand);
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2008-07-09 12:15:08 +08:00
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::EH_LABEL, MVT::Other, Expand);
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2008-07-09 12:15:08 +08:00
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// Use the default for now
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::MEMBARRIER, MVT::Other, Expand);
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2008-07-08 03:11:24 +08:00
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2008-08-04 14:44:31 +08:00
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if (Subtarget->isSingleFloat())
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
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2007-06-06 15:42:06 +08:00
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2008-07-09 13:32:22 +08:00
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if (!Subtarget->hasSEInReg()) {
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
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}
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2008-08-08 14:16:31 +08:00
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if (!Subtarget->hasBitCount())
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::CTLZ, MVT::i32, Expand);
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2008-08-08 14:16:31 +08:00
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2008-08-13 15:13:40 +08:00
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if (!Subtarget->hasSwap())
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2009-08-12 04:47:22 +08:00
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setOperationAction(ISD::BSWAP, MVT::i32, Expand);
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2008-08-13 15:13:40 +08:00
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2011-01-19 03:29:17 +08:00
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setTargetDAGCombine(ISD::ADDE);
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setTargetDAGCombine(ISD::SUBE);
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2007-06-06 15:42:06 +08:00
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setStackPointerRegisterToSaveRestore(Mips::SP);
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computeRegisterProperties();
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}
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2009-08-12 04:47:22 +08:00
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|
|
MVT::SimpleValueType MipsTargetLowering::getSetCCResultType(EVT VT) const {
|
|
|
|
return MVT::i32;
|
2008-03-10 23:42:14 +08:00
|
|
|
}
|
|
|
|
|
2009-07-02 02:50:55 +08:00
|
|
|
/// getFunctionAlignment - Return the Log2 alignment of this function.
|
2009-07-01 06:38:32 +08:00
|
|
|
unsigned MipsTargetLowering::getFunctionAlignment(const Function *) const {
|
|
|
|
return 2;
|
|
|
|
}
|
2008-03-10 23:42:14 +08:00
|
|
|
|
2011-01-19 03:29:17 +08:00
|
|
|
// SelectMadd -
|
|
|
|
// Transforms a subgraph in CurDAG if the following pattern is found:
|
|
|
|
// (addc multLo, Lo0), (adde multHi, Hi0),
|
|
|
|
// where,
|
|
|
|
// multHi/Lo: product of multiplication
|
2011-02-11 02:05:10 +08:00
|
|
|
// Lo0: initial value of Lo register
|
|
|
|
// Hi0: initial value of Hi register
|
2011-01-19 03:29:17 +08:00
|
|
|
// Return true if mattern matching was successful.
|
|
|
|
static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) {
|
2011-02-11 02:05:10 +08:00
|
|
|
// ADDENode's second operand must be a flag output of an ADDC node in order
|
2011-01-19 03:29:17 +08:00
|
|
|
// for the matching to be successful.
|
|
|
|
SDNode* ADDCNode = ADDENode->getOperand(2).getNode();
|
|
|
|
|
|
|
|
if (ADDCNode->getOpcode() != ISD::ADDC)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue MultHi = ADDENode->getOperand(0);
|
|
|
|
SDValue MultLo = ADDCNode->getOperand(0);
|
2011-02-11 02:05:10 +08:00
|
|
|
SDNode* MultNode = MultHi.getNode();
|
2011-01-19 03:29:17 +08:00
|
|
|
unsigned MultOpc = MultHi.getOpcode();
|
|
|
|
|
|
|
|
// MultHi and MultLo must be generated by the same node,
|
|
|
|
if (MultLo.getNode() != MultNode)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// and it must be a multiplication.
|
|
|
|
if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
|
|
|
|
return false;
|
2011-02-11 02:05:10 +08:00
|
|
|
|
|
|
|
// MultLo amd MultHi must be the first and second output of MultNode
|
|
|
|
// respectively.
|
2011-01-19 03:29:17 +08:00
|
|
|
if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
|
|
|
|
return false;
|
|
|
|
|
2011-02-11 02:05:10 +08:00
|
|
|
// Transform this to a MADD only if ADDENode and ADDCNode are the only users
|
2011-01-19 03:29:17 +08:00
|
|
|
// of the values of MultNode, in which case MultNode will be removed in later
|
|
|
|
// phases.
|
|
|
|
// If there exist users other than ADDENode or ADDCNode, this function returns
|
2011-02-11 02:05:10 +08:00
|
|
|
// here, which will result in MultNode being mapped to a single MULT
|
|
|
|
// instruction node rather than a pair of MULT and MADD instructions being
|
2011-01-19 03:29:17 +08:00
|
|
|
// produced.
|
|
|
|
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
2011-02-11 02:05:10 +08:00
|
|
|
SDValue Chain = CurDAG->getEntryNode();
|
2011-01-19 03:29:17 +08:00
|
|
|
DebugLoc dl = ADDENode->getDebugLoc();
|
|
|
|
|
|
|
|
// create MipsMAdd(u) node
|
|
|
|
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd;
|
2011-02-11 02:05:10 +08:00
|
|
|
|
2011-01-19 03:29:17 +08:00
|
|
|
SDValue MAdd = CurDAG->getNode(MultOpc, dl,
|
|
|
|
MVT::Glue,
|
|
|
|
MultNode->getOperand(0),// Factor 0
|
|
|
|
MultNode->getOperand(1),// Factor 1
|
2011-02-11 02:05:10 +08:00
|
|
|
ADDCNode->getOperand(1),// Lo0
|
2011-01-19 03:29:17 +08:00
|
|
|
ADDENode->getOperand(1));// Hi0
|
|
|
|
|
|
|
|
// create CopyFromReg nodes
|
|
|
|
SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
|
|
|
|
MAdd);
|
2011-02-11 02:05:10 +08:00
|
|
|
SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
|
2011-01-19 03:29:17 +08:00
|
|
|
Mips::HI, MVT::i32,
|
|
|
|
CopyFromLo.getValue(2));
|
|
|
|
|
|
|
|
// replace uses of adde and addc here
|
|
|
|
if (!SDValue(ADDCNode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), CopyFromLo);
|
|
|
|
|
|
|
|
if (!SDValue(ADDENode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), CopyFromHi);
|
|
|
|
|
2011-02-11 02:05:10 +08:00
|
|
|
return true;
|
2011-01-19 03:29:17 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// SelectMsub -
|
|
|
|
// Transforms a subgraph in CurDAG if the following pattern is found:
|
|
|
|
// (addc Lo0, multLo), (sube Hi0, multHi),
|
|
|
|
// where,
|
|
|
|
// multHi/Lo: product of multiplication
|
2011-02-11 02:05:10 +08:00
|
|
|
// Lo0: initial value of Lo register
|
|
|
|
// Hi0: initial value of Hi register
|
2011-01-19 03:29:17 +08:00
|
|
|
// Return true if mattern matching was successful.
|
|
|
|
static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) {
|
2011-02-11 02:05:10 +08:00
|
|
|
// SUBENode's second operand must be a flag output of an SUBC node in order
|
2011-01-19 03:29:17 +08:00
|
|
|
// for the matching to be successful.
|
|
|
|
SDNode* SUBCNode = SUBENode->getOperand(2).getNode();
|
|
|
|
|
|
|
|
if (SUBCNode->getOpcode() != ISD::SUBC)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue MultHi = SUBENode->getOperand(1);
|
|
|
|
SDValue MultLo = SUBCNode->getOperand(1);
|
2011-02-11 02:05:10 +08:00
|
|
|
SDNode* MultNode = MultHi.getNode();
|
2011-01-19 03:29:17 +08:00
|
|
|
unsigned MultOpc = MultHi.getOpcode();
|
|
|
|
|
|
|
|
// MultHi and MultLo must be generated by the same node,
|
|
|
|
if (MultLo.getNode() != MultNode)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// and it must be a multiplication.
|
|
|
|
if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// MultLo amd MultHi must be the first and second output of MultNode
|
|
|
|
// respectively.
|
|
|
|
if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Transform this to a MSUB only if SUBENode and SUBCNode are the only users
|
|
|
|
// of the values of MultNode, in which case MultNode will be removed in later
|
|
|
|
// phases.
|
|
|
|
// If there exist users other than SUBENode or SUBCNode, this function returns
|
|
|
|
// here, which will result in MultNode being mapped to a single MULT
|
|
|
|
// instruction node rather than a pair of MULT and MSUB instructions being
|
|
|
|
// produced.
|
|
|
|
if (!MultHi.hasOneUse() || !MultLo.hasOneUse())
|
|
|
|
return false;
|
|
|
|
|
|
|
|
SDValue Chain = CurDAG->getEntryNode();
|
|
|
|
DebugLoc dl = SUBENode->getDebugLoc();
|
|
|
|
|
|
|
|
// create MipsSub(u) node
|
|
|
|
MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub;
|
|
|
|
|
|
|
|
SDValue MSub = CurDAG->getNode(MultOpc, dl,
|
|
|
|
MVT::Glue,
|
|
|
|
MultNode->getOperand(0),// Factor 0
|
|
|
|
MultNode->getOperand(1),// Factor 1
|
|
|
|
SUBCNode->getOperand(0),// Lo0
|
|
|
|
SUBENode->getOperand(0));// Hi0
|
|
|
|
|
|
|
|
// create CopyFromReg nodes
|
|
|
|
SDValue CopyFromLo = CurDAG->getCopyFromReg(Chain, dl, Mips::LO, MVT::i32,
|
|
|
|
MSub);
|
|
|
|
SDValue CopyFromHi = CurDAG->getCopyFromReg(CopyFromLo.getValue(1), dl,
|
|
|
|
Mips::HI, MVT::i32,
|
|
|
|
CopyFromLo.getValue(2));
|
|
|
|
|
|
|
|
// replace uses of sube and subc here
|
|
|
|
if (!SDValue(SUBCNode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), CopyFromLo);
|
|
|
|
|
|
|
|
if (!SDValue(SUBENode, 0).use_empty())
|
|
|
|
CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), CopyFromHi);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static SDValue PerformADDECombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalize())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (Subtarget->isMips32() && SelectMadd(N, &DAG))
|
|
|
|
return SDValue(N, 0);
|
2011-02-11 02:05:10 +08:00
|
|
|
|
2011-01-19 03:29:17 +08:00
|
|
|
return SDValue();
|
2011-02-11 02:05:10 +08:00
|
|
|
}
|
2011-01-19 03:29:17 +08:00
|
|
|
|
|
|
|
static SDValue PerformSUBECombine(SDNode *N, SelectionDAG& DAG,
|
|
|
|
TargetLowering::DAGCombinerInfo &DCI,
|
|
|
|
const MipsSubtarget* Subtarget) {
|
|
|
|
if (DCI.isBeforeLegalize())
|
|
|
|
return SDValue();
|
|
|
|
|
|
|
|
if (Subtarget->isMips32() && SelectMsub(N, &DAG))
|
|
|
|
return SDValue(N, 0);
|
2011-02-11 02:05:10 +08:00
|
|
|
|
2011-01-19 03:29:17 +08:00
|
|
|
return SDValue();
|
2011-02-11 02:05:10 +08:00
|
|
|
}
|
2011-01-19 03:29:17 +08:00
|
|
|
|
2011-02-11 02:05:10 +08:00
|
|
|
SDValue MipsTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI)
|
2011-01-19 03:29:17 +08:00
|
|
|
const {
|
|
|
|
SelectionDAG &DAG = DCI.DAG;
|
|
|
|
unsigned opc = N->getOpcode();
|
|
|
|
|
|
|
|
switch (opc) {
|
|
|
|
default: break;
|
|
|
|
case ISD::ADDE:
|
|
|
|
return PerformADDECombine(N, DAG, DCI, Subtarget);
|
|
|
|
case ISD::SUBE:
|
|
|
|
return PerformSUBECombine(N, DAG, DCI, Subtarget);
|
|
|
|
}
|
|
|
|
|
|
|
|
return SDValue();
|
|
|
|
}
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerOperation(SDValue Op, SelectionDAG &DAG) const
|
2007-06-06 15:42:06 +08:00
|
|
|
{
|
2010-11-23 11:31:01 +08:00
|
|
|
switch (Op.getOpcode())
|
2007-06-06 15:42:06 +08:00
|
|
|
{
|
2008-08-08 03:08:11 +08:00
|
|
|
case ISD::AND: return LowerANDOR(Op, DAG);
|
|
|
|
case ISD::BRCOND: return LowerBRCOND(Op, DAG);
|
|
|
|
case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
|
|
|
|
case ISD::DYNAMIC_STACKALLOC: return LowerDYNAMIC_STACKALLOC(Op, DAG);
|
2009-05-28 01:23:44 +08:00
|
|
|
case ISD::FP_TO_SINT: return LowerFP_TO_SINT(Op, DAG);
|
2008-08-08 03:08:11 +08:00
|
|
|
case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
|
|
|
|
case ISD::GlobalTLSAddress: return LowerGlobalTLSAddress(Op, DAG);
|
|
|
|
case ISD::JumpTable: return LowerJumpTable(Op, DAG);
|
|
|
|
case ISD::OR: return LowerANDOR(Op, DAG);
|
|
|
|
case ISD::SELECT: return LowerSELECT(Op, DAG);
|
|
|
|
case ISD::SETCC: return LowerSETCC(Op, DAG);
|
2010-02-07 05:00:02 +08:00
|
|
|
case ISD::VASTART: return LowerVASTART(Op, DAG);
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2008-07-28 05:46:04 +08:00
|
|
|
return SDValue();
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Lower helper functions
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
// AddLiveIn - This helper function adds the specified physical register to the
|
|
|
|
// MachineFunction as a live in value. It also creates a corresponding
|
|
|
|
// virtual register for it.
|
|
|
|
static unsigned
|
2010-11-23 11:31:01 +08:00
|
|
|
AddLiveIn(MachineFunction &MF, unsigned PReg, TargetRegisterClass *RC)
|
2007-06-06 15:42:06 +08:00
|
|
|
{
|
|
|
|
assert(RC->contains(PReg) && "Not the correct regclass!");
|
2007-12-31 12:13:23 +08:00
|
|
|
unsigned VReg = MF.getRegInfo().createVirtualRegister(RC);
|
|
|
|
MF.getRegInfo().addLiveIn(PReg, VReg);
|
2007-06-06 15:42:06 +08:00
|
|
|
return VReg;
|
|
|
|
}
|
|
|
|
|
2008-07-29 03:11:24 +08:00
|
|
|
// Get fp branch code (not opcode) from condition code.
|
|
|
|
static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) {
|
|
|
|
if (CC >= Mips::FCOND_F && CC <= Mips::FCOND_NGT)
|
|
|
|
return Mips::BRANCH_T;
|
|
|
|
|
|
|
|
if (CC >= Mips::FCOND_T && CC <= Mips::FCOND_GT)
|
|
|
|
return Mips::BRANCH_F;
|
|
|
|
|
|
|
|
return Mips::BRANCH_INVALID;
|
|
|
|
}
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2008-07-30 03:05:28 +08:00
|
|
|
static unsigned FPBranchCodeToOpc(Mips::FPBranchCode BC) {
|
|
|
|
switch(BC) {
|
|
|
|
default:
|
2009-07-15 00:55:14 +08:00
|
|
|
llvm_unreachable("Unknown branch code");
|
2008-07-30 03:05:28 +08:00
|
|
|
case Mips::BRANCH_T : return Mips::BC1T;
|
|
|
|
case Mips::BRANCH_F : return Mips::BC1F;
|
|
|
|
case Mips::BRANCH_TL : return Mips::BC1TL;
|
|
|
|
case Mips::BRANCH_FL : return Mips::BC1FL;
|
|
|
|
}
|
|
|
|
}
|
2008-07-29 03:11:24 +08:00
|
|
|
|
|
|
|
static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) {
|
|
|
|
switch (CC) {
|
2009-07-15 00:55:14 +08:00
|
|
|
default: llvm_unreachable("Unknown fp condition code!");
|
2010-11-23 11:31:01 +08:00
|
|
|
case ISD::SETEQ:
|
2008-07-29 03:11:24 +08:00
|
|
|
case ISD::SETOEQ: return Mips::FCOND_EQ;
|
|
|
|
case ISD::SETUNE: return Mips::FCOND_OGL;
|
2010-11-23 11:31:01 +08:00
|
|
|
case ISD::SETLT:
|
2008-07-29 03:11:24 +08:00
|
|
|
case ISD::SETOLT: return Mips::FCOND_OLT;
|
2010-11-23 11:31:01 +08:00
|
|
|
case ISD::SETGT:
|
2008-07-29 03:11:24 +08:00
|
|
|
case ISD::SETOGT: return Mips::FCOND_OGT;
|
2010-11-23 11:31:01 +08:00
|
|
|
case ISD::SETLE:
|
|
|
|
case ISD::SETOLE: return Mips::FCOND_OLE;
|
2008-07-29 03:11:24 +08:00
|
|
|
case ISD::SETGE:
|
|
|
|
case ISD::SETOGE: return Mips::FCOND_OGE;
|
|
|
|
case ISD::SETULT: return Mips::FCOND_ULT;
|
2010-11-23 11:31:01 +08:00
|
|
|
case ISD::SETULE: return Mips::FCOND_ULE;
|
2008-07-29 03:11:24 +08:00
|
|
|
case ISD::SETUGT: return Mips::FCOND_UGT;
|
|
|
|
case ISD::SETUGE: return Mips::FCOND_UGE;
|
2010-11-23 11:31:01 +08:00
|
|
|
case ISD::SETUO: return Mips::FCOND_UN;
|
2008-07-29 03:11:24 +08:00
|
|
|
case ISD::SETO: return Mips::FCOND_OR;
|
2010-11-23 11:31:01 +08:00
|
|
|
case ISD::SETNE:
|
2008-07-29 03:11:24 +08:00
|
|
|
case ISD::SETONE: return Mips::FCOND_NEQ;
|
|
|
|
case ISD::SETUEQ: return Mips::FCOND_UEQ;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2008-07-30 03:05:28 +08:00
|
|
|
MachineBasicBlock *
|
|
|
|
MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
|
2010-05-01 08:01:06 +08:00
|
|
|
MachineBasicBlock *BB) const {
|
2008-07-30 03:05:28 +08:00
|
|
|
const TargetInstrInfo *TII = getTargetMachine().getInstrInfo();
|
|
|
|
bool isFPCmp = false;
|
2009-02-13 10:34:39 +08:00
|
|
|
DebugLoc dl = MI->getDebugLoc();
|
2008-07-30 03:05:28 +08:00
|
|
|
|
|
|
|
switch (MI->getOpcode()) {
|
|
|
|
default: assert(false && "Unexpected instr type to insert");
|
|
|
|
case Mips::Select_FCC:
|
2009-03-21 08:05:07 +08:00
|
|
|
case Mips::Select_FCC_S32:
|
2008-07-30 03:05:28 +08:00
|
|
|
case Mips::Select_FCC_D32:
|
|
|
|
isFPCmp = true; // FALL THROUGH
|
|
|
|
case Mips::Select_CC:
|
2009-03-21 08:05:07 +08:00
|
|
|
case Mips::Select_CC_S32:
|
2008-07-30 03:05:28 +08:00
|
|
|
case Mips::Select_CC_D32: {
|
|
|
|
// To "insert" a SELECT_CC instruction, we actually have to insert the
|
|
|
|
// diamond control-flow pattern. The incoming instruction knows the
|
|
|
|
// destination vreg to set, the condition code register to branch on, the
|
|
|
|
// true/false values to select between, and a branch opcode to use.
|
|
|
|
const BasicBlock *LLVM_BB = BB->getBasicBlock();
|
|
|
|
MachineFunction::iterator It = BB;
|
|
|
|
++It;
|
|
|
|
|
|
|
|
// thisMBB:
|
|
|
|
// ...
|
|
|
|
// TrueVal = ...
|
|
|
|
// setcc r1, r2, r3
|
|
|
|
// bNE r1, r0, copy1MBB
|
|
|
|
// fallthrough --> copy0MBB
|
|
|
|
MachineBasicBlock *thisMBB = BB;
|
|
|
|
MachineFunction *F = BB->getParent();
|
|
|
|
MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
|
|
|
|
MachineBasicBlock *sinkMBB = F->CreateMachineBasicBlock(LLVM_BB);
|
2010-07-07 04:24:04 +08:00
|
|
|
F->insert(It, copy0MBB);
|
|
|
|
F->insert(It, sinkMBB);
|
|
|
|
|
|
|
|
// Transfer the remainder of BB and its successor edges to sinkMBB.
|
|
|
|
sinkMBB->splice(sinkMBB->begin(), BB,
|
|
|
|
llvm::next(MachineBasicBlock::iterator(MI)),
|
|
|
|
BB->end());
|
|
|
|
sinkMBB->transferSuccessorsAndUpdatePHIs(BB);
|
|
|
|
|
|
|
|
// Next, add the true and fallthrough blocks as its successors.
|
|
|
|
BB->addSuccessor(copy0MBB);
|
|
|
|
BB->addSuccessor(sinkMBB);
|
2008-07-30 03:05:28 +08:00
|
|
|
|
|
|
|
// Emit the right instruction according to the type of the operands compared
|
|
|
|
if (isFPCmp) {
|
|
|
|
// Find the condiction code present in the setcc operation.
|
|
|
|
Mips::CondCode CC = (Mips::CondCode)MI->getOperand(4).getImm();
|
|
|
|
// Get the branch opcode from the branch code.
|
|
|
|
unsigned Opc = FPBranchCodeToOpc(GetFPBranchCodeFromCond(CC));
|
2009-02-13 10:34:39 +08:00
|
|
|
BuildMI(BB, dl, TII->get(Opc)).addMBB(sinkMBB);
|
2008-07-30 03:05:28 +08:00
|
|
|
} else
|
2009-02-13 10:34:39 +08:00
|
|
|
BuildMI(BB, dl, TII->get(Mips::BNE)).addReg(MI->getOperand(1).getReg())
|
2008-07-30 03:05:28 +08:00
|
|
|
.addReg(Mips::ZERO).addMBB(sinkMBB);
|
|
|
|
|
|
|
|
// copy0MBB:
|
|
|
|
// %FalseValue = ...
|
|
|
|
// # fallthrough to sinkMBB
|
|
|
|
BB = copy0MBB;
|
|
|
|
|
|
|
|
// Update machine-CFG edges
|
|
|
|
BB->addSuccessor(sinkMBB);
|
|
|
|
|
|
|
|
// sinkMBB:
|
2010-07-20 15:58:51 +08:00
|
|
|
// %Result = phi [ %TrueValue, thisMBB ], [ %FalseValue, copy0MBB ]
|
2008-07-30 03:05:28 +08:00
|
|
|
// ...
|
|
|
|
BB = sinkMBB;
|
2010-07-07 04:24:04 +08:00
|
|
|
BuildMI(*BB, BB->begin(), dl,
|
|
|
|
TII->get(Mips::PHI), MI->getOperand(0).getReg())
|
2010-07-20 15:58:51 +08:00
|
|
|
.addReg(MI->getOperand(2).getReg()).addMBB(thisMBB)
|
|
|
|
.addReg(MI->getOperand(3).getReg()).addMBB(copy0MBB);
|
2008-07-30 03:05:28 +08:00
|
|
|
|
2010-07-07 04:24:04 +08:00
|
|
|
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
2008-07-30 03:05:28 +08:00
|
|
|
return BB;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Misc Lower Operation implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
2008-07-30 03:29:50 +08:00
|
|
|
|
2009-05-28 01:23:44 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const
|
2009-05-28 01:23:44 +08:00
|
|
|
{
|
|
|
|
if (!Subtarget->isMips1())
|
|
|
|
return Op;
|
|
|
|
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
unsigned CCReg = AddLiveIn(MF, Mips::FCR31, Mips::CCRRegisterClass);
|
|
|
|
|
|
|
|
SDValue Chain = DAG.getEntryNode();
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
SDValue Src = Op.getOperand(0);
|
|
|
|
|
|
|
|
// Set the condition register
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue CondReg = DAG.getCopyFromReg(Chain, dl, CCReg, MVT::i32);
|
2009-05-28 01:23:44 +08:00
|
|
|
CondReg = DAG.getCopyToReg(Chain, dl, Mips::AT, CondReg);
|
2009-08-12 04:47:22 +08:00
|
|
|
CondReg = DAG.getCopyFromReg(CondReg, dl, Mips::AT, MVT::i32);
|
2009-05-28 01:23:44 +08:00
|
|
|
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Cst = DAG.getConstant(3, MVT::i32);
|
|
|
|
SDValue Or = DAG.getNode(ISD::OR, dl, MVT::i32, CondReg, Cst);
|
|
|
|
Cst = DAG.getConstant(2, MVT::i32);
|
|
|
|
SDValue Xor = DAG.getNode(ISD::XOR, dl, MVT::i32, Or, Cst);
|
2009-05-28 01:23:44 +08:00
|
|
|
|
|
|
|
SDValue InFlag(0, 0);
|
|
|
|
CondReg = DAG.getCopyToReg(Chain, dl, Mips::FCR31, Xor, InFlag);
|
|
|
|
|
|
|
|
// Emit the round instruction and bit convert to integer
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Trunc = DAG.getNode(MipsISD::FPRound, dl, MVT::f32,
|
2009-05-28 01:23:44 +08:00
|
|
|
Src, CondReg.getValue(1));
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue BitCvt = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Trunc);
|
2009-05-28 01:23:44 +08:00
|
|
|
return BitCvt;
|
|
|
|
}
|
|
|
|
|
2008-08-08 03:08:11 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
|
2008-08-08 03:08:11 +08:00
|
|
|
{
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Size = Op.getOperand(1);
|
2009-02-05 07:02:30 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-08-08 03:08:11 +08:00
|
|
|
|
|
|
|
// Get a reference from Mips stack pointer
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue StackPointer = DAG.getCopyFromReg(Chain, dl, Mips::SP, MVT::i32);
|
2008-08-08 03:08:11 +08:00
|
|
|
|
|
|
|
// Subtract the dynamic size from the actual stack size to
|
|
|
|
// obtain the new stack size.
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Sub = DAG.getNode(ISD::SUB, dl, MVT::i32, StackPointer, Size);
|
2008-08-08 03:08:11 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// The Sub result contains the new stack start address, so it
|
2008-08-08 03:08:11 +08:00
|
|
|
// must be placed in the stack pointer register.
|
2009-02-05 07:02:30 +08:00
|
|
|
Chain = DAG.getCopyToReg(StackPointer.getValue(1), dl, Mips::SP, Sub);
|
2010-11-23 11:31:01 +08:00
|
|
|
|
|
|
|
// This node always has two return values: a new stack pointer
|
2008-08-08 03:08:11 +08:00
|
|
|
// value and a chain
|
|
|
|
SDValue Ops[2] = { Sub, Chain };
|
2009-02-05 07:02:30 +08:00
|
|
|
return DAG.getMergeValues(Ops, 2, dl);
|
2008-08-08 03:08:11 +08:00
|
|
|
}
|
|
|
|
|
2008-08-01 02:31:28 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerANDOR(SDValue Op, SelectionDAG &DAG) const
|
2008-08-01 02:31:28 +08:00
|
|
|
{
|
|
|
|
SDValue LHS = Op.getOperand(0);
|
|
|
|
SDValue RHS = Op.getOperand(1);
|
2009-02-07 05:50:26 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
|
|
|
|
2008-08-01 02:31:28 +08:00
|
|
|
if (LHS.getOpcode() != MipsISD::FPCmp || RHS.getOpcode() != MipsISD::FPCmp)
|
|
|
|
return Op;
|
|
|
|
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue True = DAG.getConstant(1, MVT::i32);
|
|
|
|
SDValue False = DAG.getConstant(0, MVT::i32);
|
2008-08-01 02:31:28 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue LSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
|
2008-08-01 02:31:28 +08:00
|
|
|
LHS, True, False, LHS.getOperand(2));
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue RSEL = DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
|
2008-08-01 02:31:28 +08:00
|
|
|
RHS, True, False, RHS.getOperand(2));
|
|
|
|
|
2009-08-12 04:47:22 +08:00
|
|
|
return DAG.getNode(Op.getOpcode(), dl, MVT::i32, LSEL, RSEL);
|
2008-08-01 02:31:28 +08:00
|
|
|
}
|
|
|
|
|
2008-07-29 03:11:24 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerBRCOND(SDValue Op, SelectionDAG &DAG) const
|
2008-07-29 03:11:24 +08:00
|
|
|
{
|
2010-11-23 11:31:01 +08:00
|
|
|
// The first operand is the chain, the second is the condition, the third is
|
2008-07-29 03:11:24 +08:00
|
|
|
// the block to branch to if the condition is true.
|
|
|
|
SDValue Chain = Op.getOperand(0);
|
|
|
|
SDValue Dest = Op.getOperand(2);
|
2009-02-07 05:50:26 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-08-01 02:31:28 +08:00
|
|
|
|
|
|
|
if (Op.getOperand(1).getOpcode() != MipsISD::FPCmp)
|
2008-07-31 01:06:13 +08:00
|
|
|
return Op;
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2008-08-01 02:31:28 +08:00
|
|
|
SDValue CondRes = Op.getOperand(1);
|
|
|
|
SDValue CCNode = CondRes.getOperand(2);
|
2008-09-13 00:56:44 +08:00
|
|
|
Mips::CondCode CC =
|
|
|
|
(Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue();
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue BrCode = DAG.getConstant(GetFPBranchCodeFromCond(CC), MVT::i32);
|
2008-07-29 03:11:24 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
return DAG.getNode(MipsISD::FPBrcond, dl, Op.getValueType(), Chain, BrCode,
|
2008-07-29 03:11:24 +08:00
|
|
|
Dest, CondRes);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerSETCC(SDValue Op, SelectionDAG &DAG) const
|
2008-07-29 03:11:24 +08:00
|
|
|
{
|
2010-11-23 11:31:01 +08:00
|
|
|
// The operands to this are the left and right operands to compare (ops #0,
|
|
|
|
// and #1) and the condition code to compare them with (op #2) as a
|
2008-07-29 03:11:24 +08:00
|
|
|
// CondCodeSDNode.
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue LHS = Op.getOperand(0);
|
2009-02-07 05:50:26 +08:00
|
|
|
SDValue RHS = Op.getOperand(1);
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-07-29 03:11:24 +08:00
|
|
|
|
|
|
|
ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
|
2010-11-23 11:31:01 +08:00
|
|
|
|
|
|
|
return DAG.getNode(MipsISD::FPCmp, dl, Op.getValueType(), LHS, RHS,
|
2009-08-12 04:47:22 +08:00
|
|
|
DAG.getConstant(FPCondCCodeToFCC(CC), MVT::i32));
|
2008-07-29 03:11:24 +08:00
|
|
|
}
|
|
|
|
|
2008-07-30 03:05:28 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerSELECT(SDValue Op, SelectionDAG &DAG) const
|
2008-07-30 03:05:28 +08:00
|
|
|
{
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue Cond = Op.getOperand(0);
|
2008-07-30 03:05:28 +08:00
|
|
|
SDValue True = Op.getOperand(1);
|
|
|
|
SDValue False = Op.getOperand(2);
|
2009-02-07 05:50:26 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-07-30 03:05:28 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// if the incomming condition comes from a integer compare, the select
|
|
|
|
// operation must be SelectCC or a conditional move if the subtarget
|
2008-08-13 15:13:40 +08:00
|
|
|
// supports it.
|
|
|
|
if (Cond.getOpcode() != MipsISD::FPCmp) {
|
|
|
|
if (Subtarget->hasCondMov() && !True.getValueType().isFloatingPoint())
|
|
|
|
return Op;
|
2010-11-23 11:31:01 +08:00
|
|
|
return DAG.getNode(MipsISD::SelectCC, dl, True.getValueType(),
|
2008-08-01 02:31:28 +08:00
|
|
|
Cond, True, False);
|
2008-08-13 15:13:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// if the incomming condition comes from fpcmp, the select
|
|
|
|
// operation must use FPSelectCC.
|
2008-08-01 02:31:28 +08:00
|
|
|
SDValue CCNode = Cond.getOperand(2);
|
2010-11-23 11:31:01 +08:00
|
|
|
return DAG.getNode(MipsISD::FPSelectCC, dl, True.getValueType(),
|
2008-08-01 02:31:28 +08:00
|
|
|
Cond, True, False, CCNode);
|
2008-07-30 03:05:28 +08:00
|
|
|
}
|
|
|
|
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue MipsTargetLowering::LowerGlobalAddress(SDValue Op,
|
|
|
|
SelectionDAG &DAG) const {
|
2009-02-07 05:50:26 +08:00
|
|
|
// FIXME there isn't actually debug info here
|
2009-02-05 04:06:27 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2010-04-15 09:51:59 +08:00
|
|
|
const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
|
2008-07-30 03:29:50 +08:00
|
|
|
|
2009-08-03 10:22:28 +08:00
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
2009-08-13 13:41:27 +08:00
|
|
|
SDVTList VTs = DAG.getVTList(MVT::i32);
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2009-08-13 14:28:06 +08:00
|
|
|
MipsTargetObjectFile &TLOF = (MipsTargetObjectFile&)getObjFileLowering();
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2009-08-13 13:41:27 +08:00
|
|
|
// %gp_rel relocation
|
2010-11-23 11:31:01 +08:00
|
|
|
if (TLOF.IsGlobalInSmallSection(GV, getTargetMachine())) {
|
|
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
2009-09-02 01:27:58 +08:00
|
|
|
MipsII::MO_GPREL);
|
2009-08-13 13:41:27 +08:00
|
|
|
SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, dl, VTs, &GA, 1);
|
|
|
|
SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
|
2010-11-23 11:31:01 +08:00
|
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, GOT, GPRelNode);
|
2009-08-13 13:41:27 +08:00
|
|
|
}
|
2008-07-30 03:29:50 +08:00
|
|
|
// %hi/%lo relocation
|
2010-07-07 06:08:15 +08:00
|
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
2009-09-02 01:27:58 +08:00
|
|
|
MipsII::MO_ABS_HILO);
|
2009-08-13 13:41:27 +08:00
|
|
|
SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, VTs, &GA, 1);
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
|
|
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
|
2008-07-30 03:29:50 +08:00
|
|
|
|
2009-09-02 01:27:58 +08:00
|
|
|
} else {
|
2010-07-07 06:08:15 +08:00
|
|
|
SDValue GA = DAG.getTargetGlobalAddress(GV, dl, MVT::i32, 0,
|
2009-09-02 01:27:58 +08:00
|
|
|
MipsII::MO_GOT);
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue ResNode = DAG.getLoad(MVT::i32, dl,
|
2010-09-21 14:44:06 +08:00
|
|
|
DAG.getEntryNode(), GA, MachinePointerInfo(),
|
2010-02-16 00:56:10 +08:00
|
|
|
false, false, 0);
|
2008-07-30 03:29:50 +08:00
|
|
|
// On functions and global targets not internal linked only
|
|
|
|
// a load from got/GP is necessary for PIC to work.
|
2009-01-16 04:18:42 +08:00
|
|
|
if (!GV->hasLocalLinkage() || isa<Function>(GV))
|
2008-07-30 03:29:50 +08:00
|
|
|
return ResNode;
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, GA);
|
|
|
|
return DAG.getNode(ISD::ADD, dl, MVT::i32, ResNode, Lo);
|
2008-07-30 03:29:50 +08:00
|
|
|
}
|
|
|
|
|
2009-07-15 00:55:14 +08:00
|
|
|
llvm_unreachable("Dont know how to handle GlobalAddress");
|
2008-07-30 03:29:50 +08:00
|
|
|
return SDValue(0,0);
|
|
|
|
}
|
|
|
|
|
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
|
2008-07-30 03:29:50 +08:00
|
|
|
{
|
2009-07-15 00:55:14 +08:00
|
|
|
llvm_unreachable("TLS not implemented for MIPS.");
|
2008-07-30 03:29:50 +08:00
|
|
|
return SDValue(); // Not reached
|
|
|
|
}
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerJumpTable(SDValue Op, SelectionDAG &DAG) const
|
2007-11-13 03:49:57 +08:00
|
|
|
{
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue ResNode;
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue HiPart;
|
2009-02-07 05:50:26 +08:00
|
|
|
// FIXME there isn't actually debug info here
|
2009-02-05 04:06:27 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2009-09-02 01:27:58 +08:00
|
|
|
bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
|
|
|
|
unsigned char OpFlag = IsPIC ? MipsII::MO_GOT : MipsII::MO_ABS_HILO;
|
2007-11-13 03:49:57 +08:00
|
|
|
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT PtrVT = Op.getValueType();
|
2007-11-13 03:49:57 +08:00
|
|
|
JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
|
|
|
|
|
2009-09-02 01:27:58 +08:00
|
|
|
SDValue JTI = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, OpFlag);
|
|
|
|
|
2010-07-20 16:37:04 +08:00
|
|
|
if (!IsPIC) {
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Ops[] = { JTI };
|
2009-09-02 01:27:58 +08:00
|
|
|
HiPart = DAG.getNode(MipsISD::Hi, dl, DAG.getVTList(MVT::i32), Ops, 1);
|
2007-11-13 03:49:57 +08:00
|
|
|
} else // Emit Load from Global Pointer
|
2010-09-21 14:44:06 +08:00
|
|
|
HiPart = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(), JTI,
|
|
|
|
MachinePointerInfo(),
|
2010-02-16 00:56:10 +08:00
|
|
|
false, false, 0);
|
2007-11-13 03:49:57 +08:00
|
|
|
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTI);
|
|
|
|
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
|
2007-11-13 03:49:57 +08:00
|
|
|
|
|
|
|
return ResNode;
|
|
|
|
}
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue MipsTargetLowering::
|
2010-04-17 23:26:15 +08:00
|
|
|
LowerConstantPool(SDValue Op, SelectionDAG &DAG) const
|
2008-07-09 12:15:08 +08:00
|
|
|
{
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue ResNode;
|
2008-07-24 00:01:50 +08:00
|
|
|
ConstantPoolSDNode *N = cast<ConstantPoolSDNode>(Op);
|
2010-04-15 09:51:59 +08:00
|
|
|
const Constant *C = N->getConstVal();
|
2009-02-07 05:50:26 +08:00
|
|
|
// FIXME there isn't actually debug info here
|
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2008-07-24 00:01:50 +08:00
|
|
|
|
|
|
|
// gp_rel relocation
|
2010-11-23 11:31:01 +08:00
|
|
|
// FIXME: we should reference the constant pool using small data sections,
|
2008-07-29 03:26:25 +08:00
|
|
|
// but the asm printer currently doens't support this feature without
|
2010-11-23 11:31:01 +08:00
|
|
|
// hacking it. This feature should come soon so we can uncomment the
|
2008-07-29 03:26:25 +08:00
|
|
|
// stuff below.
|
2009-08-03 10:22:28 +08:00
|
|
|
//if (IsInSmallSection(C->getType())) {
|
2009-08-12 04:47:22 +08:00
|
|
|
// SDValue GPRelNode = DAG.getNode(MipsISD::GPRel, MVT::i32, CP);
|
|
|
|
// SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(MVT::i32);
|
2010-11-23 11:31:01 +08:00
|
|
|
// ResNode = DAG.getNode(ISD::ADD, MVT::i32, GOT, GPRelNode);
|
2009-11-25 20:17:58 +08:00
|
|
|
|
|
|
|
if (getTargetMachine().getRelocationModel() != Reloc::PIC_) {
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
|
2009-11-25 20:17:58 +08:00
|
|
|
N->getOffset(), MipsII::MO_ABS_HILO);
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CP);
|
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
|
|
|
|
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo);
|
2009-11-25 20:17:58 +08:00
|
|
|
} else {
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue CP = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(),
|
2009-11-25 20:17:58 +08:00
|
|
|
N->getOffset(), MipsII::MO_GOT);
|
2010-11-23 11:31:01 +08:00
|
|
|
SDValue Load = DAG.getLoad(MVT::i32, dl, DAG.getEntryNode(),
|
2010-09-21 14:44:06 +08:00
|
|
|
CP, MachinePointerInfo::getConstantPool(),
|
|
|
|
false, false, 0);
|
2009-11-25 20:17:58 +08:00
|
|
|
SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CP);
|
|
|
|
ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo);
|
|
|
|
}
|
2008-07-24 00:01:50 +08:00
|
|
|
|
|
|
|
return ResNode;
|
2008-07-09 12:15:08 +08:00
|
|
|
}
|
|
|
|
|
2010-04-17 23:26:15 +08:00
|
|
|
SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const {
|
2010-04-17 22:41:14 +08:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *FuncInfo = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
|
2010-02-07 05:00:02 +08:00
|
|
|
DebugLoc dl = Op.getDebugLoc();
|
2010-04-17 22:41:14 +08:00
|
|
|
SDValue FI = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(),
|
|
|
|
getPointerTy());
|
2010-02-07 05:00:02 +08:00
|
|
|
|
|
|
|
// vastart just stores the address of the VarArgsFrameIndex slot into the
|
|
|
|
// memory location argument.
|
|
|
|
const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
|
2010-09-22 01:50:43 +08:00
|
|
|
return DAG.getStore(Op.getOperand(0), dl, FI, Op.getOperand(1),
|
|
|
|
MachinePointerInfo(SV),
|
2010-02-16 00:56:10 +08:00
|
|
|
false, false, 0);
|
2010-02-07 05:00:02 +08:00
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
#include "MipsGenCallingConv.inc"
|
|
|
|
|
2009-03-19 10:12:28 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2010-11-23 11:31:01 +08:00
|
|
|
// TODO: Implement a generic logic using tblgen that can support this.
|
2009-03-19 10:12:28 +08:00
|
|
|
// Mips O32 ABI rules:
|
|
|
|
// ---
|
|
|
|
// i32 - Passed in A0, A1, A2, A3 and stack
|
2010-11-23 11:31:01 +08:00
|
|
|
// f32 - Only passed in f32 registers if no int reg has been used yet to hold
|
2009-03-19 10:12:28 +08:00
|
|
|
// an argument. Otherwise, passed in A1, A2, A3 and stack.
|
2010-11-23 11:31:01 +08:00
|
|
|
// f64 - Only passed in two aliased f32 registers if no int reg has been used
|
|
|
|
// yet to hold an argument. Otherwise, use A2, A3 and stack. If A1 is
|
2009-03-19 10:12:28 +08:00
|
|
|
// not used, it must be shadowed. If only A3 is avaiable, shadow it and
|
|
|
|
// go to stack.
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2010-11-04 18:49:57 +08:00
|
|
|
static bool CC_MipsO32(unsigned ValNo, MVT ValVT,
|
2010-11-03 19:35:31 +08:00
|
|
|
MVT LocVT, CCValAssign::LocInfo LocInfo,
|
2009-03-19 10:12:28 +08:00
|
|
|
ISD::ArgFlagsTy ArgFlags, CCState &State) {
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
static const unsigned IntRegsSize=4, FloatRegsSize=2;
|
2009-03-19 10:12:28 +08:00
|
|
|
|
|
|
|
static const unsigned IntRegs[] = {
|
|
|
|
Mips::A0, Mips::A1, Mips::A2, Mips::A3
|
|
|
|
};
|
|
|
|
static const unsigned F32Regs[] = {
|
|
|
|
Mips::F12, Mips::F14
|
|
|
|
};
|
|
|
|
static const unsigned F64Regs[] = {
|
|
|
|
Mips::D6, Mips::D7
|
|
|
|
};
|
|
|
|
|
2011-02-11 02:05:10 +08:00
|
|
|
unsigned Reg = 0;
|
|
|
|
static bool IntRegUsed = false;
|
|
|
|
|
|
|
|
// This must be the first arg of the call if no regs have been allocated.
|
|
|
|
// Initialize IntRegUsed in that case.
|
|
|
|
if (IntRegs[State.getFirstUnallocated(IntRegs, IntRegsSize)] == Mips::A0 &&
|
|
|
|
F32Regs[State.getFirstUnallocated(F32Regs, FloatRegsSize)] == Mips::F12 &&
|
|
|
|
F64Regs[State.getFirstUnallocated(F64Regs, FloatRegsSize)] == Mips::D6)
|
|
|
|
IntRegUsed = false;
|
2009-03-19 10:12:28 +08:00
|
|
|
|
|
|
|
// Promote i8 and i16
|
2009-08-12 04:47:22 +08:00
|
|
|
if (LocVT == MVT::i8 || LocVT == MVT::i16) {
|
|
|
|
LocVT = MVT::i32;
|
2009-03-19 10:12:28 +08:00
|
|
|
if (ArgFlags.isSExt())
|
|
|
|
LocInfo = CCValAssign::SExt;
|
|
|
|
else if (ArgFlags.isZExt())
|
|
|
|
LocInfo = CCValAssign::ZExt;
|
|
|
|
else
|
|
|
|
LocInfo = CCValAssign::AExt;
|
|
|
|
}
|
|
|
|
|
2011-02-11 02:05:10 +08:00
|
|
|
if (ValVT == MVT::i32) {
|
2009-03-19 10:12:28 +08:00
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
IntRegUsed = true;
|
2011-02-11 02:05:10 +08:00
|
|
|
} else if (ValVT == MVT::f32) {
|
|
|
|
// An int reg has to be marked allocated regardless of whether or not
|
|
|
|
// IntRegUsed is true.
|
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
2009-03-19 10:12:28 +08:00
|
|
|
|
2011-02-11 02:05:10 +08:00
|
|
|
if (IntRegUsed) {
|
|
|
|
if (Reg) // Int reg is available
|
|
|
|
LocVT = MVT::i32;
|
|
|
|
} else {
|
|
|
|
unsigned FReg = State.AllocateReg(F32Regs, FloatRegsSize);
|
|
|
|
if (FReg) // F32 reg is available
|
|
|
|
Reg = FReg;
|
|
|
|
else if (Reg) // No F32 regs are available, but an int reg is available.
|
|
|
|
LocVT = MVT::i32;
|
2010-11-23 11:31:01 +08:00
|
|
|
}
|
2011-02-11 02:05:10 +08:00
|
|
|
} else if (ValVT == MVT::f64) {
|
|
|
|
// Int regs have to be marked allocated regardless of whether or not
|
|
|
|
// IntRegUsed is true.
|
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
if (Reg == Mips::A1)
|
|
|
|
Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
else if (Reg == Mips::A3)
|
|
|
|
Reg = 0;
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
|
|
|
|
// At this point, Reg is A0, A2 or 0, and all the unavailable integer regs
|
|
|
|
// are marked as allocated.
|
|
|
|
if (IntRegUsed) {
|
|
|
|
if (Reg)// if int reg is available
|
|
|
|
LocVT = MVT::i32;
|
|
|
|
} else {
|
|
|
|
unsigned FReg = State.AllocateReg(F64Regs, FloatRegsSize);
|
|
|
|
if (FReg) // F64 reg is available.
|
|
|
|
Reg = FReg;
|
|
|
|
else if (Reg) // No F64 regs are available, but an int reg is available.
|
|
|
|
LocVT = MVT::i32;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
assert(false && "cannot handle this ValVT");
|
2009-03-19 10:12:28 +08:00
|
|
|
|
|
|
|
if (!Reg) {
|
|
|
|
unsigned SizeInBytes = ValVT.getSizeInBits() >> 3;
|
|
|
|
unsigned Offset = State.AllocateStack(SizeInBytes, SizeInBytes);
|
|
|
|
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
|
|
|
|
} else
|
|
|
|
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, LocVT, LocInfo));
|
|
|
|
|
|
|
|
return false; // CC must always match
|
|
|
|
}
|
|
|
|
|
2010-11-04 18:49:57 +08:00
|
|
|
static bool CC_MipsO32_VarArgs(unsigned ValNo, MVT ValVT,
|
2010-11-03 19:35:31 +08:00
|
|
|
MVT LocVT, CCValAssign::LocInfo LocInfo,
|
2010-02-07 03:20:49 +08:00
|
|
|
ISD::ArgFlagsTy ArgFlags, CCState &State) {
|
|
|
|
|
|
|
|
static const unsigned IntRegsSize=4;
|
|
|
|
|
|
|
|
static const unsigned IntRegs[] = {
|
|
|
|
Mips::A0, Mips::A1, Mips::A2, Mips::A3
|
|
|
|
};
|
|
|
|
|
|
|
|
// Promote i8 and i16
|
|
|
|
if (LocVT == MVT::i8 || LocVT == MVT::i16) {
|
|
|
|
LocVT = MVT::i32;
|
|
|
|
if (ArgFlags.isSExt())
|
|
|
|
LocInfo = CCValAssign::SExt;
|
|
|
|
else if (ArgFlags.isZExt())
|
|
|
|
LocInfo = CCValAssign::ZExt;
|
|
|
|
else
|
|
|
|
LocInfo = CCValAssign::AExt;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (ValVT == MVT::i32 || ValVT == MVT::f32) {
|
|
|
|
if (unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize)) {
|
|
|
|
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
unsigned Off = State.AllocateStack(4, 4);
|
|
|
|
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned UnallocIntReg = State.getFirstUnallocated(IntRegs, IntRegsSize);
|
|
|
|
if (ValVT == MVT::f64) {
|
|
|
|
if (IntRegs[UnallocIntReg] == (unsigned (Mips::A1))) {
|
|
|
|
// A1 can't be used anymore, because 64 bit arguments
|
|
|
|
// must be aligned when copied back to the caller stack
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
UnallocIntReg++;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (IntRegs[UnallocIntReg] == (unsigned (Mips::A0)) ||
|
|
|
|
IntRegs[UnallocIntReg] == (unsigned (Mips::A2))) {
|
|
|
|
unsigned Reg = State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
State.addLoc(CCValAssign::getReg(ValNo, ValVT, Reg, MVT::i32, LocInfo));
|
2010-11-23 11:31:01 +08:00
|
|
|
// Shadow the next register so it can be used
|
2010-02-07 03:20:49 +08:00
|
|
|
// later to get the other 32bit part.
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Register is shadowed to preserve alignment, and the
|
|
|
|
// argument goes to a stack location.
|
|
|
|
if (UnallocIntReg != IntRegsSize)
|
|
|
|
State.AllocateReg(IntRegs, IntRegsSize);
|
|
|
|
|
|
|
|
unsigned Off = State.AllocateStack(8, 8);
|
|
|
|
State.addLoc(CCValAssign::getMem(ValNo, ValVT, Off, LocVT, LocInfo));
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
return true; // CC didn't match
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
// Call Calling Convention Implementation
|
2007-06-06 15:42:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
/// LowerCall - functions arguments are copied from virtual regs to
|
2009-01-26 11:15:54 +08:00
|
|
|
/// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
|
2010-02-07 03:20:49 +08:00
|
|
|
/// TODO: isTailCall.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue
|
2010-02-03 07:55:14 +08:00
|
|
|
MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
2010-01-27 08:07:07 +08:00
|
|
|
bool &isTailCall,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 23:54:55 +08:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const {
|
2010-01-27 08:07:07 +08:00
|
|
|
// MIPs target does not yet support tail call optimization.
|
|
|
|
isTailCall = false;
|
2007-07-12 07:16:16 +08:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-07-12 07:16:16 +08:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2009-09-02 01:27:58 +08:00
|
|
|
bool IsPIC = getTargetMachine().getRelocationModel() == Reloc::PIC_;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Analyze operands of the call, assigning locations to each operand.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
CCState CCInfo(CallConv, isVarArg, getTargetMachine(), ArgLocs,
|
|
|
|
*DAG.getContext());
|
2007-07-12 07:16:16 +08:00
|
|
|
|
2008-07-15 10:03:36 +08:00
|
|
|
// To meet O32 ABI, Mips must always allocate 16 bytes on
|
2007-07-12 07:16:16 +08:00
|
|
|
// the stack (even if less than 4 are used as arguments)
|
2008-07-15 10:03:36 +08:00
|
|
|
if (Subtarget->isABI_O32()) {
|
2010-11-04 18:49:57 +08:00
|
|
|
int VTsize = MVT(MVT::i32).getSizeInBits()/8;
|
2010-07-03 08:40:23 +08:00
|
|
|
MFI->CreateFixedObject(VTsize, (VTsize*3), true);
|
2010-11-23 11:31:01 +08:00
|
|
|
CCInfo.AnalyzeCallOperands(Outs,
|
2010-02-07 03:20:49 +08:00
|
|
|
isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
|
2009-03-19 10:12:28 +08:00
|
|
|
} else
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
CCInfo.AnalyzeCallOperands(Outs, CC_Mips);
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Get a count of how many bytes are to be pushed on the stack.
|
|
|
|
unsigned NumBytes = CCInfo.getNextStackOffset();
|
2008-10-12 06:08:30 +08:00
|
|
|
Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// With EABI is it possible to have 16 args on registers.
|
2008-07-28 05:46:04 +08:00
|
|
|
SmallVector<std::pair<unsigned, SDValue>, 16> RegsToPass;
|
|
|
|
SmallVector<SDValue, 8> MemOpChains;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// First/LastArgStackLoc contains the first/last
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// "at stack" argument location.
|
|
|
|
int LastArgStackLoc = 0;
|
|
|
|
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Walk the register/memloc assignments, inserting copies/loads.
|
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
2010-07-07 23:54:55 +08:00
|
|
|
SDValue Arg = OutVals[i];
|
2007-06-06 15:42:06 +08:00
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
|
|
|
|
// Promote the value if needed.
|
|
|
|
switch (VA.getLocInfo()) {
|
2009-07-15 00:55:14 +08:00
|
|
|
default: llvm_unreachable("Unknown loc info!");
|
2010-11-23 11:31:01 +08:00
|
|
|
case CCValAssign::Full:
|
2009-03-19 10:12:28 +08:00
|
|
|
if (Subtarget->isABI_O32() && VA.isRegLoc()) {
|
2009-08-12 04:47:22 +08:00
|
|
|
if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i32)
|
2010-11-23 11:31:01 +08:00
|
|
|
Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i32, Arg);
|
2009-08-12 04:47:22 +08:00
|
|
|
if (VA.getValVT() == MVT::f64 && VA.getLocVT() == MVT::i32) {
|
2010-11-23 11:31:01 +08:00
|
|
|
Arg = DAG.getNode(ISD::BITCAST, dl, MVT::i64, Arg);
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
|
2009-03-19 10:12:28 +08:00
|
|
|
DAG.getConstant(0, getPointerTy()));
|
2009-08-12 04:47:22 +08:00
|
|
|
SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32, Arg,
|
2009-03-19 10:12:28 +08:00
|
|
|
DAG.getConstant(1, getPointerTy()));
|
|
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Lo));
|
|
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg()+1, Hi));
|
|
|
|
continue;
|
2010-11-23 11:31:01 +08:00
|
|
|
}
|
2009-03-19 10:12:28 +08:00
|
|
|
}
|
|
|
|
break;
|
2008-03-17 14:57:02 +08:00
|
|
|
case CCValAssign::SExt:
|
2009-02-05 04:06:27 +08:00
|
|
|
Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
|
2008-03-17 14:57:02 +08:00
|
|
|
break;
|
|
|
|
case CCValAssign::ZExt:
|
2009-02-05 04:06:27 +08:00
|
|
|
Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
|
2008-03-17 14:57:02 +08:00
|
|
|
break;
|
|
|
|
case CCValAssign::AExt:
|
2009-02-05 04:06:27 +08:00
|
|
|
Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
|
2008-03-17 14:57:02 +08:00
|
|
|
break;
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2010-11-23 11:31:01 +08:00
|
|
|
|
|
|
|
// Arguments that can be passed on register must be kept at
|
2007-11-05 11:02:32 +08:00
|
|
|
// RegsToPass vector
|
2007-06-06 15:42:06 +08:00
|
|
|
if (VA.isRegLoc()) {
|
|
|
|
RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
|
2008-03-17 14:57:02 +08:00
|
|
|
continue;
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2009-03-19 10:12:28 +08:00
|
|
|
// Register can't get to this point...
|
2008-03-17 14:57:02 +08:00
|
|
|
assert(VA.isMemLoc());
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2008-03-17 14:57:02 +08:00
|
|
|
// Create the frame index object for this incoming parameter
|
|
|
|
// This guarantees that when allocating Local Area the firsts
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// 16 bytes which are alwayes reserved won't be overwritten
|
|
|
|
// if O32 ABI is used. For EABI the first address is zero.
|
|
|
|
LastArgStackLoc = (FirstStackArgLoc + VA.getLocMemOffset());
|
2008-06-06 20:08:01 +08:00
|
|
|
int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
|
2010-07-03 08:40:23 +08:00
|
|
|
LastArgStackLoc, true);
|
2008-03-17 14:57:02 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue PtrOff = DAG.getFrameIndex(FI,getPointerTy());
|
2008-03-17 14:57:02 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// emit ISD::STORE whichs stores the
|
2008-03-17 14:57:02 +08:00
|
|
|
// parameter value to a stack Location
|
2010-09-22 01:50:43 +08:00
|
|
|
MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
|
|
|
|
MachinePointerInfo(),
|
2010-02-16 00:56:10 +08:00
|
|
|
false, false, 0));
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// Transform all store nodes into one single node because all store
|
|
|
|
// nodes are independent of each other.
|
2010-11-23 11:31:01 +08:00
|
|
|
if (!MemOpChains.empty())
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
2007-06-06 15:42:06 +08:00
|
|
|
&MemOpChains[0], MemOpChains.size());
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// Build a sequence of copy-to-reg nodes chained together with token
|
2007-06-06 15:42:06 +08:00
|
|
|
// chain and flag operands which copy the outgoing args into registers.
|
|
|
|
// The InFlag in necessary since all emited instructions must be
|
|
|
|
// stuck together.
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue InFlag;
|
2007-06-06 15:42:06 +08:00
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
|
2010-11-23 11:31:01 +08:00
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
|
2007-06-06 15:42:06 +08:00
|
|
|
RegsToPass[i].second, InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2008-09-17 05:48:12 +08:00
|
|
|
// If the callee is a GlobalAddress/ExternalSymbol node (quite common, every
|
2010-11-23 11:31:01 +08:00
|
|
|
// direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol
|
|
|
|
// node so that legalize doesn't hack it.
|
2009-09-02 01:27:58 +08:00
|
|
|
unsigned char OpFlag = IsPIC ? MipsII::MO_GOT_CALL : MipsII::MO_NO_FLAG;
|
2010-11-23 11:31:01 +08:00
|
|
|
if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
|
|
|
|
Callee = DAG.getTargetGlobalAddress(G->getGlobal(), dl,
|
2009-09-02 01:27:58 +08:00
|
|
|
getPointerTy(), 0, OpFlag);
|
2008-09-17 05:48:12 +08:00
|
|
|
else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(Callee))
|
2010-11-23 11:31:01 +08:00
|
|
|
Callee = DAG.getTargetExternalSymbol(S->getSymbol(),
|
2009-09-02 01:27:58 +08:00
|
|
|
getPointerTy(), OpFlag);
|
2008-09-17 05:48:12 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// MipsJmpLink = #chain, #target_address, #opt_in_flags...
|
2010-11-23 11:31:01 +08:00
|
|
|
// = Chain, Callee, Reg#1, Reg#2, ...
|
2007-06-06 15:42:06 +08:00
|
|
|
//
|
|
|
|
// Returns a chain & a flag for retval copy to use.
|
2010-12-21 10:38:05 +08:00
|
|
|
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
|
2008-07-28 05:46:04 +08:00
|
|
|
SmallVector<SDValue, 8> Ops;
|
2007-06-06 15:42:06 +08:00
|
|
|
Ops.push_back(Chain);
|
|
|
|
Ops.push_back(Callee);
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// Add argument registers to the end of the list so that they are
|
2007-06-06 15:42:06 +08:00
|
|
|
// known live into the call.
|
|
|
|
for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
|
|
|
|
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
|
|
|
|
RegsToPass[i].second.getValueType()));
|
|
|
|
|
2008-08-29 05:40:38 +08:00
|
|
|
if (InFlag.getNode())
|
2007-06-06 15:42:06 +08:00
|
|
|
Ops.push_back(InFlag);
|
|
|
|
|
2009-02-05 04:06:27 +08:00
|
|
|
Chain = DAG.getNode(MipsISD::JmpLink, dl, NodeTys, &Ops[0], Ops.size());
|
2007-06-06 15:42:06 +08:00
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// Create a stack location to hold GP when PIC is used. This stack
|
|
|
|
// location is used on function prologue to save GP and also after all
|
|
|
|
// emited CALL's to restore GP.
|
2009-09-02 01:27:58 +08:00
|
|
|
if (IsPIC) {
|
2010-11-23 11:31:01 +08:00
|
|
|
// Function can have an arbitrary number of calls, so
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// hold the LastArgStackLoc with the biggest offset.
|
2007-11-05 11:02:32 +08:00
|
|
|
int FI;
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if (LastArgStackLoc >= MipsFI->getGPStackOffset()) {
|
|
|
|
LastArgStackLoc = (!LastArgStackLoc) ? (16) : (LastArgStackLoc+4);
|
2010-11-23 11:31:01 +08:00
|
|
|
// Create the frame index only once. SPOffset here can be anything
|
2007-11-05 11:02:32 +08:00
|
|
|
// (this will be fixed on processFunctionBeforeFrameFinalized)
|
|
|
|
if (MipsFI->getGPStackOffset() == -1) {
|
2010-07-03 08:40:23 +08:00
|
|
|
FI = MFI->CreateFixedObject(4, 0, true);
|
2007-11-05 11:02:32 +08:00
|
|
|
MipsFI->setGPFI(FI);
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
MipsFI->setGPStackOffset(LastArgStackLoc);
|
2007-11-05 11:02:32 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// Reload GP value.
|
|
|
|
FI = MipsFI->getGPFI();
|
2010-09-21 14:44:06 +08:00
|
|
|
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
|
|
|
|
SDValue GPLoad = DAG.getLoad(MVT::i32, dl, Chain, FIN,
|
|
|
|
MachinePointerInfo::getFixedStack(FI),
|
2010-02-16 00:56:10 +08:00
|
|
|
false, false, 0);
|
2007-11-05 11:02:32 +08:00
|
|
|
Chain = GPLoad.getValue(1);
|
2010-11-23 11:31:01 +08:00
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, DAG.getRegister(Mips::GP, MVT::i32),
|
2008-07-28 05:46:04 +08:00
|
|
|
GPLoad, SDValue(0,0));
|
2008-06-01 11:49:39 +08:00
|
|
|
InFlag = Chain.getValue(1);
|
2010-11-23 11:31:01 +08:00
|
|
|
}
|
2007-11-05 11:02:32 +08:00
|
|
|
|
2010-01-31 02:32:07 +08:00
|
|
|
// Create the CALLSEQ_END node.
|
|
|
|
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(NumBytes, true),
|
|
|
|
DAG.getIntPtrConstant(0, true), InFlag);
|
|
|
|
InFlag = Chain.getValue(1);
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Handle result values, copying them out of physregs into vregs that we
|
|
|
|
// return.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
return LowerCallResult(Chain, InFlag, CallConv, isVarArg,
|
|
|
|
Ins, dl, DAG, InVals);
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
/// LowerCallResult - Lower the result values of a call into the
|
|
|
|
/// appropriate copies out of appropriate physical registers.
|
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::InputArg> &Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals) const {
|
2007-07-12 07:16:16 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Assign locations to each value returned by this call.
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
|
2009-07-22 08:24:57 +08:00
|
|
|
RVLocs, *DAG.getContext());
|
2007-07-12 07:16:16 +08:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
CCInfo.AnalyzeCallResult(Ins, RetCC_Mips);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Copy all of the result registers out of their specified physreg.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
2009-02-05 04:06:27 +08:00
|
|
|
Chain = DAG.getCopyFromReg(Chain, dl, RVLocs[i].getLocReg(),
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
RVLocs[i].getValVT(), InFlag).getValue(1);
|
2007-06-06 15:42:06 +08:00
|
|
|
InFlag = Chain.getValue(2);
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
InVals.push_back(Chain.getValue(0));
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2007-11-05 11:02:32 +08:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
return Chain;
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
// Formal Arguments Calling Convention Implementation
|
2007-06-06 15:42:06 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
/// LowerFormalArguments - transform physical registers into virtual registers
|
2010-02-07 03:20:49 +08:00
|
|
|
/// and generate load operations for arguments places on the stack.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerFormalArguments(SDValue Chain,
|
2010-02-07 03:20:49 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
|
|
|
const SmallVectorImpl<ISD::InputArg>
|
|
|
|
&Ins,
|
|
|
|
DebugLoc dl, SelectionDAG &DAG,
|
2010-04-17 23:26:15 +08:00
|
|
|
SmallVectorImpl<SDValue> &InVals)
|
|
|
|
const {
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2008-08-04 15:12:52 +08:00
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
2007-06-06 15:42:06 +08:00
|
|
|
MachineFrameInfo *MFI = MF.getFrameInfo();
|
2007-08-28 13:08:16 +08:00
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
2007-07-12 07:16:16 +08:00
|
|
|
|
|
|
|
unsigned StackReg = MF.getTarget().getRegisterInfo()->getFrameRegister(MF);
|
2010-04-17 22:41:14 +08:00
|
|
|
MipsFI->setVarArgsFrameIndex(0);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2010-02-07 03:20:49 +08:00
|
|
|
// Used with vargs to acumulate store chains.
|
|
|
|
std::vector<SDValue> OutChains;
|
|
|
|
|
|
|
|
// Keep track of the last register used for arguments
|
|
|
|
unsigned ArgRegEnd = 0;
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Assign locations to all of the incoming arguments.
|
|
|
|
SmallVector<CCValAssign, 16> ArgLocs;
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
|
|
|
|
ArgLocs, *DAG.getContext());
|
2007-07-12 07:16:16 +08:00
|
|
|
|
2009-03-19 10:12:28 +08:00
|
|
|
if (Subtarget->isABI_O32())
|
2010-11-23 11:31:01 +08:00
|
|
|
CCInfo.AnalyzeFormalArguments(Ins,
|
2010-02-07 03:20:49 +08:00
|
|
|
isVarArg ? CC_MipsO32_VarArgs : CC_MipsO32);
|
2009-03-19 10:12:28 +08:00
|
|
|
else
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
CCInfo.AnalyzeFormalArguments(Ins, CC_Mips);
|
2009-03-19 10:12:28 +08:00
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue StackPtr;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
unsigned FirstStackArgLoc = (Subtarget->isABI_EABI() ? 0 : 16);
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
|
|
|
|
CCValAssign &VA = ArgLocs[i];
|
|
|
|
|
|
|
|
// Arguments stored on registers
|
|
|
|
if (VA.isRegLoc()) {
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT RegVT = VA.getLocVT();
|
2010-02-07 03:20:49 +08:00
|
|
|
ArgRegEnd = VA.getLocReg();
|
2008-07-09 13:55:53 +08:00
|
|
|
TargetRegisterClass *RC = 0;
|
2009-03-19 10:12:28 +08:00
|
|
|
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RegVT == MVT::i32)
|
2010-11-23 11:31:01 +08:00
|
|
|
RC = Mips::CPURegsRegisterClass;
|
|
|
|
else if (RegVT == MVT::f32)
|
2009-03-21 08:05:07 +08:00
|
|
|
RC = Mips::FGR32RegisterClass;
|
2009-08-12 04:47:22 +08:00
|
|
|
else if (RegVT == MVT::f64) {
|
2010-11-23 11:31:01 +08:00
|
|
|
if (!Subtarget->isSingleFloat())
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
RC = Mips::AFGR64RegisterClass;
|
2010-11-23 11:31:01 +08:00
|
|
|
} else
|
2010-02-07 03:20:49 +08:00
|
|
|
llvm_unreachable("RegVT not supported by FormalArguments Lowering");
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// Transform the arguments stored on
|
2007-06-06 15:42:06 +08:00
|
|
|
// physical registers into virtual ones
|
2010-02-07 03:20:49 +08:00
|
|
|
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
|
2010-11-23 11:31:01 +08:00
|
|
|
|
|
|
|
// If this is an 8 or 16-bit value, it has been passed promoted
|
|
|
|
// to 32 bits. Insert an assert[sz]ext to capture this, then
|
2007-06-06 15:42:06 +08:00
|
|
|
// truncate to the right size.
|
2009-03-19 10:12:28 +08:00
|
|
|
if (VA.getLocInfo() != CCValAssign::Full) {
|
2009-03-26 13:28:14 +08:00
|
|
|
unsigned Opcode = 0;
|
2009-03-19 10:12:28 +08:00
|
|
|
if (VA.getLocInfo() == CCValAssign::SExt)
|
|
|
|
Opcode = ISD::AssertSext;
|
|
|
|
else if (VA.getLocInfo() == CCValAssign::ZExt)
|
|
|
|
Opcode = ISD::AssertZext;
|
2009-03-26 13:28:14 +08:00
|
|
|
if (Opcode)
|
2010-11-23 11:31:01 +08:00
|
|
|
ArgValue = DAG.getNode(Opcode, dl, RegVT, ArgValue,
|
2009-03-26 13:28:14 +08:00
|
|
|
DAG.getValueType(VA.getValVT()));
|
2009-02-05 04:06:27 +08:00
|
|
|
ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
|
2009-03-19 10:12:28 +08:00
|
|
|
}
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// Handle O32 ABI cases: i32->f32 and (i32,i32)->f64
|
2009-03-19 10:12:28 +08:00
|
|
|
if (Subtarget->isABI_O32()) {
|
2010-11-23 11:31:01 +08:00
|
|
|
if (RegVT == MVT::i32 && VA.getValVT() == MVT::f32)
|
|
|
|
ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f32, ArgValue);
|
2009-08-12 04:47:22 +08:00
|
|
|
if (RegVT == MVT::i32 && VA.getValVT() == MVT::f64) {
|
2010-11-23 11:31:01 +08:00
|
|
|
unsigned Reg2 = AddLiveIn(DAG.getMachineFunction(),
|
2009-03-19 10:12:28 +08:00
|
|
|
VA.getLocReg()+1, RC);
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue ArgValue2 = DAG.getCopyFromReg(Chain, dl, Reg2, RegVT);
|
2011-01-19 03:38:25 +08:00
|
|
|
SDValue Pair = DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, ArgValue2, ArgValue);
|
|
|
|
ArgValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, Pair);
|
2009-03-19 10:12:28 +08:00
|
|
|
}
|
|
|
|
}
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
InVals.push_back(ArgValue);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
} else { // VA.isRegLoc()
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// sanity check
|
|
|
|
assert(VA.isMemLoc());
|
2010-02-07 03:20:49 +08:00
|
|
|
|
|
|
|
// The last argument is not a register anymore
|
|
|
|
ArgRegEnd = 0;
|
2010-11-23 11:31:01 +08:00
|
|
|
|
|
|
|
// The stack pointer offset is relative to the caller stack frame.
|
|
|
|
// Since the real stack size is unknown here, a negative SPOffset
|
2007-08-28 13:08:16 +08:00
|
|
|
// is used so there's a way to adjust these offsets when the stack
|
2010-11-23 11:31:01 +08:00
|
|
|
// size get known (on EliminateFrameIndex). A dummy SPOffset is
|
2007-08-28 13:08:16 +08:00
|
|
|
// used instead of a direct negative address (which is recorded to
|
2010-11-23 11:31:01 +08:00
|
|
|
// be used on emitPrologue) to avoid mis-calc of the first stack
|
2007-08-28 13:08:16 +08:00
|
|
|
// offset on PEI::calculateFrameObjectOffsets.
|
|
|
|
// Arguments are always 32-bit.
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
unsigned ArgSize = VA.getLocVT().getSizeInBits()/8;
|
2010-07-03 08:40:23 +08:00
|
|
|
int FI = MFI->CreateFixedObject(ArgSize, 0, true);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
MipsFI->recordLoadArgsFI(FI, -(ArgSize+
|
|
|
|
(FirstStackArgLoc + VA.getLocMemOffset())));
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Create load nodes to retrieve arguments from the stack
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
|
2010-09-21 14:44:06 +08:00
|
|
|
InVals.push_back(DAG.getLoad(VA.getValVT(), dl, Chain, FIN,
|
|
|
|
MachinePointerInfo::getFixedStack(FI),
|
2010-02-16 00:56:10 +08:00
|
|
|
false, false, 0));
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. Save the argument into
|
|
|
|
// a virtual register so that we can access it from the return points.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
if (!Reg) {
|
2009-08-12 04:47:22 +08:00
|
|
|
Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32));
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
MipsFI->setSRetReturnReg(Reg);
|
|
|
|
}
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue Copy = DAG.getCopyToReg(DAG.getEntryNode(), dl, Reg, InVals[0]);
|
2009-08-12 04:47:22 +08:00
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Copy, Chain);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
}
|
|
|
|
|
2010-02-07 03:20:49 +08:00
|
|
|
// To meet ABI, when VARARGS are passed on registers, the registers
|
|
|
|
// must have their values written to the caller stack frame. If the last
|
2010-11-23 11:31:01 +08:00
|
|
|
// argument was placed in the stack, there's no need to save any register.
|
2010-02-07 03:20:49 +08:00
|
|
|
if ((isVarArg) && (Subtarget->isABI_O32() && ArgRegEnd)) {
|
|
|
|
if (StackPtr.getNode() == 0)
|
|
|
|
StackPtr = DAG.getRegister(StackReg, getPointerTy());
|
2010-11-23 11:31:01 +08:00
|
|
|
|
2010-02-07 03:20:49 +08:00
|
|
|
// The last register argument that must be saved is Mips::A3
|
|
|
|
TargetRegisterClass *RC = Mips::CPURegsRegisterClass;
|
|
|
|
unsigned StackLoc = ArgLocs.size()-1;
|
|
|
|
|
|
|
|
for (++ArgRegEnd; ArgRegEnd <= Mips::A3; ++ArgRegEnd, ++StackLoc) {
|
|
|
|
unsigned Reg = AddLiveIn(DAG.getMachineFunction(), ArgRegEnd, RC);
|
|
|
|
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, MVT::i32);
|
|
|
|
|
2010-07-03 08:40:23 +08:00
|
|
|
int FI = MFI->CreateFixedObject(4, 0, true);
|
2010-02-07 03:20:49 +08:00
|
|
|
MipsFI->recordStoreVarArgsFI(FI, -(4+(StackLoc*4)));
|
|
|
|
SDValue PtrOff = DAG.getFrameIndex(FI, getPointerTy());
|
2010-09-22 01:50:43 +08:00
|
|
|
OutChains.push_back(DAG.getStore(Chain, dl, ArgValue, PtrOff,
|
|
|
|
MachinePointerInfo(),
|
2010-02-16 00:56:10 +08:00
|
|
|
false, false, 0));
|
2010-02-07 05:00:02 +08:00
|
|
|
|
|
|
|
// Record the frame index of the first variable argument
|
|
|
|
// which is a value necessary to VASTART.
|
2010-04-17 22:41:14 +08:00
|
|
|
if (!MipsFI->getVarArgsFrameIndex())
|
|
|
|
MipsFI->setVarArgsFrameIndex(FI);
|
2010-02-07 03:20:49 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// All stores are grouped in one node to allow the matching between
|
2010-02-07 03:20:49 +08:00
|
|
|
// the size of Ins and InVals. This only happens when on varg functions
|
|
|
|
if (!OutChains.empty()) {
|
|
|
|
OutChains.push_back(Chain);
|
|
|
|
Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
|
|
|
|
&OutChains[0], OutChains.size());
|
|
|
|
}
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
return Chain;
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Return Value Calling Convention Implementation
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
SDValue
|
|
|
|
MipsTargetLowering::LowerReturn(SDValue Chain,
|
2009-09-02 16:44:58 +08:00
|
|
|
CallingConv::ID CallConv, bool isVarArg,
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
2010-07-07 23:54:55 +08:00
|
|
|
const SmallVectorImpl<SDValue> &OutVals,
|
2010-04-17 23:26:15 +08:00
|
|
|
DebugLoc dl, SelectionDAG &DAG) const {
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// CCValAssign - represent the assignment of
|
|
|
|
// the return value to a location
|
|
|
|
SmallVector<CCValAssign, 16> RVLocs;
|
|
|
|
|
|
|
|
// CCState - Info about the registers and stack slot.
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
|
|
|
|
RVLocs, *DAG.getContext());
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Major calling convention code refactoring.
Instead of awkwardly encoding calling-convention information with ISD::CALL,
ISD::FORMAL_ARGUMENTS, ISD::RET, and ISD::ARG_FLAGS nodes, TargetLowering
provides three virtual functions for targets to override:
LowerFormalArguments, LowerCall, and LowerRet, which replace the custom
lowering done on the special nodes. They provide the same information, but
in a more immediately usable format.
This also reworks much of the target-independent tail call logic. The
decision of whether or not to perform a tail call is now cleanly split
between target-independent portions, and the target dependent portion
in IsEligibleForTailCallOptimization.
This also synchronizes all in-tree targets, to help enable future
refactoring and feature work.
llvm-svn: 78142
2009-08-05 09:29:28 +08:00
|
|
|
// Analize return values.
|
|
|
|
CCInfo.AnalyzeReturn(Outs, RetCC_Mips);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
// If this is the first return lowered for this function, add
|
2007-06-06 15:42:06 +08:00
|
|
|
// the regs to the liveout set for the function.
|
2007-12-31 12:13:23 +08:00
|
|
|
if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
|
2007-06-06 15:42:06 +08:00
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i)
|
2007-07-12 07:16:16 +08:00
|
|
|
if (RVLocs[i].isRegLoc())
|
2007-12-31 12:13:23 +08:00
|
|
|
DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
|
|
|
|
2008-07-28 05:46:04 +08:00
|
|
|
SDValue Flag;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// Copy the result values into the output registers.
|
|
|
|
for (unsigned i = 0; i != RVLocs.size(); ++i) {
|
|
|
|
CCValAssign &VA = RVLocs[i];
|
|
|
|
assert(VA.isRegLoc() && "Can only return in registers!");
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(),
|
2010-07-07 23:54:55 +08:00
|
|
|
OutVals[i], Flag);
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
// guarantee that all emitted copies are
|
|
|
|
// stuck together, avoiding something bad
|
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// The mips ABIs for returning structs by value requires that we copy
|
|
|
|
// the sret argument into $v0 for the return. We saved the argument into
|
|
|
|
// a virtual register in the entry block, so now we copy the value out
|
|
|
|
// and into $v0.
|
|
|
|
if (DAG.getMachineFunction().getFunction()->hasStructRetAttr()) {
|
|
|
|
MachineFunction &MF = DAG.getMachineFunction();
|
|
|
|
MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
|
|
|
|
unsigned Reg = MipsFI->getSRetReturnReg();
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
if (!Reg)
|
2009-07-15 00:55:14 +08:00
|
|
|
llvm_unreachable("sret virtual register not created in the entry block");
|
2009-02-05 07:02:30 +08:00
|
|
|
SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2009-02-05 07:02:30 +08:00
|
|
|
Chain = DAG.getCopyToReg(Chain, dl, Mips::V0, Val, Flag);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
Flag = Chain.getValue(1);
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
// Return on Mips is always a "jr $ra"
|
2008-08-29 05:40:38 +08:00
|
|
|
if (Flag.getNode())
|
2010-11-23 11:31:01 +08:00
|
|
|
return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
|
2009-08-12 04:47:22 +08:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32), Flag);
|
2007-06-06 15:42:06 +08:00
|
|
|
else // Return Void
|
2010-11-23 11:31:01 +08:00
|
|
|
return DAG.getNode(MipsISD::Ret, dl, MVT::Other,
|
2009-08-12 04:47:22 +08:00
|
|
|
Chain, DAG.getRegister(Mips::RA, MVT::i32));
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|
2007-08-22 00:09:25 +08:00
|
|
|
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Mips Inline Assembly Support
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
|
|
/// constraint it is for this target.
|
|
|
|
MipsTargetLowering::ConstraintType MipsTargetLowering::
|
2010-11-23 11:31:01 +08:00
|
|
|
getConstraintType(const std::string &Constraint) const
|
2007-08-22 00:09:25 +08:00
|
|
|
{
|
2010-11-23 11:31:01 +08:00
|
|
|
// Mips specific constrainy
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// GCC config/mips/constraints.md
|
|
|
|
//
|
2010-11-23 11:31:01 +08:00
|
|
|
// 'd' : An address register. Equivalent to r
|
|
|
|
// unless generating MIPS16 code.
|
|
|
|
// 'y' : Equivalent to r; retained for
|
|
|
|
// backwards compatibility.
|
|
|
|
// 'f' : Floating Point registers.
|
2007-08-22 00:09:25 +08:00
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
default : break;
|
2010-11-23 11:31:01 +08:00
|
|
|
case 'd':
|
|
|
|
case 'y':
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
case 'f':
|
2007-08-22 00:09:25 +08:00
|
|
|
return C_RegisterClass;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getConstraintType(Constraint);
|
|
|
|
}
|
|
|
|
|
2010-10-30 01:29:13 +08:00
|
|
|
/// Examine constraint type and operand type and determine a weight value.
|
|
|
|
/// This object must already have been set up with the operand type
|
|
|
|
/// and the current alternative constraint selected.
|
|
|
|
TargetLowering::ConstraintWeight
|
|
|
|
MipsTargetLowering::getSingleConstraintMatchWeight(
|
|
|
|
AsmOperandInfo &info, const char *constraint) const {
|
|
|
|
ConstraintWeight weight = CW_Invalid;
|
|
|
|
Value *CallOperandVal = info.CallOperandVal;
|
|
|
|
// If we don't have a value, we can't do a match,
|
|
|
|
// but allow it at the lowest weight.
|
|
|
|
if (CallOperandVal == NULL)
|
|
|
|
return CW_Default;
|
|
|
|
const Type *type = CallOperandVal->getType();
|
|
|
|
// Look at the constraint type.
|
|
|
|
switch (*constraint) {
|
|
|
|
default:
|
|
|
|
weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
|
|
|
|
break;
|
2010-11-23 11:31:01 +08:00
|
|
|
case 'd':
|
|
|
|
case 'y':
|
2010-10-30 01:29:13 +08:00
|
|
|
if (type->isIntegerTy())
|
|
|
|
weight = CW_Register;
|
|
|
|
break;
|
|
|
|
case 'f':
|
|
|
|
if (type->isFloatTy())
|
|
|
|
weight = CW_Register;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return weight;
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
/// getRegClassForInlineAsmConstraint - Given a constraint letter (e.g. "r"),
|
|
|
|
/// return a list of registers that can be used to satisfy the constraint.
|
|
|
|
/// This should only be used for C_RegisterClass constraints.
|
2007-08-22 00:09:25 +08:00
|
|
|
std::pair<unsigned, const TargetRegisterClass*> MipsTargetLowering::
|
2009-08-11 06:56:29 +08:00
|
|
|
getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const
|
2007-08-22 00:09:25 +08:00
|
|
|
{
|
|
|
|
if (Constraint.size() == 1) {
|
|
|
|
switch (Constraint[0]) {
|
|
|
|
case 'r':
|
|
|
|
return std::make_pair(0U, Mips::CPURegsRegisterClass);
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
case 'f':
|
2009-08-12 04:47:22 +08:00
|
|
|
if (VT == MVT::f32)
|
2009-03-21 08:05:07 +08:00
|
|
|
return std::make_pair(0U, Mips::FGR32RegisterClass);
|
2010-11-23 11:31:01 +08:00
|
|
|
if (VT == MVT::f64)
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
|
|
|
|
return std::make_pair(0U, Mips::AFGR64RegisterClass);
|
2007-08-22 00:09:25 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
|
|
|
|
}
|
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
/// Given a register class constraint, like 'r', if this corresponds directly
|
|
|
|
/// to an LLVM register class, return a register of 0 and the register class
|
|
|
|
/// pointer.
|
2007-08-22 00:09:25 +08:00
|
|
|
std::vector<unsigned> MipsTargetLowering::
|
|
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
2009-08-11 06:56:29 +08:00
|
|
|
EVT VT) const
|
2007-08-22 00:09:25 +08:00
|
|
|
{
|
|
|
|
if (Constraint.size() != 1)
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
switch (Constraint[0]) {
|
2007-08-22 00:09:25 +08:00
|
|
|
default : break;
|
|
|
|
case 'r':
|
|
|
|
// GCC Mips Constraint Letters
|
2010-11-23 11:31:01 +08:00
|
|
|
case 'd':
|
|
|
|
case 'y':
|
|
|
|
return make_vector<unsigned>(Mips::T0, Mips::T1, Mips::T2, Mips::T3,
|
|
|
|
Mips::T4, Mips::T5, Mips::T6, Mips::T7, Mips::S0, Mips::S1,
|
|
|
|
Mips::S2, Mips::S3, Mips::S4, Mips::S5, Mips::S6, Mips::S7,
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
Mips::T8, 0);
|
|
|
|
|
|
|
|
case 'f':
|
2009-08-12 04:47:22 +08:00
|
|
|
if (VT == MVT::f32) {
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if (Subtarget->isSingleFloat())
|
|
|
|
return make_vector<unsigned>(Mips::F2, Mips::F3, Mips::F4, Mips::F5,
|
|
|
|
Mips::F6, Mips::F7, Mips::F8, Mips::F9, Mips::F10, Mips::F11,
|
|
|
|
Mips::F20, Mips::F21, Mips::F22, Mips::F23, Mips::F24,
|
|
|
|
Mips::F25, Mips::F26, Mips::F27, Mips::F28, Mips::F29,
|
|
|
|
Mips::F30, Mips::F31, 0);
|
|
|
|
else
|
2010-11-23 11:31:01 +08:00
|
|
|
return make_vector<unsigned>(Mips::F2, Mips::F4, Mips::F6, Mips::F8,
|
|
|
|
Mips::F10, Mips::F20, Mips::F22, Mips::F24, Mips::F26,
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
Mips::F28, Mips::F30, 0);
|
2008-07-08 17:33:14 +08:00
|
|
|
}
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
|
2010-11-23 11:31:01 +08:00
|
|
|
if (VT == MVT::f64)
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
if ((!Subtarget->isSingleFloat()) && (!Subtarget->isFP64bit()))
|
2010-11-23 11:31:01 +08:00
|
|
|
return make_vector<unsigned>(Mips::D1, Mips::D2, Mips::D3, Mips::D4,
|
|
|
|
Mips::D5, Mips::D10, Mips::D11, Mips::D12, Mips::D13,
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
Mips::D14, Mips::D15, 0);
|
2007-08-22 00:09:25 +08:00
|
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
|
|
}
|
Teach DAGCombine to fold constant offsets into GlobalAddress nodes,
and add a TargetLowering hook for it to use to determine when this
is legal (i.e. not in PIC mode, etc.)
This allows instruction selection to emit folded constant offsets
in more cases, such as the included testcase, eliminating the need
for explicit arithmetic instructions.
This eliminates the need for the C++ code in X86ISelDAGToDAG.cpp
that attempted to achieve the same effect, but wasn't as effective.
Also, fix handling of offsets in GlobalAddressSDNodes in several
places, including changing GlobalAddressSDNode's offset from
int to int64_t.
The Mips, Alpha, Sparc, and CellSPU targets appear to be
unaware of GlobalAddress offsets currently, so set the hook to
false on those targets.
llvm-svn: 57748
2008-10-18 10:06:02 +08:00
|
|
|
|
|
|
|
bool
|
|
|
|
MipsTargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
|
|
|
|
// The Mips target isn't yet aware of offsets.
|
|
|
|
return false;
|
|
|
|
}
|
2009-10-28 03:56:55 +08:00
|
|
|
|
2009-10-28 09:43:28 +08:00
|
|
|
bool MipsTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
|
|
|
|
if (VT != MVT::f32 && VT != MVT::f64)
|
|
|
|
return false;
|
2011-01-19 03:41:41 +08:00
|
|
|
if (Imm.isNegZero())
|
|
|
|
return false;
|
2009-10-28 03:56:55 +08:00
|
|
|
return Imm.isZero();
|
|
|
|
}
|