2013-04-26 04:29:37 +08:00
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//===-- X86FixupLEAs.cpp - use or replace LEA instructions -----------===//
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2013-04-26 04:29:37 +08:00
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//
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//===----------------------------------------------------------------------===//
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//
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2014-07-17 04:18:49 +08:00
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// This file defines the pass that finds instructions that can be
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// re-written as LEA instructions in order to reduce pipeline delays.
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2019-05-25 14:17:47 +08:00
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// It replaces LEAs with ADD/INC/DEC when that is better for size/speed.
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2013-04-26 04:29:37 +08:00
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//
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//===----------------------------------------------------------------------===//
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#include "X86.h"
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#include "X86InstrInfo.h"
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#include "X86Subtarget.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/Passes.h"
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2018-04-13 23:09:39 +08:00
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#include "llvm/CodeGen/TargetSchedule.h"
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2013-04-26 04:29:37 +08:00
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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2017-05-18 16:11:50 +08:00
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#define FIXUPLEA_DESC "X86 LEA Fixup"
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#define FIXUPLEA_NAME "x86-fixup-LEAs"
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#define DEBUG_TYPE FIXUPLEA_NAME
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2014-04-22 10:41:26 +08:00
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2013-04-26 04:29:37 +08:00
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STATISTIC(NumLEAs, "Number of LEA instructions created");
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namespace {
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2014-06-04 05:01:35 +08:00
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class FixupLEAPass : public MachineFunctionPass {
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enum RegUsageState { RU_NotUsed, RU_Write, RU_Read };
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2017-05-18 16:11:50 +08:00
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2018-05-01 23:54:18 +08:00
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/// Given a machine register, look for the instruction
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2014-06-04 05:01:35 +08:00
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/// which writes it in the current basic block. If found,
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/// try to replace it with an equivalent LEA instruction.
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2015-06-19 09:53:21 +08:00
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/// If replacement succeeds, then also process the newly created
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2014-06-04 05:01:35 +08:00
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/// instruction.
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void seekLEAFixup(MachineOperand &p, MachineBasicBlock::iterator &I,
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2019-05-01 01:56:28 +08:00
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MachineBasicBlock &MBB);
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2013-04-26 05:31:33 +08:00
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2018-05-01 23:54:18 +08:00
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/// Given a memory access or LEA instruction
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2014-06-04 05:01:35 +08:00
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/// whose address mode uses a base and/or index register, look for
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/// an opportunity to replace the instruction which sets the base or index
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/// register with an equivalent LEA instruction.
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void processInstruction(MachineBasicBlock::iterator &I,
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2019-05-01 01:56:28 +08:00
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MachineBasicBlock &MBB);
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2013-04-26 05:31:33 +08:00
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2018-05-01 23:54:18 +08:00
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/// Given a LEA instruction which is unprofitable
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2018-11-01 22:57:07 +08:00
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/// on SlowLEA targets try to replace it with an equivalent ADD instruction.
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void processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
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2019-05-01 01:56:28 +08:00
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MachineBasicBlock &MBB);
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2017-05-18 16:11:50 +08:00
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2018-05-01 23:54:18 +08:00
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/// Given a LEA instruction which is unprofitable
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2017-05-18 16:11:50 +08:00
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/// on SNB+ try to replace it with other instructions.
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/// According to Intel's Optimization Reference Manual:
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/// " For LEA instructions with three source operands and some specific
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/// situations, instruction latency has increased to 3 cycles, and must
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/// dispatch via port 1:
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/// - LEA that has all three source operands: base, index, and offset
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/// - LEA that uses base and index registers where the base is EBP, RBP,
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/// or R13
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/// - LEA that uses RIP relative addressing mode
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/// - LEA that uses 16-bit addressing mode "
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/// This function currently handles the first 2 cases only.
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MachineInstr *processInstrForSlow3OpLEA(MachineInstr &MI,
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2019-05-01 01:56:28 +08:00
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MachineBasicBlock &MBB);
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2017-05-18 16:11:50 +08:00
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2019-05-25 14:17:47 +08:00
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/// Look for LEAs that are really two address LEAs that we might be able to
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/// turn into regular ADD instructions.
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bool optTwoAddrLEA(MachineBasicBlock::iterator &I,
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MachineBasicBlock &MBB, bool OptIncDec,
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bool UseLEAForSP) const;
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2015-11-11 19:44:31 +08:00
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2018-05-01 23:54:18 +08:00
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/// Determine if an instruction references a machine register
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2014-06-04 05:01:35 +08:00
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/// and, if so, whether it reads or writes the register.
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RegUsageState usesRegister(MachineOperand &p, MachineBasicBlock::iterator I);
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2013-04-26 05:31:33 +08:00
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2018-05-01 23:54:18 +08:00
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/// Step backwards through a basic block, looking
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2014-06-04 05:01:35 +08:00
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/// for an instruction which writes a register within
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/// a maximum of INSTR_DISTANCE_THRESHOLD instruction latency cycles.
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MachineBasicBlock::iterator searchBackwards(MachineOperand &p,
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MachineBasicBlock::iterator &I,
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2019-05-01 01:56:28 +08:00
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MachineBasicBlock &MBB);
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2013-04-26 05:31:33 +08:00
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2018-05-01 23:54:18 +08:00
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/// if an instruction can be converted to an
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2014-06-04 05:01:35 +08:00
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/// equivalent LEA, insert the new instruction into the basic block
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/// and return a pointer to it. Otherwise, return zero.
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2019-05-01 01:56:28 +08:00
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MachineInstr *postRAConvertToLEA(MachineBasicBlock &MBB,
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2014-06-04 05:01:35 +08:00
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MachineBasicBlock::iterator &MBBI) const;
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2013-04-26 04:29:37 +08:00
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2014-06-04 05:01:35 +08:00
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public:
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2017-05-18 16:11:50 +08:00
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static char ID;
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StringRef getPassName() const override { return FIXUPLEA_DESC; }
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2019-06-13 10:09:32 +08:00
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FixupLEAPass() : MachineFunctionPass(ID) { }
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2013-04-26 04:29:37 +08:00
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2018-05-01 23:54:18 +08:00
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/// Loop over all of the basic blocks,
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2014-06-04 05:01:35 +08:00
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/// replacing instructions by equivalent LEA instructions
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/// if needed and when possible.
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bool runOnMachineFunction(MachineFunction &MF) override;
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2013-04-26 04:29:37 +08:00
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2016-04-05 01:09:25 +08:00
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// This pass runs after regalloc and doesn't support VReg operands.
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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2016-08-25 09:27:13 +08:00
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MachineFunctionProperties::Property::NoVRegs);
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2016-04-05 01:09:25 +08:00
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}
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2014-06-04 05:01:35 +08:00
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private:
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2018-04-13 23:09:39 +08:00
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TargetSchedModel TSM;
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2019-05-25 14:17:47 +08:00
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const X86InstrInfo *TII;
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const X86RegisterInfo *TRI;
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2014-06-04 05:01:35 +08:00
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};
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2017-05-17 03:55:03 +08:00
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}
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2017-05-17 00:01:36 +08:00
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2017-05-18 16:11:50 +08:00
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char FixupLEAPass::ID = 0;
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INITIALIZE_PASS(FixupLEAPass, FIXUPLEA_NAME, FIXUPLEA_DESC, false, false)
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2013-04-26 04:29:37 +08:00
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MachineInstr *
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2019-05-01 01:56:28 +08:00
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FixupLEAPass::postRAConvertToLEA(MachineBasicBlock &MBB,
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2013-04-26 05:31:33 +08:00
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MachineBasicBlock::iterator &MBBI) const {
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2016-06-30 08:01:54 +08:00
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MachineInstr &MI = *MBBI;
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switch (MI.getOpcode()) {
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2014-05-20 16:55:50 +08:00
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case X86::MOV32rr:
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2013-04-26 04:29:37 +08:00
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case X86::MOV64rr: {
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2016-06-30 08:01:54 +08:00
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const MachineOperand &Src = MI.getOperand(1);
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const MachineOperand &Dest = MI.getOperand(0);
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MachineInstr *NewMI =
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2019-05-01 01:56:28 +08:00
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BuildMI(MBB, MBBI, MI.getDebugLoc(),
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2016-06-30 08:01:54 +08:00
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TII->get(MI.getOpcode() == X86::MOV32rr ? X86::LEA32r
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: X86::LEA64r))
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2017-01-13 17:58:52 +08:00
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.add(Dest)
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.add(Src)
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2016-06-30 08:01:54 +08:00
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.addImm(1)
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.addReg(0)
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.addImm(0)
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.addReg(0);
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2013-04-26 04:29:37 +08:00
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return NewMI;
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}
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2019-04-03 04:52:10 +08:00
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}
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if (!MI.isConvertibleTo3Addr())
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return nullptr;
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switch (MI.getOpcode()) {
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2013-04-26 04:29:37 +08:00
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case X86::ADD64ri32:
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case X86::ADD64ri8:
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case X86::ADD64ri32_DB:
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case X86::ADD64ri8_DB:
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case X86::ADD32ri:
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case X86::ADD32ri8:
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case X86::ADD32ri_DB:
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case X86::ADD32ri8_DB:
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case X86::ADD16ri:
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case X86::ADD16ri8:
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case X86::ADD16ri_DB:
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case X86::ADD16ri8_DB:
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2016-06-30 08:01:54 +08:00
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if (!MI.getOperand(2).isImm()) {
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2013-04-26 04:29:37 +08:00
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// convertToThreeAddress will call getImm()
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// which requires isImm() to be true
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2014-04-25 13:30:21 +08:00
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return nullptr;
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2013-04-26 04:29:37 +08:00
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}
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2013-10-01 07:51:22 +08:00
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break;
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2013-10-01 07:18:42 +08:00
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case X86::ADD16rr:
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case X86::ADD16rr_DB:
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2016-06-30 08:01:54 +08:00
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if (MI.getOperand(1).getReg() != MI.getOperand(2).getReg()) {
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2013-10-01 07:18:42 +08:00
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// if src1 != src2, then convertToThreeAddress will
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// need to create a Virtual register, which we cannot do
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// after register allocation.
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2014-04-25 13:30:21 +08:00
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return nullptr;
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2013-10-01 07:18:42 +08:00
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}
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2013-04-26 04:29:37 +08:00
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}
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2019-05-01 01:56:28 +08:00
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MachineFunction::iterator MFI = MBB.getIterator();
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2016-06-30 08:01:54 +08:00
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return TII->convertToThreeAddress(MFI, MI, nullptr);
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2013-04-26 04:29:37 +08:00
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}
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2014-06-04 05:01:35 +08:00
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FunctionPass *llvm::createX86FixupLEAs() { return new FixupLEAPass(); }
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2013-04-26 04:29:37 +08:00
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2019-05-01 14:53:03 +08:00
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static bool isLEA(unsigned Opcode) {
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2019-05-03 06:46:23 +08:00
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return Opcode == X86::LEA32r || Opcode == X86::LEA64r ||
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Opcode == X86::LEA64_32r;
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2019-05-01 14:53:03 +08:00
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}
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2019-05-01 01:56:28 +08:00
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bool FixupLEAPass::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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2016-04-27 05:44:24 +08:00
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return false;
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2019-05-01 01:56:28 +08:00
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const X86Subtarget &ST = MF.getSubtarget<X86Subtarget>();
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2018-11-07 20:26:00 +08:00
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bool IsSlowLEA = ST.slowLEA();
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bool IsSlow3OpsLEA = ST.slow3OpsLEA();
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2019-05-01 01:56:28 +08:00
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bool LEAUsesAG = ST.LEAusesAG();
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2018-11-07 20:26:00 +08:00
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2019-05-01 01:56:28 +08:00
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bool OptIncDec = !ST.slowIncDec() || MF.getFunction().hasOptSize();
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2019-05-25 14:17:47 +08:00
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bool UseLEAForSP = ST.useLeaForSP();
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2014-05-22 09:46:02 +08:00
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2019-05-01 01:56:28 +08:00
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TSM.init(&ST);
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2015-02-06 03:27:01 +08:00
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TII = ST.getInstrInfo();
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2019-05-25 14:17:47 +08:00
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TRI = ST.getRegisterInfo();
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2013-04-26 04:29:37 +08:00
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << "Start X86FixupLEAs\n";);
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2019-05-01 01:56:28 +08:00
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for (MachineBasicBlock &MBB : MF) {
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// First pass. Try to remove or optimize existing LEAs.
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I) {
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2019-05-01 14:53:03 +08:00
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if (!isLEA(I->getOpcode()))
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continue;
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2019-05-25 14:17:47 +08:00
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if (optTwoAddrLEA(I, MBB, OptIncDec, UseLEAForSP))
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2019-05-01 01:56:28 +08:00
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continue;
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if (IsSlowLEA) {
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processInstructionForSlowLEA(I, MBB);
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} else if (IsSlow3OpsLEA) {
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if (auto *NewMI = processInstrForSlow3OpLEA(*I, MBB)) {
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MBB.erase(I);
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I = NewMI;
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}
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}
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}
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// Second pass for creating LEAs. This may reverse some of the
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// transformations above.
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if (LEAUsesAG) {
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for (MachineBasicBlock::iterator I = MBB.begin(); I != MBB.end(); ++I)
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processInstruction(I, MBB);
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}
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}
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2018-05-14 20:53:11 +08:00
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LLVM_DEBUG(dbgs() << "End X86FixupLEAs\n";);
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2013-04-26 04:29:37 +08:00
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return true;
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}
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2014-06-04 05:01:35 +08:00
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FixupLEAPass::RegUsageState
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FixupLEAPass::usesRegister(MachineOperand &p, MachineBasicBlock::iterator I) {
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2013-04-26 04:29:37 +08:00
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RegUsageState RegUsage = RU_NotUsed;
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2016-07-12 11:18:50 +08:00
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MachineInstr &MI = *I;
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2013-04-26 04:29:37 +08:00
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2019-04-02 08:50:58 +08:00
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for (unsigned i = 0; i < MI.getNumOperands(); ++i) {
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2016-07-12 11:18:50 +08:00
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MachineOperand &opnd = MI.getOperand(i);
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2014-06-04 05:01:35 +08:00
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if (opnd.isReg() && opnd.getReg() == p.getReg()) {
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2013-04-26 04:29:37 +08:00
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if (opnd.isDef())
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return RU_Write;
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RegUsage = RU_Read;
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}
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}
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return RegUsage;
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}
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/// getPreviousInstr - Given a reference to an instruction in a basic
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/// block, return a reference to the previous instruction in the block,
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/// wrapping around to the last instruction of the block if the block
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/// branches to itself.
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2014-06-04 05:01:35 +08:00
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static inline bool getPreviousInstr(MachineBasicBlock::iterator &I,
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2019-05-01 01:56:28 +08:00
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MachineBasicBlock &MBB) {
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if (I == MBB.begin()) {
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if (MBB.isPredecessor(&MBB)) {
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I = --MBB.end();
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2013-04-26 04:29:37 +08:00
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return true;
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2014-06-04 05:01:35 +08:00
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} else
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2013-04-26 04:29:37 +08:00
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return false;
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}
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--I;
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return true;
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}
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2014-06-04 05:01:35 +08:00
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MachineBasicBlock::iterator
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|
|
FixupLEAPass::searchBackwards(MachineOperand &p, MachineBasicBlock::iterator &I,
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineBasicBlock &MBB) {
|
2013-04-26 04:29:37 +08:00
|
|
|
int InstrDistance = 1;
|
|
|
|
MachineBasicBlock::iterator CurInst;
|
|
|
|
static const int INSTR_DISTANCE_THRESHOLD = 5;
|
|
|
|
|
|
|
|
CurInst = I;
|
|
|
|
bool Found;
|
2019-05-01 01:56:28 +08:00
|
|
|
Found = getPreviousInstr(CurInst, MBB);
|
2014-06-04 05:01:35 +08:00
|
|
|
while (Found && I != CurInst) {
|
2013-04-26 04:29:37 +08:00
|
|
|
if (CurInst->isCall() || CurInst->isInlineAsm())
|
|
|
|
break;
|
|
|
|
if (InstrDistance > INSTR_DISTANCE_THRESHOLD)
|
|
|
|
break; // too far back to make a difference
|
2014-06-04 05:01:35 +08:00
|
|
|
if (usesRegister(p, CurInst) == RU_Write) {
|
2013-04-26 04:29:37 +08:00
|
|
|
return CurInst;
|
|
|
|
}
|
2018-04-13 23:09:39 +08:00
|
|
|
InstrDistance += TSM.computeInstrLatency(&*CurInst);
|
2019-05-01 01:56:28 +08:00
|
|
|
Found = getPreviousInstr(CurInst, MBB);
|
2013-04-26 04:29:37 +08:00
|
|
|
}
|
2016-07-12 11:18:50 +08:00
|
|
|
return MachineBasicBlock::iterator();
|
2013-04-26 04:29:37 +08:00
|
|
|
}
|
|
|
|
|
2019-04-02 08:50:58 +08:00
|
|
|
static inline bool isInefficientLEAReg(unsigned Reg) {
|
2018-08-03 11:45:19 +08:00
|
|
|
return Reg == X86::EBP || Reg == X86::RBP ||
|
|
|
|
Reg == X86::R13D || Reg == X86::R13;
|
2017-05-18 16:11:50 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool isRegOperand(const MachineOperand &Op) {
|
|
|
|
return Op.isReg() && Op.getReg() != X86::NoRegister;
|
|
|
|
}
|
2018-11-07 20:26:00 +08:00
|
|
|
|
|
|
|
/// Returns true if this LEA uses base an index registers, and the base register
|
|
|
|
/// is known to be inefficient for the subtarget.
|
2018-07-20 00:42:15 +08:00
|
|
|
// TODO: use a variant scheduling class to model the latency profile
|
|
|
|
// of LEA instructions, and implement this logic as a scheduling predicate.
|
2017-05-18 16:11:50 +08:00
|
|
|
static inline bool hasInefficientLEABaseReg(const MachineOperand &Base,
|
|
|
|
const MachineOperand &Index) {
|
|
|
|
return Base.isReg() && isInefficientLEAReg(Base.getReg()) &&
|
|
|
|
isRegOperand(Index);
|
|
|
|
}
|
|
|
|
|
|
|
|
static inline bool hasLEAOffset(const MachineOperand &Offset) {
|
|
|
|
return (Offset.isImm() && Offset.getImm() != 0) || Offset.isGlobal();
|
|
|
|
}
|
|
|
|
|
2019-04-02 08:50:58 +08:00
|
|
|
static inline unsigned getADDrrFromLEA(unsigned LEAOpcode) {
|
2017-05-18 16:11:50 +08:00
|
|
|
switch (LEAOpcode) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected LEA instruction");
|
|
|
|
case X86::LEA32r:
|
|
|
|
case X86::LEA64_32r:
|
2019-05-25 14:17:47 +08:00
|
|
|
return X86::ADD32rr;
|
2017-05-18 16:11:50 +08:00
|
|
|
case X86::LEA64r:
|
|
|
|
return X86::ADD64rr;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2019-04-02 08:50:58 +08:00
|
|
|
static inline unsigned getADDriFromLEA(unsigned LEAOpcode,
|
|
|
|
const MachineOperand &Offset) {
|
2017-05-18 16:11:50 +08:00
|
|
|
bool IsInt8 = Offset.isImm() && isInt<8>(Offset.getImm());
|
|
|
|
switch (LEAOpcode) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected LEA instruction");
|
|
|
|
case X86::LEA32r:
|
|
|
|
case X86::LEA64_32r:
|
|
|
|
return IsInt8 ? X86::ADD32ri8 : X86::ADD32ri;
|
|
|
|
case X86::LEA64r:
|
|
|
|
return IsInt8 ? X86::ADD64ri8 : X86::ADD64ri32;
|
|
|
|
}
|
2015-11-11 19:44:31 +08:00
|
|
|
}
|
|
|
|
|
2019-05-25 14:17:47 +08:00
|
|
|
static inline unsigned getINCDECFromLEA(unsigned LEAOpcode, bool IsINC) {
|
|
|
|
switch (LEAOpcode) {
|
|
|
|
default:
|
|
|
|
llvm_unreachable("Unexpected LEA instruction");
|
|
|
|
case X86::LEA32r:
|
|
|
|
case X86::LEA64_32r:
|
|
|
|
return IsINC ? X86::INC32r : X86::DEC32r;
|
|
|
|
case X86::LEA64r:
|
|
|
|
return IsINC ? X86::INC64r : X86::DEC64r;
|
|
|
|
}
|
2015-11-11 19:44:31 +08:00
|
|
|
}
|
|
|
|
|
2019-05-25 14:17:47 +08:00
|
|
|
bool FixupLEAPass::optTwoAddrLEA(MachineBasicBlock::iterator &I,
|
|
|
|
MachineBasicBlock &MBB, bool OptIncDec,
|
|
|
|
bool UseLEAForSP) const {
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineInstr &MI = *I;
|
2015-11-11 19:44:31 +08:00
|
|
|
|
2019-05-25 14:17:47 +08:00
|
|
|
const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
|
|
|
|
const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
|
|
|
|
const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
|
|
|
|
const MachineOperand &Disp = MI.getOperand(1 + X86::AddrDisp);
|
|
|
|
const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
|
2015-11-11 19:44:31 +08:00
|
|
|
|
2019-05-25 14:17:47 +08:00
|
|
|
if (Segment.getReg() != 0 || !Disp.isImm() || Scale.getImm() > 1 ||
|
|
|
|
!TII->isSafeToClobberEFLAGS(MBB, I))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
unsigned DestReg = MI.getOperand(0).getReg();
|
|
|
|
unsigned BaseReg = Base.getReg();
|
|
|
|
unsigned IndexReg = Index.getReg();
|
|
|
|
|
|
|
|
// Don't change stack adjustment LEAs.
|
|
|
|
if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP))
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// LEA64_32 has 64-bit operands but 32-bit result.
|
|
|
|
if (MI.getOpcode() == X86::LEA64_32r) {
|
|
|
|
if (BaseReg != 0)
|
|
|
|
BaseReg = TRI->getSubReg(BaseReg, X86::sub_32bit);
|
|
|
|
if (IndexReg != 0)
|
|
|
|
IndexReg = TRI->getSubReg(IndexReg, X86::sub_32bit);
|
2015-11-11 19:44:31 +08:00
|
|
|
}
|
2019-05-25 14:17:47 +08:00
|
|
|
|
|
|
|
MachineInstr *NewMI = nullptr;
|
|
|
|
|
|
|
|
// Look for lea(%reg1, %reg2), %reg1 or lea(%reg2, %reg1), %reg1
|
|
|
|
// which can be turned into add %reg2, %reg1
|
|
|
|
if (BaseReg != 0 && IndexReg != 0 && Disp.getImm() == 0 &&
|
|
|
|
(DestReg == BaseReg || DestReg == IndexReg)) {
|
|
|
|
unsigned NewOpcode = getADDrrFromLEA(MI.getOpcode());
|
|
|
|
if (DestReg != BaseReg)
|
|
|
|
std::swap(BaseReg, IndexReg);
|
|
|
|
|
|
|
|
if (MI.getOpcode() == X86::LEA64_32r) {
|
|
|
|
// TODO: Do we need the super register implicit use?
|
|
|
|
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
|
|
|
|
.addReg(BaseReg).addReg(IndexReg)
|
|
|
|
.addReg(Base.getReg(), RegState::Implicit)
|
|
|
|
.addReg(Index.getReg(), RegState::Implicit);
|
|
|
|
} else {
|
|
|
|
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
|
|
|
|
.addReg(BaseReg).addReg(IndexReg);
|
|
|
|
}
|
|
|
|
} else if (DestReg == BaseReg && IndexReg == 0) {
|
|
|
|
// This is an LEA with only a base register and a displacement,
|
|
|
|
// We can use ADDri or INC/DEC.
|
|
|
|
|
|
|
|
// Does this LEA have one these forms:
|
|
|
|
// lea %reg, 1(%reg)
|
|
|
|
// lea %reg, -1(%reg)
|
|
|
|
if (OptIncDec && (Disp.getImm() == 1 || Disp.getImm() == -1)) {
|
|
|
|
bool IsINC = Disp.getImm() == 1;
|
|
|
|
unsigned NewOpcode = getINCDECFromLEA(MI.getOpcode(), IsINC);
|
|
|
|
|
|
|
|
if (MI.getOpcode() == X86::LEA64_32r) {
|
|
|
|
// TODO: Do we need the super register implicit use?
|
|
|
|
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
|
|
|
|
.addReg(BaseReg).addReg(Base.getReg(), RegState::Implicit);
|
|
|
|
} else {
|
|
|
|
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
|
|
|
|
.addReg(BaseReg);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
unsigned NewOpcode = getADDriFromLEA(MI.getOpcode(), Disp);
|
|
|
|
if (MI.getOpcode() == X86::LEA64_32r) {
|
|
|
|
// TODO: Do we need the super register implicit use?
|
|
|
|
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
|
|
|
|
.addReg(BaseReg).addImm(Disp.getImm())
|
|
|
|
.addReg(Base.getReg(), RegState::Implicit);
|
|
|
|
} else {
|
|
|
|
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg)
|
|
|
|
.addReg(BaseReg).addImm(Disp.getImm());
|
|
|
|
}
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
return false;
|
|
|
|
|
|
|
|
MBB.erase(I);
|
|
|
|
I = NewMI;
|
|
|
|
return true;
|
2015-11-11 19:44:31 +08:00
|
|
|
}
|
|
|
|
|
2014-06-04 05:01:35 +08:00
|
|
|
void FixupLEAPass::processInstruction(MachineBasicBlock::iterator &I,
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineBasicBlock &MBB) {
|
2013-04-26 04:29:37 +08:00
|
|
|
// Process a load, store, or LEA instruction.
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineInstr &MI = *I;
|
|
|
|
const MCInstrDesc &Desc = MI.getDesc();
|
2016-04-28 13:58:46 +08:00
|
|
|
int AddrOffset = X86II::getMemoryOperandNo(Desc.TSFlags);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (AddrOffset >= 0) {
|
|
|
|
AddrOffset += X86II::getOperandBias(Desc);
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineOperand &p = MI.getOperand(AddrOffset + X86::AddrBaseReg);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (p.isReg() && p.getReg() != X86::ESP) {
|
2019-05-01 01:56:28 +08:00
|
|
|
seekLEAFixup(p, I, MBB);
|
2013-04-26 04:29:37 +08:00
|
|
|
}
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineOperand &q = MI.getOperand(AddrOffset + X86::AddrIndexReg);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (q.isReg() && q.getReg() != X86::ESP) {
|
2019-05-01 01:56:28 +08:00
|
|
|
seekLEAFixup(q, I, MBB);
|
2013-04-26 04:29:37 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-06-04 05:01:35 +08:00
|
|
|
void FixupLEAPass::seekLEAFixup(MachineOperand &p,
|
|
|
|
MachineBasicBlock::iterator &I,
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineBasicBlock &MBB) {
|
|
|
|
MachineBasicBlock::iterator MBI = searchBackwards(p, I, MBB);
|
2016-07-12 11:18:50 +08:00
|
|
|
if (MBI != MachineBasicBlock::iterator()) {
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineInstr *NewMI = postRAConvertToLEA(MBB, MBI);
|
2013-04-26 04:29:37 +08:00
|
|
|
if (NewMI) {
|
|
|
|
++NumLEAs;
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MBI->dump(););
|
2013-04-26 04:29:37 +08:00
|
|
|
// now to replace with an equivalent LEA...
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: "; NewMI->dump(););
|
2019-05-01 01:56:28 +08:00
|
|
|
MBB.erase(MBI);
|
2013-04-26 04:29:37 +08:00
|
|
|
MachineBasicBlock::iterator J =
|
2014-06-04 05:01:35 +08:00
|
|
|
static_cast<MachineBasicBlock::iterator>(NewMI);
|
2019-05-01 01:56:28 +08:00
|
|
|
processInstruction(J, MBB);
|
2013-04-26 04:29:37 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2018-11-01 22:57:07 +08:00
|
|
|
void FixupLEAPass::processInstructionForSlowLEA(MachineBasicBlock::iterator &I,
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineBasicBlock &MBB) {
|
2016-07-12 11:18:50 +08:00
|
|
|
MachineInstr &MI = *I;
|
2019-04-02 08:50:58 +08:00
|
|
|
const unsigned Opcode = MI.getOpcode();
|
2018-12-22 09:34:47 +08:00
|
|
|
|
|
|
|
const MachineOperand &Dst = MI.getOperand(0);
|
|
|
|
const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
|
|
|
|
const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
|
|
|
|
const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
|
|
|
|
const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
|
|
|
|
const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
|
|
|
|
|
|
|
|
if (Segment.getReg() != 0 || !Offset.isImm() ||
|
2019-05-01 01:56:28 +08:00
|
|
|
!TII->isSafeToClobberEFLAGS(MBB, I))
|
2014-05-20 16:55:50 +08:00
|
|
|
return;
|
2018-12-22 09:34:47 +08:00
|
|
|
const unsigned DstR = Dst.getReg();
|
|
|
|
const unsigned SrcR1 = Base.getReg();
|
|
|
|
const unsigned SrcR2 = Index.getReg();
|
2014-05-20 16:55:50 +08:00
|
|
|
if ((SrcR1 == 0 || SrcR1 != DstR) && (SrcR2 == 0 || SrcR2 != DstR))
|
|
|
|
return;
|
2018-12-22 09:34:47 +08:00
|
|
|
if (Scale.getImm() > 1)
|
2014-05-20 16:55:50 +08:00
|
|
|
return;
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; I->dump(););
|
|
|
|
LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
|
2014-06-09 06:29:17 +08:00
|
|
|
MachineInstr *NewMI = nullptr;
|
2014-05-20 16:55:50 +08:00
|
|
|
// Make ADD instruction for two registers writing to LEA's destination
|
|
|
|
if (SrcR1 != 0 && SrcR2 != 0) {
|
2017-05-18 16:11:50 +08:00
|
|
|
const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(Opcode));
|
2018-12-22 09:34:47 +08:00
|
|
|
const MachineOperand &Src = SrcR1 == DstR ? Index : Base;
|
2017-05-18 16:11:50 +08:00
|
|
|
NewMI =
|
2019-05-01 01:56:28 +08:00
|
|
|
BuildMI(MBB, I, MI.getDebugLoc(), ADDrr, DstR).addReg(DstR).add(Src);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2014-05-20 16:55:50 +08:00
|
|
|
}
|
|
|
|
// Make ADD instruction for immediate
|
2018-12-22 09:34:47 +08:00
|
|
|
if (Offset.getImm() != 0) {
|
2017-05-18 16:11:50 +08:00
|
|
|
const MCInstrDesc &ADDri =
|
2018-12-22 09:34:47 +08:00
|
|
|
TII->get(getADDriFromLEA(Opcode, Offset));
|
|
|
|
const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index;
|
2019-05-01 01:56:28 +08:00
|
|
|
NewMI = BuildMI(MBB, I, MI.getDebugLoc(), ADDri, DstR)
|
2017-01-13 17:58:52 +08:00
|
|
|
.add(SrcR)
|
2018-12-22 09:34:47 +08:00
|
|
|
.addImm(Offset.getImm());
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2014-05-20 16:55:50 +08:00
|
|
|
}
|
|
|
|
if (NewMI) {
|
2019-05-01 01:56:28 +08:00
|
|
|
MBB.erase(I);
|
2017-05-18 16:11:50 +08:00
|
|
|
I = NewMI;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
MachineInstr *
|
|
|
|
FixupLEAPass::processInstrForSlow3OpLEA(MachineInstr &MI,
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineBasicBlock &MBB) {
|
2019-04-02 08:50:58 +08:00
|
|
|
const unsigned LEAOpcode = MI.getOpcode();
|
2017-05-18 16:11:50 +08:00
|
|
|
|
2018-12-22 09:34:47 +08:00
|
|
|
const MachineOperand &Dst = MI.getOperand(0);
|
|
|
|
const MachineOperand &Base = MI.getOperand(1 + X86::AddrBaseReg);
|
|
|
|
const MachineOperand &Scale = MI.getOperand(1 + X86::AddrScaleAmt);
|
|
|
|
const MachineOperand &Index = MI.getOperand(1 + X86::AddrIndexReg);
|
|
|
|
const MachineOperand &Offset = MI.getOperand(1 + X86::AddrDisp);
|
|
|
|
const MachineOperand &Segment = MI.getOperand(1 + X86::AddrSegmentReg);
|
2017-05-18 16:11:50 +08:00
|
|
|
|
2018-07-20 00:42:15 +08:00
|
|
|
if (!(TII->isThreeOperandsLEA(MI) ||
|
2017-05-18 16:11:50 +08:00
|
|
|
hasInefficientLEABaseReg(Base, Index)) ||
|
2019-05-01 01:56:28 +08:00
|
|
|
!TII->isSafeToClobberEFLAGS(MBB, MI) ||
|
2017-05-18 16:11:50 +08:00
|
|
|
Segment.getReg() != X86::NoRegister)
|
|
|
|
return nullptr;
|
|
|
|
|
2019-04-02 08:50:58 +08:00
|
|
|
unsigned DstR = Dst.getReg();
|
|
|
|
unsigned BaseR = Base.getReg();
|
|
|
|
unsigned IndexR = Index.getReg();
|
2017-05-18 16:11:50 +08:00
|
|
|
unsigned SSDstR =
|
|
|
|
(LEAOpcode == X86::LEA64_32r) ? getX86SubSuperRegister(DstR, 64) : DstR;
|
|
|
|
bool IsScale1 = Scale.getImm() == 1;
|
|
|
|
bool IsInefficientBase = isInefficientLEAReg(BaseR);
|
|
|
|
bool IsInefficientIndex = isInefficientLEAReg(IndexR);
|
|
|
|
|
|
|
|
// Skip these cases since it takes more than 2 instructions
|
|
|
|
// to replace the LEA instruction.
|
|
|
|
if (IsInefficientBase && SSDstR == BaseR && !IsScale1)
|
|
|
|
return nullptr;
|
|
|
|
if (LEAOpcode == X86::LEA64_32r && IsInefficientBase &&
|
|
|
|
(IsInefficientIndex || !IsScale1))
|
|
|
|
return nullptr;
|
|
|
|
|
|
|
|
const DebugLoc DL = MI.getDebugLoc();
|
|
|
|
const MCInstrDesc &ADDrr = TII->get(getADDrrFromLEA(LEAOpcode));
|
|
|
|
const MCInstrDesc &ADDri = TII->get(getADDriFromLEA(LEAOpcode, Offset));
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "FixLEA: Candidate to replace:"; MI.dump(););
|
|
|
|
LLVM_DEBUG(dbgs() << "FixLEA: Replaced by: ";);
|
2017-05-18 16:11:50 +08:00
|
|
|
|
|
|
|
// First try to replace LEA with one or two (for the 3-op LEA case)
|
|
|
|
// add instructions:
|
|
|
|
// 1.lea (%base,%index,1), %base => add %index,%base
|
|
|
|
// 2.lea (%base,%index,1), %index => add %base,%index
|
|
|
|
if (IsScale1 && (DstR == BaseR || DstR == IndexR)) {
|
|
|
|
const MachineOperand &Src = DstR == BaseR ? Index : Base;
|
|
|
|
MachineInstr *NewMI =
|
2019-05-01 01:56:28 +08:00
|
|
|
BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Src);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
// Create ADD instruction for the Offset in case of 3-Ops LEA.
|
|
|
|
if (hasLEAOffset(Offset)) {
|
2019-05-01 01:56:28 +08:00
|
|
|
NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
}
|
|
|
|
return NewMI;
|
|
|
|
}
|
|
|
|
// If the base is inefficient try switching the index and base operands,
|
|
|
|
// otherwise just break the 3-Ops LEA inst into 2-Ops LEA + ADD instruction:
|
|
|
|
// lea offset(%base,%index,scale),%dst =>
|
|
|
|
// lea (%base,%index,scale); add offset,%dst
|
|
|
|
if (!IsInefficientBase || (!IsInefficientIndex && IsScale1)) {
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
|
2017-05-18 16:11:50 +08:00
|
|
|
.add(Dst)
|
|
|
|
.add(IsInefficientBase ? Index : Base)
|
|
|
|
.add(Scale)
|
|
|
|
.add(IsInefficientBase ? Base : Index)
|
|
|
|
.addImm(0)
|
|
|
|
.add(Segment);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
// Create ADD instruction for the Offset in case of 3-Ops LEA.
|
|
|
|
if (hasLEAOffset(Offset)) {
|
2019-05-01 01:56:28 +08:00
|
|
|
NewMI = BuildMI(MBB, MI, DL, ADDri, DstR).addReg(DstR).add(Offset);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
}
|
|
|
|
return NewMI;
|
|
|
|
}
|
|
|
|
// Handle the rest of the cases with inefficient base register:
|
|
|
|
assert(SSDstR != BaseR && "SSDstR == BaseR should be handled already!");
|
|
|
|
assert(IsInefficientBase && "efficient base should be handled already!");
|
|
|
|
|
|
|
|
// lea (%base,%index,1), %dst => mov %base,%dst; add %index,%dst
|
|
|
|
if (IsScale1 && !hasLEAOffset(Offset)) {
|
2018-01-26 12:49:26 +08:00
|
|
|
bool BIK = Base.isKill() && BaseR != IndexR;
|
2019-05-01 01:56:28 +08:00
|
|
|
TII->copyPhysReg(MBB, MI, DL, DstR, BaseR, BIK);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(MI.getPrevNode()->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
|
|
|
|
MachineInstr *NewMI =
|
2019-05-01 01:56:28 +08:00
|
|
|
BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Index);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
return NewMI;
|
2014-05-20 16:55:50 +08:00
|
|
|
}
|
2017-05-18 16:11:50 +08:00
|
|
|
// lea offset(%base,%index,scale), %dst =>
|
|
|
|
// lea offset( ,%index,scale), %dst; add %base,%dst
|
2019-05-01 01:56:28 +08:00
|
|
|
MachineInstr *NewMI = BuildMI(MBB, MI, DL, TII->get(LEAOpcode))
|
2017-05-18 16:11:50 +08:00
|
|
|
.add(Dst)
|
|
|
|
.addReg(0)
|
|
|
|
.add(Scale)
|
|
|
|
.add(Index)
|
|
|
|
.add(Offset)
|
|
|
|
.add(Segment);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
|
2019-05-01 01:56:28 +08:00
|
|
|
NewMI = BuildMI(MBB, MI, DL, ADDrr, DstR).addReg(DstR).add(Base);
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(NewMI->dump(););
|
2017-05-18 16:11:50 +08:00
|
|
|
return NewMI;
|
2014-05-20 16:55:50 +08:00
|
|
|
}
|