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//===--------------------- SummaryView.h ------------------------*- C++ -*-===//
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2018-03-09 21:52:03 +08:00
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//
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2019-01-19 16:50:56 +08:00
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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2018-03-09 21:52:03 +08:00
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//
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//===----------------------------------------------------------------------===//
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/// \file
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///
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/// This file implements the summary view.
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///
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/// The goal of the summary view is to give a very quick overview of the
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/// performance throughput. Below is an example of summary view:
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///
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///
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2018-05-23 23:59:27 +08:00
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/// Iterations: 300
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/// Instructions: 900
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/// Total Cycles: 610
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/// Dispatch Width: 2
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/// IPC: 1.48
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/// Block RThroughput: 2.0
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///
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/// The summary view collects a few performance numbers. The two main
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/// performance indicators are 'Total Cycles' and IPC (Instructions Per Cycle).
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_TOOLS_LLVM_MCA_SUMMARYVIEW_H
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#define LLVM_TOOLS_LLVM_MCA_SUMMARYVIEW_H
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2018-05-23 23:59:27 +08:00
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/MC/MCSchedule.h"
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#include "llvm/MCA/View.h"
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#include "llvm/Support/raw_ostream.h"
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2018-10-30 23:56:08 +08:00
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namespace llvm {
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2018-03-09 21:52:03 +08:00
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namespace mca {
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2018-05-01 23:54:18 +08:00
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/// A view that collects and prints a few performance numbers.
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class SummaryView : public View {
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const llvm::MCSchedModel &SM;
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llvm::ArrayRef<llvm::MCInst> Source;
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const unsigned DispatchWidth;
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unsigned LastInstructionIdx;
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unsigned TotalCycles;
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// The total number of micro opcodes contributed by a block of instructions.
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unsigned NumMicroOps;
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[MCA] Highlight kernel bottlenecks in the summary view.
This patch adds a new flag named -bottleneck-analysis to print out information
about throughput bottlenecks.
MCA knows how to identify and classify dynamic dispatch stalls. However, it
doesn't know how to analyze and highlight kernel bottlenecks. The goal of this
patch is to teach MCA how to correlate increases in backend pressure to backend
stalls (and therefore, the loss of throughput).
From a Scheduler point of view, backend pressure is a function of the scheduler
buffer usage (i.e. how the number of uOps in the scheduler buffers changes over
time). Backend pressure increases (or decreases) when there is a mismatch
between the number of opcodes dispatched, and the number of opcodes issued in
the same cycle. Since buffer resources are limited, continuous increases in
backend pressure would eventually leads to dispatch stalls. So, there is a
strong correlation between dispatch stalls, and how backpressure changed over
time.
This patch teaches how to identify situations where backend pressure increases
due to:
- unavailable pipeline resources.
- data dependencies.
Data dependencies may delay execution of instructions and therefore increase the
time that uOps have to spend in the scheduler buffers. That often translates to
an increase in backend pressure which may eventually lead to a bottleneck.
Contention on pipeline resources may also delay execution of instructions, and
lead to a temporary increase in backend pressure.
Internally, the Scheduler classifies instructions based on whether register /
memory operands are available or not.
An instruction is marked as "ready to execute" only if data dependencies are
fully resolved.
Every cycle, the Scheduler attempts to execute all instructions that are ready
to execute. If an instruction cannot execute because of unavailable pipeline
resources, then the Scheduler internally updates a BusyResourceUnits mask with
the ID of each unavailable resource.
ExecuteStage is responsible for tracking changes in backend pressure. If backend
pressure increases during a cycle because of contention on pipeline resources,
then ExecuteStage sends a "backend pressure" event to the listeners.
That event would contain information about instructions delayed by resource
pressure, as well as the BusyResourceUnits mask.
Note that ExecuteStage also knows how to identify situations where backpressure
increased because of delays introduced by data dependencies.
The SummaryView observes "backend pressure" events and prints out a "bottleneck
report".
Example of bottleneck report:
```
Cycles with backend pressure increase [ 99.89% ]
Throughput Bottlenecks:
Resource Pressure [ 0.00% ]
Data Dependencies: [ 99.89% ]
- Register Dependencies [ 0.00% ]
- Memory Dependencies [ 99.89% ]
```
A bottleneck report is printed out only if increases in backend pressure
eventually caused backend stalls.
About the time complexity:
Time complexity is linear in the number of instructions in the
Scheduler::PendingSet.
The average slowdown tends to be in the range of ~5-6%.
For memory intensive kernels, the slowdown can be significant if flag
-noalias=false is specified. In the worst case scenario I have observed a
slowdown of ~30% when flag -noalias=false was specified.
We can definitely recover part of that slowdown if we optimize class LSUnit (by
doing extra bookkeeping to speedup queries). For now, this new analysis is
disabled by default, and it can be enabled via flag -bottleneck-analysis. Users
of MCA as a library can enable the generation of pressure events through the
constructor of ExecuteStage.
This patch partially addresses https://bugs.llvm.org/show_bug.cgi?id=37494
Differential Revision: https://reviews.llvm.org/D58728
llvm-svn: 355308
2019-03-04 19:52:34 +08:00
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2020-08-20 02:53:39 +08:00
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struct DisplayValues {
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unsigned Instructions;
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unsigned Iterations;
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unsigned TotalInstructions;
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unsigned TotalCycles;
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unsigned DispatchWidth;
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unsigned TotalUOps;
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double IPC;
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double UOpsPerCycle;
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double BlockRThroughput;
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};
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2018-06-01 22:35:21 +08:00
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// For each processor resource, this vector stores the cumulative number of
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// resource cycles consumed by the analyzed code block.
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llvm::SmallVector<unsigned, 8> ProcResourceUsage;
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// Each processor resource is associated with a so-called processor resource
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// mask. This vector allows to correlate processor resource IDs with processor
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// resource masks. There is exactly one element per each processor resource
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// declared by the scheduling model.
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llvm::SmallVector<uint64_t, 8> ProcResourceMasks;
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2019-02-20 22:53:18 +08:00
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// Used to map resource indices to actual processor resource IDs.
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llvm::SmallVector<unsigned, 8> ResIdx2ProcResID;
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2020-08-20 02:53:39 +08:00
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/// Compute the data we want to print out in the object DV.
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void collectData(DisplayValues &DV) const;
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2018-03-09 21:52:03 +08:00
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public:
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SummaryView(const llvm::MCSchedModel &Model, llvm::ArrayRef<llvm::MCInst> S,
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unsigned Width);
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2019-04-17 14:02:05 +08:00
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void onCycleEnd() override { ++TotalCycles; }
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void onEvent(const HWInstructionEvent &Event) override;
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void printView(llvm::raw_ostream &OS) const override;
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StringRef getNameAsString() const override { return "SummaryView"; }
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json::Value toJSON() const override;
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};
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} // namespace mca
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} // namespace llvm
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#endif
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