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llvm-project/lld/test/ELF/arm-thumb-pc8-weak.s

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[LLD][ELF][ARM] Implement Thumb pc-relative relocations for adr and ldr MC will now output the R_ARM_THM_PC8, R_ARM_THM_PC12 and R_ARM_THM_PREL_11_0 relocations. These are short-ranged relocations that are used to implement the adr rd, literal and ldr rd, literal pseudo instructions. The instructions use a new RelExpr called R_ARM_PCA in order to calculate the required S + A - Pa expression, where Pa is AlignDown(P, 4) as the instructions add their immediate to AlignDown(PC, 4). We also do not want these relocations to generate or resolve against a PLT entry as the range of these relocations is so short they would never reach. The R_ARM_THM_PC8 has a special encoding convention for the relocation addend, the immediate field is unsigned, yet the addend must be -4 to account for the Thumb PC bias. The ABI (not the architecture) uses the convention that the 8-byte immediate of 0xff represents -4. Differential Revision: https://reviews.llvm.org/D75042
2020-02-24 03:46:46 +08:00
// REQUIRES: arm
[LLD][ELF][ARM] Replace adr, ldr with .inst .reloc in test [NFC] After D78301 MC no longer emits a relocation for this case. Change to use .inst and .reloc to synthesize the same instruction and relocation. One more test case I missed.
2020-04-22 18:57:13 +08:00
// RUN: llvm-mc --arm-add-build-attributes -filetype=obj -triple=thumbv5-none-linux-gnueabi %s -o %t
[LLD][ELF][ARM] Implement Thumb pc-relative relocations for adr and ldr MC will now output the R_ARM_THM_PC8, R_ARM_THM_PC12 and R_ARM_THM_PREL_11_0 relocations. These are short-ranged relocations that are used to implement the adr rd, literal and ldr rd, literal pseudo instructions. The instructions use a new RelExpr called R_ARM_PCA in order to calculate the required S + A - Pa expression, where Pa is AlignDown(P, 4) as the instructions add their immediate to AlignDown(PC, 4). We also do not want these relocations to generate or resolve against a PLT entry as the range of these relocations is so short they would never reach. The R_ARM_THM_PC8 has a special encoding convention for the relocation addend, the immediate field is unsigned, yet the addend must be -4 to account for the Thumb PC bias. The ABI (not the architecture) uses the convention that the 8-byte immediate of 0xff represents -4. Differential Revision: https://reviews.llvm.org/D75042
2020-02-24 03:46:46 +08:00
// RUN: ld.lld %t -o %t2
[ELF][test] Delete unneeded --triple=thumb* from llvm-objdump RUN lines
2021-07-29 03:47:12 +08:00
// RUN: llvm-objdump --no-show-raw-insn -d %t2 | FileCheck %s
[LLD][ELF][ARM] Implement Thumb pc-relative relocations for adr and ldr MC will now output the R_ARM_THM_PC8, R_ARM_THM_PC12 and R_ARM_THM_PREL_11_0 relocations. These are short-ranged relocations that are used to implement the adr rd, literal and ldr rd, literal pseudo instructions. The instructions use a new RelExpr called R_ARM_PCA in order to calculate the required S + A - Pa expression, where Pa is AlignDown(P, 4) as the instructions add their immediate to AlignDown(PC, 4). We also do not want these relocations to generate or resolve against a PLT entry as the range of these relocations is so short they would never reach. The R_ARM_THM_PC8 has a special encoding convention for the relocation addend, the immediate field is unsigned, yet the addend must be -4 to account for the Thumb PC bias. The ABI (not the architecture) uses the convention that the 8-byte immediate of 0xff represents -4. Differential Revision: https://reviews.llvm.org/D75042
2020-02-24 03:46:46 +08:00
/// Check that the ARM ABI rules for undefined weak symbols are applied.
/// Relative relocations are resolved to the place. Although we can't encode
/// this for R_ARM_THM_PC8 as negative addends are not permitted. Use smallest
/// available value. These are corner cases.
.syntax unified
.weak target
.type target, %function
.text
.global _start
_start:
/// R_ARM_THM_PC8
[LLD][ELF][ARM] Replace adr, ldr with .inst .reloc in test [NFC] After D78301 MC no longer emits a relocation for this case. Change to use .inst and .reloc to synthesize the same instruction and relocation. One more test case I missed.
2020-04-22 18:57:13 +08:00
/// adr r0, target
.inst.n 0xa0ff
.reloc 0, R_ARM_THM_PC8, target
/// ldr r0, target
.inst.n 0x48ff
.reloc 2, R_ARM_THM_PC8, target
// CHECK: 000200b4 <_start>:
// CHECK-NEXT: 200b4: adr r0, #0
[LLD][ELF][ARM] Implement Thumb pc-relative relocations for adr and ldr MC will now output the R_ARM_THM_PC8, R_ARM_THM_PC12 and R_ARM_THM_PREL_11_0 relocations. These are short-ranged relocations that are used to implement the adr rd, literal and ldr rd, literal pseudo instructions. The instructions use a new RelExpr called R_ARM_PCA in order to calculate the required S + A - Pa expression, where Pa is AlignDown(P, 4) as the instructions add their immediate to AlignDown(PC, 4). We also do not want these relocations to generate or resolve against a PLT entry as the range of these relocations is so short they would never reach. The R_ARM_THM_PC8 has a special encoding convention for the relocation addend, the immediate field is unsigned, yet the addend must be -4 to account for the Thumb PC bias. The ABI (not the architecture) uses the convention that the 8-byte immediate of 0xff represents -4. Differential Revision: https://reviews.llvm.org/D75042
2020-02-24 03:46:46 +08:00
// CHECK-NEXT: ldr r0, [pc, #0]