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llvm-project/llvm/test/CodeGen/Mips/fcopysign-f32-f64.ll

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Revert "[mips] Fix the target specific instruction verifier" This reverts commit r320974. The commit message lacked the Differential Revison: line. llvm-svn: 320975
2017-12-18 20:30:34 +08:00
; RUN: llc < %s -march=mips64el -mcpu=mips4 -target-abi=n64 | \
; RUN: FileCheck %s -check-prefixes=ALL,64
; RUN: llc < %s -march=mips64el -mcpu=mips64 -target-abi=n64 | \
; RUN: FileCheck %s -check-prefixes=ALL,64
; RUN: llc < %s -march=mips64el -mcpu=mips64r2 -target-abi=n64 | \
; RUN: FileCheck %s -check-prefixes=ALL,64R2
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
declare double @copysign(double, double) nounwind readnone
declare float @copysignf(float, float) nounwind readnone
define float @func2(float %d, double %f) nounwind readnone {
entry:
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
2016-02-29 23:58:12 +08:00
; ALL-LABEL: func2:
[mips] Implement MipsTargetMachine::getInstrItineraryData(). llvm-svn: 186227
2013-07-13 07:33:22 +08:00
; 64-DAG: lui $[[T0:[0-9]+]], 32767
; 64-DAG: ori $[[MSK0:[0-9]+]], $[[T0]], 65535
; 64-DAG: and $[[AND0:[0-9]+]], ${{[0-9]+}}, $[[MSK0]]
; 64-DAG: dsrl $[[DSRL:[0-9]+]], ${{[0-9]+}}, 63
; 64-DAG: sll $[[SLL0:[0-9]+]], $[[DSRL]], 0
; 64-DAG: sll $[[SLL1:[0-9]+]], $[[SLL0]], 31
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[SLL1]]
; 64: mtc1 $[[OR]], $f0
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
[mips] Make isel select the correct DEXT variant up front. Summary: Previously, it would always select DEXT and substitute any invalid matches for DEXTU/DEXTM during MipsMCCodeEmitter::encodeInstruction(). This works but causes problems when adding range checked immediates to IAS. Now isel selects the correct variant up front. Reviewers: vkalintiris Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D16810 llvm-svn: 262229
2016-02-29 23:26:54 +08:00
; 64R2: dextu ${{[0-9]+}}, ${{[0-9]+}}, 63, 1
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
; 64R2: ins $[[INS:[0-9]+]], ${{[0-9]+}}, 31, 1
; 64R2: mtc1 $[[INS]], $f0
%add = fadd float %d, 1.000000e+00
%conv = fptrunc double %f to float
%call = tail call float @copysignf(float %add, float %conv) nounwind readnone
ret float %call
}
define double @func3(double %d, float %f) nounwind readnone {
entry:
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
2016-02-29 23:58:12 +08:00
; ALL-LABEL: func3:
[mips] Recommit: "N64 static relocation model support" This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! This version corrects a "Conditional jump or move depends on uninitialised value(s)" error detected by valgrind present in the original commit. Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293279
2017-01-27 19:36:52 +08:00
; 64: mfc1 $[[MFC:[0-9]+]], $f13
Revert "[mips] N64 static relocation model support" This reverts commit r293164. There are multiple tests failing. llvm-svn: 293170
2017-01-26 18:46:07 +08:00
; 64: daddiu $[[R1:[0-9]+]], $zero, 1
[mips] Recommit: "N64 static relocation model support" This patch makes one change to GOT handling and two changes to N64's relocation model handling. Furthermore, the jumptable encodings have been corrected for static N64. Big GOT handling is now done via a new SDNode MipsGotHi - this node is unconditionally lowered to an lui instruction. The first change to N64's relocation handling is the lifting of the restriction that N64 always uses PIC. Now it is possible to target static environments. The second change adds support for 64 bit symbols and enables them by default. Previously N64 had patterns for sym32 mode only. In this mode all symbols are assumed to have 32 bit addresses. sym32 mode support is selectable with attribute 'sym32'. A follow on patch for clang will add the necessary frontend parameter. This partially resolves PR/23485. Thanks to Brooks Davis for reporting the issue! This version corrects a "Conditional jump or move depends on uninitialised value(s)" error detected by valgrind present in the original commit. Reviewers: dsanders, seanbruno, zoran.jovanovic, vkalintiris Differential Revision: https://reviews.llvm.org/D23652 llvm-svn: 293279
2017-01-27 19:36:52 +08:00
; 64: dmfc1 $[[R0:[0-9]+]], ${{.*}}
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
; 64: dsll $[[R2:[0-9]+]], $[[R1]], 63
; 64: daddiu $[[R3:[0-9]+]], $[[R2]], -1
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
2016-02-29 23:58:12 +08:00
; 64: and $[[AND0:[0-9]+]], $[[R0]], $[[R3]]
[mips] interAptiv based generic schedule model This scheduler describes a processor which covers all MIPS ISAs based around the interAptiv and P5600 timings. Reviewers: vkalintiris, dsanders Differential Revision: https://reviews.llvm.org/D23551 llvm-svn: 280374
2016-09-01 22:53:53 +08:00
; 64: srl $[[SRL:[0-9]+]], $[[MFC:[0-9]+]], 31
; 64: dsll $[[DSLL:[0-9]+]], $[[SRL]], 63
[mips] Do not use SLL for ANY_EXTEND nodes as the high bits are undefined. Reviewers: dsanders Subscribers: dsanders, llvm-commits Differential Revision: http://reviews.llvm.org/D15420 llvm-svn: 262230
2016-02-29 23:58:12 +08:00
; 64: or $[[OR:[0-9]+]], $[[AND0]], $[[DSLL]]
; 64: dmtc1 $[[OR]], $f0
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
; 64R2: ext ${{[0-9]+}}, ${{[0-9]+}}, 31, 1
[mips] Pick the right variant of DINS upfront and enable target instruction verification This patch complements D16810 "[mips] Make isel select the correct DEXT variant up front.". Now ISel picks the right variant of DINS, so now there is no need to replace DINS with the appropriate variant during MipsMCCodeEmitter::encodeInstruction(). This patch also enables target specific instruction verification for ins, dins, dinsm, dinsu, ext, dext, dextm, dextu. These instructions have constraints that are checked when generating MipsISD::Ins and MipsISD::Ext nodes, but these constraints are not checked during instruction selection. Adding machine verification should catch outstanding cases. Finally, correct a bug that instruction verification uncovered, where the position operand of a DINSU generated during lowering was being silently and accidently corrected to the correct value. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D34809 llvm-svn: 313254
2017-09-14 18:58:00 +08:00
; 64R2: dinsu $[[INS:[0-9]+]], ${{[0-9]+}}, 63, 1
Fix bugs in lowering of FCOPYSIGN nodes. - FCOPYSIGN nodes that have operands of different types were not handled. - Different code was generated depending on the endianness of the target. Additionally, code is added that emits INS and EXT instructions, if they are supported by target (they are R2 instructions). llvm-svn: 154540
2012-04-12 06:13:04 +08:00
; 64R2: dmtc1 $[[INS]], $f0
%add = fadd double %d, 1.000000e+00
%conv = fpext float %f to double
%call = tail call double @copysign(double %add, double %conv) nounwind readnone
ret double %call
}