forked from OSchip/llvm-project
38 lines
1.1 KiB
LLVM
38 lines
1.1 KiB
LLVM
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; REQUIRES: asserts
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; RUN: llc < %s -mtriple=armv8r-eabi -mcpu=cortex-a57 -misched-postra -enable-misched -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s
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;
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@a = global i32 0, align 4
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@b = global i32 0, align 4
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@c = global i32 0, align 4
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; CHECK: ********** MI Scheduling **********
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; We need second, post-ra scheduling to have LDM instruction combined from single-loads
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; CHECK: ********** MI Scheduling **********
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; CHECK: LDMIA_UPD
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; CHECK: rdefs left
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; CHECK-NEXT: Latency : 4
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; CHECK: Successors:
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; CHECK: data
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; CHECK-SAME: Latency=1
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; CHECK-NEXT: data
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; CHECK-SAME: Latency=3
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; CHECK-NEXT: data
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; CHECK-SAME: Latency=3
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; CHECK-NEXT: data
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; CHECK-SAME: Latency=4
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define i32 @bar(i32 %a1, i32 %b1, i32 %c1) minsize optsize {
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%1 = load i32, i32* @a, align 4
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%2 = load i32, i32* @b, align 4
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%3 = load i32, i32* @c, align 4
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%ptr_after = getelementptr i32, i32* @a, i32 3
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%ptr_val = ptrtoint i32* %ptr_after to i32
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%mul1 = mul i32 %ptr_val, %1
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%mul2 = mul i32 %mul1, %2
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%mul3 = mul i32 %mul2, %3
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ret i32 %mul3
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}
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