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llvm-project/llvm/test/CodeGen/Mips/selectcc.ll

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[mips] Make Static a default relocation model for MIPS codegen This change follows up defaults for GCC and Clang, so LLVM does not differ from them. While number of the test files are touched with this change, they all keep the old (expected) behaviour with the explicit option: "-relocation-model=pic" The tests that have not been touched are insensitive to relocation model. Differential Revision: http://reviews.llvm.org/D17995 llvm-svn: 265949
2016-04-11 23:24:23 +08:00
; RUN: llc -march=mipsel -mcpu=mips32 -relocation-model=pic < %s
; RUN: llc -march=mipsel -mcpu=mips32 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED
; RUN: llc -march=mipsel -mcpu=mips32r2 -relocation-model=pic < %s
; RUN: llc -march=mipsel -mcpu=mips32r2 -pre-RA-sched=source -relocation-model=pic < %s | FileCheck %s --check-prefix=SOURCE-SCHED
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll. llvm-svn: 160329
2012-07-17 07:56:51 +08:00
@gf0 = external global float
@gf1 = external global float
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
@gd0 = external global double
@gd1 = external global double
Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll. llvm-svn: 160329
2012-07-17 07:56:51 +08:00
define float @select_cc_f32(float %a, float %b) nounwind {
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
entry:
Track IR ordering of SelectionDAG nodes 4/4. Unit test cases for -pre-RA-sched=source. llvm-svn: 182706
2013-05-25 11:26:51 +08:00
; SOURCE-SCHED: lui
; SOURCE-SCHED: addiu
; SOURCE-SCHED: addu
; SOURCE-SCHED: lw
; SOURCE-SCHED: sw
; SOURCE-SCHED: lw
; SOURCE-SCHED: lui
; SOURCE-SCHED: sw
SelectionDAG: Don't use MVT::Other to determine legality of ISD::SELECT_CC The SelectionDAG bad a special case for ISD::SELECT_CC, where it would allow targets to specify: setOperationAction(ISD::SELECT_CC, MVT::Other, Expand); to indicate that they wanted to expand ISD::SELECT_CC for all types. This wasn't applied correctly everywhere, and it makes writing new DAG patterns with ISD::SELECT_CC difficult. llvm-svn: 210541
2014-06-11 00:01:29 +08:00
; SOURCE-SCHED: lw
; SOURCE-SCHED: lwc1
Track IR ordering of SelectionDAG nodes 4/4. Unit test cases for -pre-RA-sched=source. llvm-svn: 182706
2013-05-25 11:26:51 +08:00
; SOURCE-SCHED: mtc1
Revert "[mips] Fix c.<cc>.<fmt> instruction definition." This reverts commit r281022. Mips buildbot broke, due to unhandled register class FCC. llvm-svn: 281033
2016-09-09 19:06:01 +08:00
; SOURCE-SCHED: c.olt.s
Track IR ordering of SelectionDAG nodes 4/4. Unit test cases for -pre-RA-sched=source. llvm-svn: 182706
2013-05-25 11:26:51 +08:00
; SOURCE-SCHED: jr
Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll. llvm-svn: 160329
2012-07-17 07:56:51 +08:00
store float 0.000000e+00, float* @gf0, align 4
store float 1.000000e+00, float* @gf1, align 4
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
%cmp = fcmp olt float %a, %b
%conv = zext i1 %cmp to i32
Fix function select_cc_f32 in test/CodeGen/Mips/selectcc.ll. llvm-svn: 160329
2012-07-17 07:56:51 +08:00
%conv1 = sitofp i32 %conv to float
ret float %conv1
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC. llvm-svn: 160064
2012-07-12 03:32:27 +08:00
}
define double @select_cc_f64(double %a, double %b) nounwind {
entry:
store double 0.000000e+00, double* @gd0, align 8
store double 1.000000e+00, double* @gd1, align 8
%cmp = fcmp olt double %a, %b
%conv = zext i1 %cmp to i32
%conv1 = sitofp i32 %conv to double
ret double %conv1
}