llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-fadd-scalar.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu                                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=SSE
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx                      -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=NO_AVX512F --check-prefix=AVX
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f                  -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=NO_AVX512VL --check-prefix=AVX512ALL --check-prefix=AVX512F
# RUN: llc -mtriple=x86_64-linux-gnu -mattr=+avx512f -mattr=+avx512vl -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL --check-prefix=AVX512ALL --check-prefix=AVX512VL
--- |

  define float @test_fadd_float(float %arg1, float %arg2) {
    %ret = fadd float %arg1, %arg2
    ret float %ret
  }

  define double @test_fadd_double(double %arg1, double %arg2) {
    %ret = fadd double %arg1, %arg2
    ret double %ret
  }

...
---
name:            test_fadd_float
alignment:       4
legalized:       true
regBankSelected: true
#
registers:
  - { id: 0, class: vecr, preferred-register: '' }
  - { id: 1, class: vecr, preferred-register: '' }
  - { id: 2, class: vecr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
#
#
body:             |
  bb.1 (%ir-block.0):
    liveins: %xmm0, %xmm1

    ; SSE-LABEL: name: test_fadd_float
    ; SSE: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
    ; SSE: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
    ; SSE: [[ADDSSrr:%[0-9]+]]:fr32 = ADDSSrr [[COPY]], [[COPY1]]
    ; SSE: %xmm0 = COPY [[ADDSSrr]]
    ; SSE: RET 0, implicit %xmm0
    ; AVX-LABEL: name: test_fadd_float
    ; AVX: [[COPY:%[0-9]+]]:fr32 = COPY %xmm0
    ; AVX: [[COPY1:%[0-9]+]]:fr32 = COPY %xmm1
    ; AVX: [[VADDSSrr:%[0-9]+]]:fr32 = VADDSSrr [[COPY]], [[COPY1]]
    ; AVX: %xmm0 = COPY [[VADDSSrr]]
    ; AVX: RET 0, implicit %xmm0
    ; AVX512F-LABEL: name: test_fadd_float
    ; AVX512F: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
    ; AVX512F: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
    ; AVX512F: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY]], [[COPY1]]
    ; AVX512F: %xmm0 = COPY [[VADDSSZrr]]
    ; AVX512F: RET 0, implicit %xmm0
    ; AVX512VL-LABEL: name: test_fadd_float
    ; AVX512VL: [[COPY:%[0-9]+]]:fr32x = COPY %xmm0
    ; AVX512VL: [[COPY1:%[0-9]+]]:fr32x = COPY %xmm1
    ; AVX512VL: [[VADDSSZrr:%[0-9]+]]:fr32x = VADDSSZrr [[COPY]], [[COPY1]]
    ; AVX512VL: %xmm0 = COPY [[VADDSSZrr]]
    ; AVX512VL: RET 0, implicit %xmm0
    %0(s32) = COPY %xmm0
    %1(s32) = COPY %xmm1
    %2(s32) = G_FADD %0, %1
    %xmm0 = COPY %2(s32)
    RET 0, implicit %xmm0

...
---
name:            test_fadd_double
alignment:       4
legalized:       true
regBankSelected: true
#
registers:
  - { id: 0, class: vecr, preferred-register: '' }
  - { id: 1, class: vecr, preferred-register: '' }
  - { id: 2, class: vecr, preferred-register: '' }
liveins:
fixedStack:
stack:
constants:
#
#
body:             |
  bb.1 (%ir-block.0):
    liveins: %xmm0, %xmm1

    ; SSE-LABEL: name: test_fadd_double
    ; SSE: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
    ; SSE: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
    ; SSE: [[ADDSDrr:%[0-9]+]]:fr64 = ADDSDrr [[COPY]], [[COPY1]]
    ; SSE: %xmm0 = COPY [[ADDSDrr]]
    ; SSE: RET 0, implicit %xmm0
    ; AVX-LABEL: name: test_fadd_double
    ; AVX: [[COPY:%[0-9]+]]:fr64 = COPY %xmm0
    ; AVX: [[COPY1:%[0-9]+]]:fr64 = COPY %xmm1
    ; AVX: [[VADDSDrr:%[0-9]+]]:fr64 = VADDSDrr [[COPY]], [[COPY1]]
    ; AVX: %xmm0 = COPY [[VADDSDrr]]
    ; AVX: RET 0, implicit %xmm0
    ; AVX512F-LABEL: name: test_fadd_double
    ; AVX512F: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
    ; AVX512F: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
    ; AVX512F: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY]], [[COPY1]]
    ; AVX512F: %xmm0 = COPY [[VADDSDZrr]]
    ; AVX512F: RET 0, implicit %xmm0
    ; AVX512VL-LABEL: name: test_fadd_double
    ; AVX512VL: [[COPY:%[0-9]+]]:fr64x = COPY %xmm0
    ; AVX512VL: [[COPY1:%[0-9]+]]:fr64x = COPY %xmm1
    ; AVX512VL: [[VADDSDZrr:%[0-9]+]]:fr64x = VADDSDZrr [[COPY]], [[COPY1]]
    ; AVX512VL: %xmm0 = COPY [[VADDSDZrr]]
    ; AVX512VL: RET 0, implicit %xmm0
    %0(s64) = COPY %xmm0
    %1(s64) = COPY %xmm1
    %2(s64) = G_FADD %0, %1
    %xmm0 = COPY %2(s64)
    RET 0, implicit %xmm0

...