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llvm-project/llvm/test/CodeGen/Hexagon/regalloc-liveout-undef.mir

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Create a PHI value when merging with a known undef live-in Differential Revision: https://reviews.llvm.org/D34640 llvm-svn: 306466
2017-06-28 05:30:46 +08:00
# RUN: llc -march=hexagon -run-pass liveintervals -run-pass machineverifier -run-pass simple-register-coalescing %s -o - | FileCheck %s
#
# If there is no consumer of the live intervals, the live intervals pass
# will be freed immediately after it runs, before the verifier. Add a
# user (register coalescer in this case), so that the verification will
# cover live intervals as well.
#
# Make sure that this compiles successfully.
MIR: Print the register class or bank in vreg defs This updates the MIRPrinter to include the regclass when printing virtual register defs, which is already valid syntax for the parser. That is, given 64 bit %0 and %1 in a "gpr" regbank, %1(s64) = COPY %0(s64) would now be written as %1:gpr(s64) = COPY %0(s64) While this change alone introduces a bit of redundancy with the registers block, it allows us to update the tests to be more concise and understandable and brings us closer to being able to remove the registers block completely. Note: We generally only print the class in defs, but there is one exception. If there are uses without any defs whatsoever, we'll print the class on all uses. I'm not completely convinced this comes up in meaningful machine IR, but for now the MIRParser and MachineVerifier both accept that kind of stuff, so we don't want to have a situation where we can print something we can't parse. llvm-svn: 316479
2017-10-25 02:04:54 +08:00
# CHECK: undef %1.isub_lo:doubleregs = A2_addi %1.isub_lo, 1
Create a PHI value when merging with a known undef live-in Differential Revision: https://reviews.llvm.org/D34640 llvm-svn: 306466
2017-06-28 05:30:46 +08:00
---
name: fred
tracksRegLiveness: true
registers:
- { id: 0, class: intregs }
- { id: 1, class: doubleregs }
- { id: 2, class: predregs }
- { id: 3, class: doubleregs }
body: |
bb.0:
liveins: %d0
successors: %bb.1
%0 = IMPLICIT_DEF
%1 = COPY %d0
bb.1:
successors: %bb.1
%2 = C2_cmpgt %0, %1.isub_lo
%3 = COPY %1
%1 = COPY %3
undef %1.isub_lo = A2_addi %1.isub_lo, 1
J2_jump %bb.1, implicit-def %pc
...