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llvm-project/llvm/test/CodeGen/AArch64/arm64-arith.ll

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[AARCH64] Enable AARCH64 lit tests on windows dev machines As discussed on PR27654, this patch fixes the triples of a lot of aarch64 tests and enables lit tests on windows This will hopefully help stop cases where windows developers break the aarch64 target Differential Revision: https://reviews.llvm.org/D22191 llvm-svn: 275973
2016-07-19 21:35:11 +08:00
; RUN: llc < %s -mtriple=arm64-eabi -asm-verbose=false | FileCheck %s
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
define i32 @t1(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t1:
; CHECK: add w0, w1, w0
; CHECK: ret
%add = add i32 %b, %a
ret i32 %add
}
define i32 @t2(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t2:
; CHECK: udiv w0, w0, w1
; CHECK: ret
%udiv = udiv i32 %a, %b
ret i32 %udiv
}
define i64 @t3(i64 %a, i64 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t3:
; CHECK: udiv x0, x0, x1
; CHECK: ret
%udiv = udiv i64 %a, %b
ret i64 %udiv
}
define i32 @t4(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t4:
; CHECK: sdiv w0, w0, w1
; CHECK: ret
%sdiv = sdiv i32 %a, %b
ret i32 %sdiv
}
define i64 @t5(i64 %a, i64 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t5:
; CHECK: sdiv x0, x0, x1
; CHECK: ret
%sdiv = sdiv i64 %a, %b
ret i64 %sdiv
}
define i32 @t6(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t6:
ARM64: print lsr instead of lsrv for variable shifts (etc) The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
2014-04-30 21:37:07 +08:00
; CHECK: lsl w0, w0, w1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%shl = shl i32 %a, %b
ret i32 %shl
}
define i64 @t7(i64 %a, i64 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t7:
ARM64: print lsr instead of lsrv for variable shifts (etc) The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
2014-04-30 21:37:07 +08:00
; CHECK: lsl x0, x0, x1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%shl = shl i64 %a, %b
ret i64 %shl
}
define i32 @t8(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t8:
ARM64: print lsr instead of lsrv for variable shifts (etc) The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
2014-04-30 21:37:07 +08:00
; CHECK: lsr w0, w0, w1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%lshr = lshr i32 %a, %b
ret i32 %lshr
}
define i64 @t9(i64 %a, i64 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t9:
ARM64: print lsr instead of lsrv for variable shifts (etc) The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
2014-04-30 21:37:07 +08:00
; CHECK: lsr x0, x0, x1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%lshr = lshr i64 %a, %b
ret i64 %lshr
}
define i32 @t10(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t10:
ARM64: print lsr instead of lsrv for variable shifts (etc) The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
2014-04-30 21:37:07 +08:00
; CHECK: asr w0, w0, w1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%ashr = ashr i32 %a, %b
ret i32 %ashr
}
define i64 @t11(i64 %a, i64 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t11:
ARM64: print lsr instead of lsrv for variable shifts (etc) The canonical syntax for shifts by a variable amount does not end with 'v', but that syntax should be supported as an alias (presumably for legacy reasons). llvm-svn: 207649
2014-04-30 21:37:07 +08:00
; CHECK: asr x0, x0, x1
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%ashr = ashr i64 %a, %b
ret i64 %ashr
}
define i32 @t12(i16 %a, i32 %x) nounwind ssp {
entry:
; CHECK-LABEL: t12:
; CHECK: add w0, w1, w0, sxth
; CHECK: ret
%c = sext i16 %a to i32
%e = add i32 %x, %c
ret i32 %e
}
define i32 @t13(i16 %a, i32 %x) nounwind ssp {
entry:
; CHECK-LABEL: t13:
; CHECK: add w0, w1, w0, sxth #2
; CHECK: ret
%c = sext i16 %a to i32
%d = shl i32 %c, 2
%e = add i32 %x, %d
ret i32 %e
}
define i64 @t14(i16 %a, i64 %x) nounwind ssp {
entry:
; CHECK-LABEL: t14:
[DAGCombiner] Attempt to mask vectors before zero extension instead of after. For cases where we TRUNCATE and then ZERO_EXTEND to a larger size (often from vector legalization), see if we can mask the source data and then ZERO_EXTEND (instead of after a ANY_EXTEND). This can help avoid having to generate a larger mask, and possibly applying it to several sub-vectors. (zext (truncate x)) -> (zext (and(x, m)) Includes a minor patch to SystemZ to better recognise 8/16-bit zero extension patterns from RISBG bit-extraction code. This is the first of a number of minor patches to help improve the conversion of byte masks to clear mask shuffles. Differential Revision: http://reviews.llvm.org/D11764 llvm-svn: 245160
2015-08-15 21:27:30 +08:00
; CHECK: and w8, w0, #0xffff
; CHECK: add x0, x1, w8, uxtw #3
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%c = zext i16 %a to i64
%d = shl i64 %c, 3
%e = add i64 %x, %d
ret i64 %e
}
; rdar://9160598
define i64 @t15(i64 %a, i64 %x) nounwind ssp {
entry:
; CHECK-LABEL: t15:
; CHECK: add x0, x1, w0, uxtw
; CHECK: ret
%b = and i64 %a, 4294967295
%c = add i64 %x, %b
ret i64 %c
}
define i64 @t16(i64 %x) nounwind ssp {
entry:
; CHECK-LABEL: t16:
; CHECK: lsl x0, x0, #1
; CHECK: ret
%a = shl i64 %x, 1
ret i64 %a
}
; rdar://9166974
define i64 @t17(i16 %a, i64 %x) nounwind ssp {
entry:
; CHECK-LABEL: t17:
ARM64: [su]xtw use W regs as inputs, not X regs. Update the SXT[BHW]/UXTW instruction aliases and the shifted reg addressing mode handling. PR19455 and rdar://16650642 llvm-svn: 206495
2014-04-18 04:47:31 +08:00
; CHECK: sxth [[REG:x[0-9]+]], w0
TableGen: fix operand counting for aliases TableGen has a fairly dubious heuristic to decide whether an alias should be printed: does the alias have lest operands than the real instruction. This is bad enough (particularly with no way to override it), but it should at least be calculated consistently for both strings. This patch implements that logic: first get the *correct* string for the variant, in the same way as the Matcher, without guessing; then count the number of whitespace chars. There are basically 4 changes this brings about after the previous commits; all of these appear to be good, so I have changed the tests: + ARM64: we print "neg X, Y" instead of "sub X, xzr, Y". + ARM64: we skip implicit "uxtx" and "uxtw" modifiers. + Sparc: we print "mov A, B" instead of "or %g0, A, B". + Sparc: we print "fcmpX A, B" instead of "fcmpX %fcc0, A, B" llvm-svn: 208969
2014-05-16 17:42:04 +08:00
; CHECK: neg x0, [[REG]], lsl #32
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; CHECK: ret
%tmp16 = sext i16 %a to i64
%tmp17 = mul i64 %tmp16, -4294967296
ret i64 %tmp17
}
define i32 @t18(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t18:
; CHECK: sdiv w0, w0, w1
; CHECK: ret
AArch64/ARM64: move ARM64 into AArch64's place This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
2014-05-24 20:50:23 +08:00
%sdiv = call i32 @llvm.aarch64.sdiv.i32(i32 %a, i32 %b)
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
ret i32 %sdiv
}
define i64 @t19(i64 %a, i64 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t19:
; CHECK: sdiv x0, x0, x1
; CHECK: ret
AArch64/ARM64: move ARM64 into AArch64's place This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
2014-05-24 20:50:23 +08:00
%sdiv = call i64 @llvm.aarch64.sdiv.i64(i64 %a, i64 %b)
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
ret i64 %sdiv
}
define i32 @t20(i32 %a, i32 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t20:
; CHECK: udiv w0, w0, w1
; CHECK: ret
AArch64/ARM64: move ARM64 into AArch64's place This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
2014-05-24 20:50:23 +08:00
%udiv = call i32 @llvm.aarch64.udiv.i32(i32 %a, i32 %b)
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
ret i32 %udiv
}
define i64 @t21(i64 %a, i64 %b) nounwind readnone ssp {
entry:
; CHECK-LABEL: t21:
; CHECK: udiv x0, x0, x1
; CHECK: ret
AArch64/ARM64: move ARM64 into AArch64's place This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
2014-05-24 20:50:23 +08:00
%udiv = call i64 @llvm.aarch64.udiv.i64(i64 %a, i64 %b)
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
ret i64 %udiv
}
AArch64/ARM64: move ARM64 into AArch64's place This commit starts with a "git mv ARM64 AArch64" and continues out from there, renaming the C++ classes, intrinsics, and other target-local objects for consistency. "ARM64" test directories are also moved, and tests that began their life in ARM64 use an arm64 triple, those from AArch64 use an aarch64 triple. Both should be equivalent though. This finishes the AArch64 merge, and everyone should feel free to continue committing as normal now. llvm-svn: 209577
2014-05-24 20:50:23 +08:00
declare i32 @llvm.aarch64.sdiv.i32(i32, i32) nounwind readnone
declare i64 @llvm.aarch64.sdiv.i64(i64, i64) nounwind readnone
declare i32 @llvm.aarch64.udiv.i32(i32, i32) nounwind readnone
declare i64 @llvm.aarch64.udiv.i64(i64, i64) nounwind readnone
ARM64: initial backend import This adds a second implementation of the AArch64 architecture to LLVM, accessible in parallel via the "arm64" triple. The plan over the coming weeks & months is to merge the two into a single backend, during which time thorough code review should naturally occur. Everything will be easier with the target in-tree though, hence this commit. llvm-svn: 205090
2014-03-29 18:18:08 +08:00
; 32-bit not.
define i32 @inv_32(i32 %x) nounwind ssp {
entry:
; CHECK: inv_32
; CHECK: mvn w0, w0
; CHECK: ret
%inv = xor i32 %x, -1
ret i32 %inv
}
; 64-bit not.
define i64 @inv_64(i64 %x) nounwind ssp {
entry:
; CHECK: inv_64
; CHECK: mvn x0, x0
; CHECK: ret
%inv = xor i64 %x, -1
ret i64 %inv
}
; Multiplying by a power of two plus or minus one is better done via shift
; and add/sub rather than the madd/msub instructions. The latter are 4+ cycles,
; and the former are two (total for the two instruction sequence for subtract).
define i32 @f0(i32 %a) nounwind readnone ssp {
; CHECK-LABEL: f0:
; CHECK-NEXT: add w0, w0, w0, lsl #3
; CHECK-NEXT: ret
%res = mul i32 %a, 9
ret i32 %res
}
define i64 @f1(i64 %a) nounwind readnone ssp {
; CHECK-LABEL: f1:
; CHECK-NEXT: lsl x8, x0, #4
; CHECK-NEXT: sub x0, x8, x0
; CHECK-NEXT: ret
%res = mul i64 %a, 15
ret i64 %res
}
define i32 @f2(i32 %a) nounwind readnone ssp {
; CHECK-LABEL: f2:
; CHECK-NEXT: lsl w8, w0, #3
; CHECK-NEXT: sub w0, w8, w0
; CHECK-NEXT: ret
%res = mul nsw i32 %a, 7
ret i32 %res
}
define i64 @f3(i64 %a) nounwind readnone ssp {
; CHECK-LABEL: f3:
; CHECK-NEXT: add x0, x0, x0, lsl #4
; CHECK-NEXT: ret
%res = mul nsw i64 %a, 17
ret i64 %res
}
[AArch64] When combining constant mul of power of 2 plus/minus 1, prefer shift plus add. The shift can be folded into the add. This only effects codegen when the constant is 3. llvm-svn: 210445
2014-06-09 09:25:51 +08:00
define i32 @f4(i32 %a) nounwind readnone ssp {
; CHECK-LABEL: f4:
; CHECK-NEXT: add w0, w0, w0, lsl #1
; CHECK-NEXT: ret
%res = mul i32 %a, 3
ret i32 %res
}