2019-10-03 05:13:07 +08:00
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//=- AArch64.td - Define AArch64 Combine Rules ---------------*- tablegen -*-=//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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include "llvm/Target/GlobalISel/Combine.td"
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2020-01-16 08:20:29 +08:00
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def fconstant_to_constant : GICombineRule<
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(defs root:$root),
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(match (wip_match_opcode G_FCONSTANT):$root,
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[{ return matchFConstantToConstant(*${root}, MRI); }]),
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(apply [{ applyFConstantToConstant(*${root}); }])>;
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2019-10-03 05:13:07 +08:00
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def AArch64PreLegalizerCombinerHelper: GICombinerHelper<
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2019-10-17 07:53:35 +08:00
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"AArch64GenPreLegalizerCombinerHelper", [all_combines,
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2020-01-16 08:20:29 +08:00
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elide_br_by_inverting_cond,
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fconstant_to_constant]> {
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2019-10-17 08:37:04 +08:00
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let DisableRuleOption = "aarch64prelegalizercombiner-disable-rule";
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}
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2020-05-22 09:05:37 +08:00
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2020-06-03 02:13:56 +08:00
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// Matchdata for combines which replace a G_SHUFFLE_VECTOR with a
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// target-specific opcode.
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def shuffle_matchdata : GIDefMatchData<"ShuffleVectorPseudo">;
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def rev : GICombineRule<
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchREV(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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2020-06-02 08:23:20 +08:00
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def zip : GICombineRule<
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2020-06-03 02:13:56 +08:00
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(defs root:$root, shuffle_matchdata:$matchinfo),
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2020-06-02 08:23:20 +08:00
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchZip(*${root}, MRI, ${matchinfo}); }]),
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2020-06-03 00:30:04 +08:00
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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2020-06-02 08:23:20 +08:00
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>;
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2020-06-03 00:30:04 +08:00
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def uzp : GICombineRule<
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2020-06-03 02:13:56 +08:00
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(defs root:$root, shuffle_matchdata:$matchinfo),
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2020-06-03 00:30:04 +08:00
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchUZP(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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[AArch64][GlobalISel] Move dup optimization into post-legalizer combiner
Since all of the other G_SHUFFLE_VECTOR transforms are going there, let's do
this with dup as well. This is nice, because it lets us split up the original
code into matching, register bank selection, and instruction selection.
- Create G_DUP, make it equivalent to AArch64dup
- Add a post-legalizer combine which is 90% a copy-and-paste from
tryOptVectorDup, except with shuffle matching closer to what SelectionDAG
does in `ShuffleVectorSDNode::isSplatMask`.
- Teach RegBankSelect about G_DUP. Since dup selection relies on the correct
register bank for FP/GPR dup selection, this is necessary.
- Kill `tryOptVectorDup`, since it's now entirely handled by G_DUP.
- Add testcases for the combine, RegBankSelect, and selection. The selection
test gives the same selection results as the old test.
Differential Revision: https://reviews.llvm.org/D81221
2020-06-05 08:08:36 +08:00
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def dup: GICombineRule <
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(defs root:$root, shuffle_matchdata:$matchinfo),
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(match (wip_match_opcode G_SHUFFLE_VECTOR):$root,
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[{ return matchDup(*${root}, MRI, ${matchinfo}); }]),
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(apply [{ applyShuffleVectorPseudo(*${root}, ${matchinfo}); }])
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>;
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2020-06-03 00:30:04 +08:00
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// Combines which replace a G_SHUFFLE_VECTOR with a target-specific pseudo
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// instruction.
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[AArch64][GlobalISel] Move dup optimization into post-legalizer combiner
Since all of the other G_SHUFFLE_VECTOR transforms are going there, let's do
this with dup as well. This is nice, because it lets us split up the original
code into matching, register bank selection, and instruction selection.
- Create G_DUP, make it equivalent to AArch64dup
- Add a post-legalizer combine which is 90% a copy-and-paste from
tryOptVectorDup, except with shuffle matching closer to what SelectionDAG
does in `ShuffleVectorSDNode::isSplatMask`.
- Teach RegBankSelect about G_DUP. Since dup selection relies on the correct
register bank for FP/GPR dup selection, this is necessary.
- Kill `tryOptVectorDup`, since it's now entirely handled by G_DUP.
- Add testcases for the combine, RegBankSelect, and selection. The selection
test gives the same selection results as the old test.
Differential Revision: https://reviews.llvm.org/D81221
2020-06-05 08:08:36 +08:00
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def shuffle_vector_pseudos : GICombineGroup<[dup, rev, zip, uzp]>;
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2020-06-03 00:30:04 +08:00
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2020-05-23 05:21:50 +08:00
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def AArch64PostLegalizerCombinerHelper
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: GICombinerHelper<"AArch64GenPostLegalizerCombinerHelper",
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2020-06-03 00:30:04 +08:00
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[erase_undef_store, combines_for_extload,
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shuffle_vector_pseudos]> {
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2020-05-22 09:05:37 +08:00
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let DisableRuleOption = "aarch64postlegalizercombiner-disable-rule";
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}
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