llvm-project/llvm/test/CodeGen/AArch64/GlobalISel/legalize-or.mir

# RUN: llc -O0 -run-pass=legalize-mir -global-isel %s -o - 2>&1 | FileCheck %s

--- |
  target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
  target triple = "aarch64--"
  define void @test_scalar_or_small() {
  entry:
    ret void
  }
...

---
name:            test_scalar_or_small
registers:
  - { id: 0, class: _ }
  - { id: 1, class: _ }
  - { id: 2, class: _ }
  - { id: 3, class: _ }
  - { id: 4, class: _ }
  - { id: 5, class: _ }
body: |
  bb.0.entry:
    liveins: %x0, %x1, %x2, %x3
    ; CHECK-LABEL: name: test_scalar_or_small
    ; CHECK: %4(s8) = G_OR %2, %3

    %0(s64) = COPY %x0
    %1(s64) = COPY %x1
    %2(s8) = G_TRUNC %0
    %3(s8) = G_TRUNC %1
    %4(s8) = G_OR %2, %3
    %5(s64) = G_ANYEXT %2
    %x0 = COPY %5
...