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llvm-project/llvm/test/MC/AArch64/neon-tbl.s

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AArch64/ARM64: run AArch64 NEON MC tests through ARM64 too. This skips a couple of compare ones due to the different syntaxt for floating-point 0.0. AArch64 does it more canonically, and we'll need to fiddle ARM64 to make it work. llvm-svn: 207119
2014-04-24 23:04:20 +08:00
// RUN: llvm-mc -triple=arm64 -mattr=+neon -show-encoding < %s | FileCheck %s
Implement AArch64 NEON instruction set AdvSIMD (table). llvm-svn: 194648
2013-11-14 09:57:32 +08:00
// Check that the assembler can handle the documented syntax for AArch64
//------------------------------------------------------------------------------
// Instructions across vector registers
//------------------------------------------------------------------------------
AArch64: print NEON lists with a space. This matches ARM64 behaviour, which I think is clearer. It also puts all the churn from that difference into one easily ignored commit. llvm-svn: 207116
2014-04-24 22:06:20 +08:00
tbl v0.8b, { v1.16b }, v2.8b
tbl v0.8b, { v1.16b, v2.16b }, v2.8b
tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
// CHECK: tbl v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x00,0x02,0x0e]
// CHECK: tbl v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x20,0x02,0x0e]
// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x40,0x02,0x0e]
// CHECK: tbl v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x60,0x02,0x0e]
// CHECK: tbl v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x63,0x02,0x0e]
tbl v0.16b, { v1.16b }, v2.16b
tbl v0.16b, { v1.16b, v2.16b }, v2.16b
tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b
tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b
// CHECK: tbl v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x00,0x02,0x4e]
// CHECK: tbl v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x20,0x02,0x4e]
// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x40,0x02,0x4e]
// CHECK: tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x60,0x02,0x4e]
// CHECK: tbl v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x63,0x02,0x4e]
tbx v0.8b, { v1.16b }, v2.8b
tbx v0.8b, { v1.16b, v2.16b }, v2.8b
tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b
tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b
tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b
// CHECK: tbx v0.8b, { v1.16b }, v2.8b // encoding: [0x20,0x10,0x02,0x0e]
// CHECK: tbx v0.8b, { v1.16b, v2.16b }, v2.8b // encoding: [0x20,0x30,0x02,0x0e]
// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b }, v2.8b // encoding: [0x20,0x50,0x02,0x0e]
// CHECK: tbx v0.8b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.8b // encoding: [0x20,0x70,0x02,0x0e]
// CHECK: tbx v0.8b, { v31.16b, v0.16b, v1.16b, v2.16b }, v2.8b // encoding: [0xe0,0x73,0x02,0x0e]
tbx v0.16b, { v1.16b }, v2.16b
tbx v0.16b, { v1.16b, v2.16b }, v2.16b
tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b
tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b
tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b
// CHECK: tbx v0.16b, { v1.16b }, v2.16b // encoding: [0x20,0x10,0x02,0x4e]
// CHECK: tbx v0.16b, { v1.16b, v2.16b }, v2.16b // encoding: [0x20,0x30,0x02,0x4e]
// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b }, v2.16b // encoding: [0x20,0x50,0x02,0x4e]
// CHECK: tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v2.16b // encoding: [0x20,0x70,0x02,0x4e]
// CHECK: tbx v0.16b, { v30.16b, v31.16b, v0.16b, v1.16b }, v2.16b // encoding: [0xc0,0x73,0x02,0x4e]