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llvm-project/llvm/test/CodeGen/X86/testl-commute.ll

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FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
; RUN: llc < %s | FileCheck %s
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
; rdar://5671654
; The loads should fold into the testl instructions, no matter how
; the inputs are commuted.
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128"
target triple = "x86_64-apple-darwin7"
define i32 @test(i32* %P, i32* %G) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test:
FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
; CHECK-NOT: ret
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
2017-10-02 07:53:53 +08:00
; CHECK: testl %{{.*}}, (%{{.*}})
FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
; CHECK: ret
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* %P, align 4 ; <i32> [#uses=3]
%1 = load i32, i32* %G, align 4 ; <i32> [#uses=1]
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
%2 = and i32 %1, %0 ; <i32> [#uses=1]
%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
br i1 %3, label %bb1, label %bb
bb: ; preds = %entry
%4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
ret i32 %0
bb1: ; preds = %entry
ret i32 %0
}
define i32 @test2(i32* %P, i32* %G) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test2:
FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
; CHECK-NOT: ret
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
2017-10-02 07:53:53 +08:00
; CHECK: testl %{{.*}}, (%{{.*}})
FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
; CHECK: ret
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* %P, align 4 ; <i32> [#uses=3]
%1 = load i32, i32* %G, align 4 ; <i32> [#uses=1]
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
%2 = and i32 %0, %1 ; <i32> [#uses=1]
%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
br i1 %3, label %bb1, label %bb
bb: ; preds = %entry
%4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
ret i32 %0
bb1: ; preds = %entry
ret i32 %0
}
FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
define i32 @test3(i32* %P, i32* %G) nounwind {
Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion. This was done with the following sed invocation to catch label lines demarking function boundaries: sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct. llvm-svn: 186258
2013-07-14 04:38:47 +08:00
; CHECK-LABEL: test3:
FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
; CHECK-NOT: ret
[X86] Change register&memory TEST instructions from MRMSrcMem to MRMDstMem Summary: Intel documentation shows the memory operand as the first operand. But we currently treat it as the second operand. Conceptually the order doesn't matter since it doesn't write memory. We have aliases to parse with the operands in either order and the isel matching is commutable. For the register&register form order does matter for the assembly parser. PR22995 was previously filed and fixed by changing the register&register form from MRMSrcReg to MRMDestReg to match gas. Ideally the memory form should match by using MRMDestMem. I believe this supercedes D38025 which was trying to switch the register&register form back to pre-PR22995. Reviewers: aymanmus, RKSimon, zvi Reviewed By: aymanmus Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D38120 llvm-svn: 314639
2017-10-02 07:53:53 +08:00
; CHECK: testl %{{.*}}, (%{{.*}})
FileCheck-ize another test, making it much more precise for testing the individual cases, while hard coding less about registers in use. llvm-svn: 134330
2011-07-03 04:42:11 +08:00
; CHECK: ret
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
entry:
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%0 = load i32, i32* %P, align 4 ; <i32> [#uses=3]
%1 = load i32, i32* %G, align 4 ; <i32> [#uses=1]
add a testcase. llvm-svn: 61845
2009-01-07 09:48:08 +08:00
%2 = and i32 %0, %1 ; <i32> [#uses=1]
%3 = icmp eq i32 %2, 0 ; <i1> [#uses=1]
br i1 %3, label %bb1, label %bb
bb: ; preds = %entry
%4 = tail call i32 @bar() nounwind ; <i32> [#uses=0]
ret i32 %1
bb1: ; preds = %entry
ret i32 %1
}
declare i32 @bar()