2017-02-24 11:04:11 +08:00
|
|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
|
|
|
; RUN: llc < %s -mtriple=arm-eabi | FileCheck %s -check-prefix=LE
|
|
|
|
; RUN: llc < %s -mtriple=armeb-eabi | FileCheck %s -check-prefix=BE
|
|
|
|
|
|
|
|
define void @i24_or(i24* %a) {
|
|
|
|
; LE-LABEL: i24_or:
|
|
|
|
; LE: @ BB#0:
|
|
|
|
; LE-NEXT: ldrh r1, [r0]
|
|
|
|
; LE-NEXT: orr r1, r1, #384
|
|
|
|
; LE-NEXT: strh r1, [r0]
|
|
|
|
; LE-NEXT: mov pc, lr
|
|
|
|
;
|
|
|
|
; BE-LABEL: i24_or:
|
|
|
|
; BE: @ BB#0:
|
|
|
|
; BE-NEXT: ldrh r1, [r0]
|
|
|
|
; BE-NEXT: ldrb r2, [r0, #2]
|
|
|
|
; BE-NEXT: orr r1, r2, r1, lsl #8
|
|
|
|
; BE-NEXT: orr r1, r1, #384
|
|
|
|
; BE-NEXT: strb r1, [r0, #2]
|
|
|
|
; BE-NEXT: lsr r1, r1, #8
|
|
|
|
; BE-NEXT: strh r1, [r0]
|
|
|
|
; BE-NEXT: mov pc, lr
|
|
|
|
%aa = load i24, i24* %a, align 1
|
|
|
|
%b = or i24 %aa, 384
|
|
|
|
store i24 %b, i24* %a, align 1
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @i24_and_or(i24* %a) {
|
|
|
|
; LE-LABEL: i24_and_or:
|
|
|
|
; LE: @ BB#0:
|
2017-03-08 08:56:35 +08:00
|
|
|
; LE-NEXT: ldrh r1, [r0]
|
|
|
|
; LE-NEXT: mov r2, #16256
|
|
|
|
; LE-NEXT: orr r2, r2, #49152
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; LE-NEXT: orr r1, r1, #384
|
2017-02-24 11:04:11 +08:00
|
|
|
; LE-NEXT: and r1, r1, r2
|
|
|
|
; LE-NEXT: strh r1, [r0]
|
|
|
|
; LE-NEXT: mov pc, lr
|
|
|
|
;
|
|
|
|
; BE-LABEL: i24_and_or:
|
|
|
|
; BE: @ BB#0:
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; BE-NEXT: mov r1, #128
|
|
|
|
; BE-NEXT: strb r1, [r0, #2]
|
2017-02-24 11:04:11 +08:00
|
|
|
; BE-NEXT: ldrh r1, [r0]
|
2017-03-08 08:56:35 +08:00
|
|
|
; BE-NEXT: orr r1, r1, #1
|
2017-02-24 11:04:11 +08:00
|
|
|
; BE-NEXT: strh r1, [r0]
|
|
|
|
; BE-NEXT: mov pc, lr
|
|
|
|
%b = load i24, i24* %a, align 1
|
|
|
|
%c = and i24 %b, -128
|
|
|
|
%d = or i24 %c, 384
|
|
|
|
store i24 %d, i24* %a, align 1
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @i24_insert_bit(i24* %a, i1 zeroext %bit) {
|
|
|
|
; LE-LABEL: i24_insert_bit:
|
|
|
|
; LE: @ BB#0:
|
2017-03-08 08:56:35 +08:00
|
|
|
; LE-NEXT: mov r3, #255
|
2017-06-28 15:07:03 +08:00
|
|
|
; LE-NEXT: ldrh r2, [r0]
|
2017-03-08 08:56:35 +08:00
|
|
|
; LE-NEXT: orr r3, r3, #57088
|
2017-02-24 11:04:11 +08:00
|
|
|
; LE-NEXT: and r2, r2, r3
|
|
|
|
; LE-NEXT: orr r1, r2, r1, lsl #13
|
|
|
|
; LE-NEXT: strh r1, [r0]
|
|
|
|
; LE-NEXT: mov pc, lr
|
|
|
|
;
|
|
|
|
; BE-LABEL: i24_insert_bit:
|
|
|
|
; BE: @ BB#0:
|
2017-03-08 08:56:35 +08:00
|
|
|
; BE-NEXT: ldrh r2, [r0]
|
|
|
|
; BE-NEXT: mov r3, #57088
|
|
|
|
; BE-NEXT: orr r3, r3, #16711680
|
|
|
|
; BE-NEXT: and r2, r3, r2, lsl #8
|
2017-02-24 11:04:11 +08:00
|
|
|
; BE-NEXT: orr r1, r2, r1, lsl #13
|
|
|
|
; BE-NEXT: lsr r1, r1, #8
|
|
|
|
; BE-NEXT: strh r1, [r0]
|
|
|
|
; BE-NEXT: mov pc, lr
|
|
|
|
%extbit = zext i1 %bit to i24
|
|
|
|
%b = load i24, i24* %a, align 1
|
|
|
|
%extbit.shl = shl nuw nsw i24 %extbit, 13
|
|
|
|
%c = and i24 %b, -8193
|
|
|
|
%d = or i24 %c, %extbit.shl
|
|
|
|
store i24 %d, i24* %a, align 1
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @i56_or(i56* %a) {
|
|
|
|
; LE-LABEL: i56_or:
|
|
|
|
; LE: @ BB#0:
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; LE-NEXT: ldr r1, [r0]
|
|
|
|
; LE-NEXT: orr r1, r1, #384
|
2017-02-24 11:04:11 +08:00
|
|
|
; LE-NEXT: str r1, [r0]
|
|
|
|
; LE-NEXT: mov pc, lr
|
|
|
|
;
|
|
|
|
; BE-LABEL: i56_or:
|
|
|
|
; BE: @ BB#0:
|
|
|
|
; BE-NEXT: mov r1, r0
|
|
|
|
; BE-NEXT: ldr r12, [r0]
|
|
|
|
; BE-NEXT: ldrh r2, [r1, #4]!
|
|
|
|
; BE-NEXT: ldrb r3, [r1, #2]
|
|
|
|
; BE-NEXT: orr r2, r3, r2, lsl #8
|
|
|
|
; BE-NEXT: orr r2, r2, r12, lsl #24
|
|
|
|
; BE-NEXT: orr r2, r2, #384
|
|
|
|
; BE-NEXT: strb r2, [r1, #2]
|
2017-06-28 15:07:03 +08:00
|
|
|
; BE-NEXT: lsr r3, r2, #8
|
2017-02-24 11:04:11 +08:00
|
|
|
; BE-NEXT: strh r3, [r1]
|
|
|
|
; BE-NEXT: bic r1, r12, #255
|
|
|
|
; BE-NEXT: orr r1, r1, r2, lsr #24
|
|
|
|
; BE-NEXT: str r1, [r0]
|
|
|
|
; BE-NEXT: mov pc, lr
|
|
|
|
%aa = load i56, i56* %a
|
|
|
|
%b = or i56 %aa, 384
|
|
|
|
store i56 %b, i56* %a
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @i56_and_or(i56* %a) {
|
|
|
|
; LE-LABEL: i56_and_or:
|
|
|
|
; LE: @ BB#0:
|
|
|
|
; LE-NEXT: ldr r1, [r0]
|
|
|
|
; LE-NEXT: orr r1, r1, #384
|
|
|
|
; LE-NEXT: bic r1, r1, #127
|
|
|
|
; LE-NEXT: str r1, [r0]
|
|
|
|
; LE-NEXT: mov pc, lr
|
|
|
|
;
|
|
|
|
; BE-LABEL: i56_and_or:
|
|
|
|
; BE: @ BB#0:
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; BE-NEXT: mov r1, r0
|
2017-08-30 22:57:12 +08:00
|
|
|
; BE-NEXT: ldr r12, [r0]
|
2017-08-16 22:17:43 +08:00
|
|
|
; BE-NEXT: ldrh r2, [r1, #4]!
|
2017-08-30 22:57:12 +08:00
|
|
|
; BE-NEXT: mov r3, #128
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; BE-NEXT: strb r3, [r1, #2]
|
2017-06-28 15:07:03 +08:00
|
|
|
; BE-NEXT: lsl r2, r2, #8
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; BE-NEXT: orr r2, r2, r12, lsl #24
|
|
|
|
; BE-NEXT: orr r2, r2, #384
|
|
|
|
; BE-NEXT: lsr r3, r2, #8
|
|
|
|
; BE-NEXT: strh r3, [r1]
|
|
|
|
; BE-NEXT: bic r1, r12, #255
|
|
|
|
; BE-NEXT: orr r1, r1, r2, lsr #24
|
2017-02-24 11:04:11 +08:00
|
|
|
; BE-NEXT: str r1, [r0]
|
|
|
|
; BE-NEXT: mov pc, lr
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
|
2017-02-24 11:04:11 +08:00
|
|
|
%b = load i56, i56* %a, align 1
|
|
|
|
%c = and i56 %b, -128
|
|
|
|
%d = or i56 %c, 384
|
|
|
|
store i56 %d, i56* %a, align 1
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|
|
|
|
define void @i56_insert_bit(i56* %a, i1 zeroext %bit) {
|
|
|
|
; LE-LABEL: i56_insert_bit:
|
|
|
|
; LE: @ BB#0:
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; LE-NEXT: ldr r2, [r0]
|
|
|
|
; LE-NEXT: bic r2, r2, #8192
|
2017-02-24 11:04:11 +08:00
|
|
|
; LE-NEXT: orr r1, r2, r1, lsl #13
|
|
|
|
; LE-NEXT: str r1, [r0]
|
|
|
|
; LE-NEXT: mov pc, lr
|
|
|
|
;
|
|
|
|
; BE-LABEL: i56_insert_bit:
|
|
|
|
; BE: @ BB#0:
|
|
|
|
; BE-NEXT: .save {r11, lr}
|
|
|
|
; BE-NEXT: push {r11, lr}
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; BE-NEXT: mov r2, r0
|
2017-03-18 06:15:50 +08:00
|
|
|
; BE-NEXT: ldr lr, [r0]
|
In visitSTORE, always use FindBetterChain, rather than only when UseAA is enabled.
Recommiting with compiler time improvements
Recommitting after fixup of 32-bit aliasing sign offset bug in DAGCombiner.
* Simplify Consecutive Merge Store Candidate Search
Now that address aliasing is much less conservative, push through
simplified store merging search and chain alias analysis which only
checks for parallel stores through the chain subgraph. This is cleaner
as the separation of non-interfering loads/stores from the
store-merging logic.
When merging stores search up the chain through a single load, and
finds all possible stores by looking down from through a load and a
TokenFactor to all stores visited.
This improves the quality of the output SelectionDAG and the output
Codegen (save perhaps for some ARM cases where we correctly constructs
wider loads, but then promotes them to float operations which appear
but requires more expensive constant generation).
Some minor peephole optimizations to deal with improved SubDAG shapes (listed below)
Additional Minor Changes:
1. Finishes removing unused AliasLoad code
2. Unifies the chain aggregation in the merged stores across code
paths
3. Re-add the Store node to the worklist after calling
SimplifyDemandedBits.
4. Increase GatherAllAliasesMaxDepth from 6 to 18. That number is
arbitrary, but seems sufficient to not cause regressions in
tests.
5. Remove Chain dependencies of Memory operations on CopyfromReg
nodes as these are captured by data dependence
6. Forward loads-store values through tokenfactors containing
{CopyToReg,CopyFromReg} Values.
7. Peephole to convert buildvector of extract_vector_elt to
extract_subvector if possible (see
CodeGen/AArch64/store-merge.ll)
8. Store merging for the ARM target is restricted to 32-bit as
some in some contexts invalid 64-bit operations are being
generated. This can be removed once appropriate checks are
added.
This finishes the change Matt Arsenault started in r246307 and
jyknight's original patch.
Many tests required some changes as memory operations are now
reorderable, improving load-store forwarding. One test in
particular is worth noting:
CodeGen/PowerPC/ppc64-align-long-double.ll - Improved load-store
forwarding converts a load-store pair into a parallel store and
a memory-realized bitcast of the same value. However, because we
lose the sharing of the explicit and implicit store values we
must create another local store. A similar transformation
happens before SelectionDAG as well.
Reviewers: arsenm, hfinkel, tstellarAMD, jyknight, nhaehnle
llvm-svn: 297695
2017-03-14 08:34:14 +08:00
|
|
|
; BE-NEXT: ldrh r12, [r2, #4]!
|
|
|
|
; BE-NEXT: ldrb r3, [r2, #2]
|
|
|
|
; BE-NEXT: orr r12, r3, r12, lsl #8
|
|
|
|
; BE-NEXT: orr r3, r12, lr, lsl #24
|
|
|
|
; BE-NEXT: bic r3, r3, #8192
|
|
|
|
; BE-NEXT: orr r1, r3, r1, lsl #13
|
|
|
|
; BE-NEXT: lsr r3, r1, #8
|
|
|
|
; BE-NEXT: strh r3, [r2]
|
2017-02-24 11:04:11 +08:00
|
|
|
; BE-NEXT: bic r2, lr, #255
|
|
|
|
; BE-NEXT: orr r1, r2, r1, lsr #24
|
|
|
|
; BE-NEXT: str r1, [r0]
|
|
|
|
; BE-NEXT: pop {r11, lr}
|
|
|
|
; BE-NEXT: mov pc, lr
|
|
|
|
%extbit = zext i1 %bit to i56
|
|
|
|
%b = load i56, i56* %a, align 1
|
|
|
|
%extbit.shl = shl nuw nsw i56 %extbit, 13
|
|
|
|
%c = and i56 %b, -8193
|
|
|
|
%d = or i56 %c, %extbit.shl
|
|
|
|
store i56 %d, i56* %a, align 1
|
|
|
|
ret void
|
|
|
|
}
|
|
|
|
|