maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/ARM/fullfp16-nopred.s

114 lines
3.4 KiB
ArmAsm
Raw Normal View History

[ARM] Make fullfp16 instructions not conditionalisable. More or less all the instructions defined in the v8.2a full-fp16 extension are defined as UNPREDICTABLE if you put them in an IT block (Thumb) or use with any condition other than AL (ARM). LLVM didn't know that, and was happy to conditionalise them. In order to force these instructions to count as not predicable, I had to make a small Tablegen change. The code generation back end mostly decides if an instruction was predicable by looking for something it can identify as a predicate operand; there's an isPredicable bit flag that overrides that check in the positive direction, but nothing that overrides it in the negative direction. (I considered the alternative approach of actually removing the predicate operand from those instructions, but thought that it would be more painful overall for instructions differing only in data type to have different shapes of operand list. This way, the only code that has to notice the difference is the if-converter.) So I've added an isUnpredicable bit alongside isPredicable, and set that bit on the right subset of FP16 instructions, and also on the VSEL, VMAXNM/VMINNM and VRINT[ANPM] families which should be unpredicable for all data types. I've included a couple of representative regression tests, both of which previously caused an fp16 instruction to be conditionalised in ARM state and (with -arm-no-restrict-it) to be put in an IT block in Thumb. Reviewers: SjoerdMeijer, t.p.northover, efriedma Reviewed By: efriedma Subscribers: jdoerfert, javed.absar, kristof.beyls, hiraditya, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D57823 llvm-svn: 354768
2019-02-25 18:39:53 +08:00
@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16 < %s 2>&1 | FileCheck %s
@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,+thumb-mode -arm-implicit-it always < %s 2>&1 | FileCheck %s
vaddeq.f16 s0, s1, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vsubne.f16 s0, s1, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vdivmi.f16 s0, s1, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vmulpl.f16 s0, s1, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vnmulvs.f16 s0, s1, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vmlavc.f16 s1, s2, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vmlshs.f16 s1, s2, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vnmlalo.f16 s1, s2, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vnmlscs.f16 s1, s2, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vcmpcc.f16 s0, s1
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vcmphi.f16 s2, #0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vcmpels.f16 s1, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vcmpege.f16 s0, #0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vabslt.f16 s0, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vneggt.f16 s0, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vsqrtle.f16 s0, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vcvteq.f16.s32 s0, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vcvtne.u32.f16 s0, s0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vcvtrmi.s32.f16 s0, s1
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vrintzhs.f16 s3, s24
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vrintrlo.f16 s0, s9
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vrintxcs.f16 s10, s14
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vfmalt.f16 s2, s7, s4
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vfmsgt.f16 s2, s7, s4
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vfnmale.f16 s2, s7, s4
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vfnmseq.f16 s2, s7, s4
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vldrpl.16 s1, [pc, #6]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vldrvs.16 s2, [pc, #510]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vldrvc.16 s3, [pc, #-510]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vldrhs.16 s4, [r4, #-18]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vstrlo.16 s1, [pc, #6]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vstrcs.16 s2, [pc, #510]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vstrcc.16 s3, [pc, #-510]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vstrhi.16 s4, [r4, #-18]
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vmovls.f16 s0, #1.0
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vmovge.f16 s1, r2
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable
vmovlt.f16 r3, s4
@ CHECK: [[@LINE-1]]:3: error: instruction is not predicable