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llvm-project/llvm/test/CodeGen/X86/mmx-punpckhdq.ll

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Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else. llvm-svn: 115352
2010-10-02 05:39:35 +08:00
; RUN: llc < %s -march=x86 -mattr=+mmx,+sse42 -mtriple=x86_64-apple-darwin10 | FileCheck %s
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 07:57:10 +08:00
; There are no MMX operations in bork; promoted to XMM.
Testcases for MMX. llvm-svn: 36408
2007-04-25 06:28:30 +08:00
define void @bork(<1 x i64>* %x) {
We must check for something. llvm-svn: 115309
2010-10-01 18:20:10 +08:00
; CHECK: bork
Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else. llvm-svn: 115352
2010-10-02 05:39:35 +08:00
; CHECK: pextrd
Testcases for MMX. llvm-svn: 36408
2007-04-25 06:28:30 +08:00
entry:
%tmp2 = load <1 x i64>* %x ; <<1 x i64>> [#uses=1]
%tmp6 = bitcast <1 x i64> %tmp2 to <2 x i32> ; <<2 x i32>> [#uses=1]
%tmp9 = shufflevector <2 x i32> %tmp6, <2 x i32> undef, <2 x i32> < i32 1, i32 1 > ; <<2 x i32>> [#uses=1]
%tmp10 = bitcast <2 x i32> %tmp9 to <1 x i64> ; <<1 x i64>> [#uses=1]
store <1 x i64> %tmp10, <1 x i64>* %x
tail call void @llvm.x86.mmx.emms( )
ret void
}
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 07:57:10 +08:00
; pork uses MMX.
define void @pork(x86_mmx* %x) {
We must check for something. llvm-svn: 115309
2010-10-01 18:20:10 +08:00
; CHECK: pork
Need to specify SSE4 for machines which don't have SSE4. The code checked for is generated by SSE4. Otherwise, we get something else. llvm-svn: 115352
2010-10-02 05:39:35 +08:00
; CHECK: punpckhdq
Massive rewrite of MMX: The x86_mmx type is used for MMX intrinsics, parameters and return values where these use MMX registers, and is also supported in load, store, and bitcast. Only the above operations generate MMX instructions, and optimizations do not operate on or produce MMX intrinsics. MMX-sized vectors <2 x i32> etc. are lowered to XMM or split into smaller pieces. Optimizations may occur on these forms and the result casted back to x86_mmx, provided the result feeds into a previous existing x86_mmx operation. The point of all this is prevent optimizations from introducing MMX operations, which is unsafe due to the EMMS problem. llvm-svn: 115243
2010-10-01 07:57:10 +08:00
entry:
%tmp2 = load x86_mmx* %x ; <x86_mmx> [#uses=1]
%tmp9 = tail call x86_mmx @llvm.x86.mmx.punpckhdq (x86_mmx %tmp2, x86_mmx %tmp2)
store x86_mmx %tmp9, x86_mmx* %x
tail call void @llvm.x86.mmx.emms( )
ret void
}
declare x86_mmx @llvm.x86.mmx.punpckhdq(x86_mmx, x86_mmx)
Testcases for MMX. llvm-svn: 36408
2007-04-25 06:28:30 +08:00
declare void @llvm.x86.mmx.emms()