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llvm-project/llvm/test/CodeGen/ARM/peephole-bitcast.ll

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ARM: Do not use llc -march in tests. `llc -march` is problematic because it only switches the target architecture, but leaves the operating system unchanged. This occasionally leads to indeterministic tests because the OS from LLVM_DEFAULT_TARGET_TRIPLE is used. However we can simply always use `llc -mtriple` instead. This changes all the tests to do this to avoid people using -march when they copy and paste parts of tests. See also the discussion in https://reviews.llvm.org/D35287 llvm-svn: 309755
2017-08-02 06:20:49 +08:00
; RUN: llc < %s -mtriple=arm-- -mcpu=cortex-a8 | FileCheck %s
XFAIL test that depends on linear scan to remove dead code. Filed PR11364 to track the problem. Should the register allocator eliminate dead code? llvm-svn: 144471
2011-11-13 06:39:30 +08:00
; XFAIL: *
; PR11364
Add a peephole optimization to optimize pairs of bitcasts. e.g. v2 = bitcast v1 ... v3 = bitcast v2 ... = v3 => v2 = bitcast v1 ... = v1 if v1 and v3 are of in the same register class. bitcast between i32 and fp (and others) are often not nops since they are in different register classes. These bitcast instructions are often left because they are in different basic blocks and cannot be eliminated by dag combine. rdar://9104514 llvm-svn: 127668
2011-03-15 13:13:13 +08:00
; vmov s0, r0 + vmov r0, s0 should have been optimized away.
; rdar://9104514
Fix ARM tests to be register allocator independent. llvm-svn: 128680
2011-04-01 06:14:03 +08:00
; Peephole leaves a dead vmovsr instruction behind, and depends on linear scan
; to remove it.
Add a peephole optimization to optimize pairs of bitcasts. e.g. v2 = bitcast v1 ... v3 = bitcast v2 ... = v3 => v2 = bitcast v1 ... = v1 if v1 and v3 are of in the same register class. bitcast between i32 and fp (and others) are often not nops since they are in different register classes. These bitcast instructions are often left because they are in different basic blocks and cannot be eliminated by dag combine. rdar://9104514 llvm-svn: 127668
2011-03-15 13:13:13 +08:00
define void @t(float %x) nounwind ssp {
entry:
Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally. This update was done with the following bash script: find test/CodeGen -name "*.ll" | \ while read NAME; do echo "$NAME" if ! grep -q "^; *RUN: *llc.*debug" $NAME; then TEMP=`mktemp -t temp` cp $NAME $TEMP sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \ while read FUNC; do sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP done sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP mv $TEMP $NAME fi done llvm-svn: 186280
2013-07-14 14:24:09 +08:00
; CHECK-LABEL: t:
Add a peephole optimization to optimize pairs of bitcasts. e.g. v2 = bitcast v1 ... v3 = bitcast v2 ... = v3 => v2 = bitcast v1 ... = v1 if v1 and v3 are of in the same register class. bitcast between i32 and fp (and others) are often not nops since they are in different register classes. These bitcast instructions are often left because they are in different basic blocks and cannot be eliminated by dag combine. rdar://9104514 llvm-svn: 127668
2011-03-15 13:13:13 +08:00
; CHECK-NOT: vmov
; CHECK: bl
%0 = bitcast float %x to i32
%cmp = icmp ult i32 %0, 2139095039
br i1 %cmp, label %if.then, label %if.end
if.then: ; preds = %entry
tail call void @doSomething(float %x) nounwind
br label %if.end
if.end: ; preds = %if.then, %entry
ret void
}
declare void @doSomething(float)