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llvm-project/llvm/test/CodeGen/ARM/fp16-insert-extract.ll

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[ARM] Add FP16 vector insert/extract patterns This change adds two FP16 extraction and two insertion patterns (one per possible vector length). Extractions are handled by copying a Q/D register into one of VFP2 class registers, where single FP32 sub-registers can be accessed. Then the extraction of even lanes are simple sub-register extractions (because we don't care about the top parts of registers for FP16 operations). Odd lanes need an additional VMOVX instruction. Unfortunately, insertions cannot be handled in the same way, because: * There is no instruction to insert FP16 into an even lane (VINS only works with odd lanes) * The patterns for odd lanes will have a form of a DAG (not a tree), and will not be implementable in pure tablegen Because of this insertions are handled in the same way as 16-bit integer insertions (with conversions between FP registers and GPRs using VMOVHR instructions). Without these patterns the ARM backend would sometimes fail during instruction selection. This patch also adds patterns which combine: * an FP16 element extraction and a store into a single VST1 instruction * an FP16 load and insertion into a single VLD1 instruction Differential Revision: https://reviews.llvm.org/D62651 llvm-svn: 362482
2019-06-04 17:39:55 +08:00
; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=hard -O1 < %s | FileCheck %s
; RUN: llc -mtriple=arm-eabi -mattr=+armv8.2-a,+fullfp16,+neon -float-abi=soft -O1 < %s | FileCheck %s
define float @test_vget_lane_f16_1(<4 x half> %a) nounwind {
; CHECK-LABEL: test_vget_lane_f16_1:
; CHECK: vmovx.f16 s0, s0
; CHECK-NEXT: vcvtb.f32.f16 s0, s0
entry:
%elt = extractelement <4 x half> %a, i32 1
%conv = fpext half %elt to float
ret float %conv
}
define float @test_vget_lane_f16_2(<4 x half> %a) nounwind {
; CHECK-LABEL: test_vget_lane_f16_2:
; CHECK-NOT: vmovx.f16
; CHECK: vcvtb.f32.f16 s0, s1
entry:
%elt = extractelement <4 x half> %a, i32 2
%conv = fpext half %elt to float
ret float %conv
}
define float @test_vget_laneq_f16_6(<8 x half> %a) nounwind {
; CHECK-LABEL: test_vget_laneq_f16_6:
; CHECK-NOT: vmovx.f16
; CHECK: vcvtb.f32.f16 s0, s3
entry:
%elt = extractelement <8 x half> %a, i32 6
%conv = fpext half %elt to float
ret float %conv
}
define float @test_vget_laneq_f16_7(<8 x half> %a) nounwind {
; CHECK-LABEL: test_vget_laneq_f16_7:
; CHECK: vmovx.f16 s0, s3
; CHECK: vcvtb.f32.f16 s0, s0
entry:
%elt = extractelement <8 x half> %a, i32 7
%conv = fpext half %elt to float
ret float %conv
}
define <4 x half> @test_vset_lane_f16(<4 x half> %a, float %fb) nounwind {
; CHECK-LABEL: test_vset_lane_f16:
; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
; CHECK: vmov.16 d{{[0-9]+}}[3], r[[GPR]]
entry:
%b = fptrunc float %fb to half
%x = insertelement <4 x half> %a, half %b, i32 3
ret <4 x half> %x
}
define <8 x half> @test_vset_laneq_f16_1(<8 x half> %a, float %fb) nounwind {
; CHECK-LABEL: test_vset_laneq_f16_1:
; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
; CHECK: vmov.16 d{{[0-9]+}}[1], r[[GPR]]
entry:
%b = fptrunc float %fb to half
%x = insertelement <8 x half> %a, half %b, i32 1
ret <8 x half> %x
}
define <8 x half> @test_vset_laneq_f16_7(<8 x half> %a, float %fb) nounwind {
; CHECK-LABEL: test_vset_laneq_f16_7:
; CHECK: vmov.f16 r[[GPR:[0-9]+]], s{{[0-9]+}}
; CHECK: vmov.16 d{{[0-9]+}}[3], r[[GPR]]
entry:
%b = fptrunc float %fb to half
%x = insertelement <8 x half> %a, half %b, i32 7
ret <8 x half> %x
}