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llvm-project/llvm/test/CodeGen/ARM/execute-only.ll

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Rewrite ARM execute only support to avoid the use of a command line flag and unqualified ARMSubtarget lookup. Paired with a clang commit to use the new behavior. llvm-svn: 306927
2017-07-01 10:55:22 +08:00
; RUN: llc -mtriple=thumbv8m.base-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
[ARM] Allow execute only code on Cortex-m23 The NoMovt feature prevents the use of MOVW/MOVT instructions on Cortex-M23 for performance reasons. These instructions are required for execute only code so NoMovt should be disabled when that option is enabled. Differential Revision: https://reviews.llvm.org/D52551 llvm-svn: 343302
2018-09-28 16:55:19 +08:00
; RUN: llc -mtriple=thumbv8m.base-eabi -mcpu=cortex-m23 -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2BASE %s
Rewrite ARM execute only support to avoid the use of a command line flag and unqualified ARMSubtarget lookup. Paired with a clang commit to use the new behavior. llvm-svn: 306927
2017-07-01 10:55:22 +08:00
; RUN: llc -mtriple=thumbv7m-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
; RUN: llc -mtriple=thumbv8m.main-eabi -mattr=+execute-only %s -o - | FileCheck --check-prefix=CHECK --check-prefix=CHECK-T2 %s
[ARM] Implement execute-only support in CodeGen This implements execute-only support for ARM code generation, which prevents the compiler from generating data accesses to code sections. The following changes are involved: * Add the CodeGen option "-arm-execute-only" to the ARM code generator. * Add the clang flag "-mexecute-only" as well as the GCC-compatible alias "-mpure-code" to enable this option. * When enabled, literal pools are replaced with MOVW/MOVT instructions, with VMOV used in addition for floating-point literals. As the MOVT instruction is required, execute-only support is only available in Thumb mode for targets supporting ARMv8-M baseline or Thumb2. * Jump tables are placed in data sections when in execute-only mode. * The execute-only text section is assigned section ID 0, and is marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'. This also overrides selection of ELF sections for globals. llvm-svn: 289784
2016-12-15 15:59:08 +08:00
The initial .text section generated in object files was missing the SHF_ARM_PURECODE flag when being built with the -mexecute-only flag. All code sections of an ELF must have the flag set for the final .text section to be execute-only, otherwise the flag gets removed. A HasData flag is added to MCSection to aid in the determination that the section is empty. A virtual setTargetSectionFlags is added to MCELFObjectTargetWriter to allow subclasses to set target specific section flags to be added to sections which we then use in the ARM backend to set SHF_ARM_PURECODE. Patch by Ivan Lozano! Reviewed By: echristo Differential Revision: https://reviews.llvm.org/D48792 llvm-svn: 341593
2018-09-07 06:09:31 +08:00
; CHECK-NOT: {{^ *}}.text{{$}}
; CHECK: .section .text,"axy",%progbits,unique,0
[ARM] Implement execute-only support in CodeGen This implements execute-only support for ARM code generation, which prevents the compiler from generating data accesses to code sections. The following changes are involved: * Add the CodeGen option "-arm-execute-only" to the ARM code generator. * Add the clang flag "-mexecute-only" as well as the GCC-compatible alias "-mpure-code" to enable this option. * When enabled, literal pools are replaced with MOVW/MOVT instructions, with VMOV used in addition for floating-point literals. As the MOVT instruction is required, execute-only support is only available in Thumb mode for targets supporting ARMv8-M baseline or Thumb2. * Jump tables are placed in data sections when in execute-only mode. * The execute-only text section is assigned section ID 0, and is marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'. This also overrides selection of ELF sections for globals. llvm-svn: 289784
2016-12-15 15:59:08 +08:00
@var = global i32 0
define i32 @global() minsize {
; CHECK-LABEL: global:
; CHECK: movw [[GLOBDEST:r[0-9]+]], :lower16:var
; CHECK: movt [[GLOBDEST]], :upper16:var
%val = load i32, i32* @var
ret i32 %val
}
define i32 @jump_table(i32 %c, i32 %a, i32 %b) #0 {
; CHECK-LABEL: jump_table:
; CHECK-T2: adr.w [[REG_JT:r[0-9]+]], .LJTI1_0
; CHECK-T2: add.w [[REG_ENTRY:r[0-9]+]], [[REG_JT]], {{r[0-9]+}}, lsl #2
; CHECK-T2: mov pc, [[REG_ENTRY]]
; CHECK-T2BASE: lsls [[REG_OFFSET:r[0-9]+]], {{r[0-9]+}}, #2
; CHECK-T2BASE: adr [[REG_JT:r[0-9]+]], .LJTI1_0
[ARM] Place jump table as the first operand in additions When generating table jump code for switch statements, place the jump table label as the first operand in the various addition instructions in order to enable addressing mode selectors to better match index computation and possibly fold them into the addressing mode of the table entry load instruction. Differential revision: https://reviews.llvm.org/D39752 llvm-svn: 318033
2017-11-13 19:56:48 +08:00
; CHECK-T2BASE: adds [[REG_ENTRY:r[0-9]+]], [[REG_JT]], [[REG_OFFSET]]
[ARM] Implement execute-only support in CodeGen This implements execute-only support for ARM code generation, which prevents the compiler from generating data accesses to code sections. The following changes are involved: * Add the CodeGen option "-arm-execute-only" to the ARM code generator. * Add the clang flag "-mexecute-only" as well as the GCC-compatible alias "-mpure-code" to enable this option. * When enabled, literal pools are replaced with MOVW/MOVT instructions, with VMOV used in addition for floating-point literals. As the MOVT instruction is required, execute-only support is only available in Thumb mode for targets supporting ARMv8-M baseline or Thumb2. * Jump tables are placed in data sections when in execute-only mode. * The execute-only text section is assigned section ID 0, and is marked as unreadable with the SHF_ARM_PURECODE flag with symbol 'y'. This also overrides selection of ELF sections for globals. llvm-svn: 289784
2016-12-15 15:59:08 +08:00
; CHECK-T2BASE: mov pc, [[REG_ENTRY]]
; CHECK-LABEL: .LJTI1_0:
; CHECK-NEXT: b.w
; CHECK-NEXT: b.w
; CHECK-NEXT: b.w
; CHECK-NEXT: b.w
; CHECK-NEXT: b.w
; CHECK-NEXT: b.w
entry:
switch i32 %c, label %return [
i32 1, label %sw.bb
i32 2, label %sw.bb1
i32 3, label %sw.bb3
i32 4, label %sw.bb4
i32 5, label %sw.bb6
i32 6, label %sw.bb8
]
sw.bb: ; preds = %entry
%add = add nsw i32 %a, 6
br label %return
sw.bb1: ; preds = %entry
%add2 = add nsw i32 %a, 4
br label %return
sw.bb3: ; preds = %entry
%sub = add nsw i32 %a, -3
br label %return
sw.bb4: ; preds = %entry
%add5 = add nsw i32 %b, 5
br label %return
sw.bb6: ; preds = %entry
%add7 = add nsw i32 %a, 1
br label %return
sw.bb8: ; preds = %entry
%add9 = add nsw i32 %a, 2
br label %return
return: ; preds = %entry, %sw.bb8, %sw.bb6, %sw.bb4, %sw.bb3, %sw.bb1, %sw.bb
%retval.0 = phi i32 [ %add9, %sw.bb8 ], [ %add7, %sw.bb6 ], [ %add5, %sw.bb4 ], [ %sub, %sw.bb3 ], [ %add2, %sw.bb1 ], [ %add, %sw.bb ], [ 0, %entry ]
ret i32 %retval.0
}
@.str = private unnamed_addr constant [4 x i8] c"FOO\00", align 1
define hidden i8* @string_literal() {
entry:
; CHECK-LABEL: string_literal:
; CHECK-NOT: .asciz
; CHECK: .fnend
ret i8* getelementptr inbounds ([4 x i8], [4 x i8]* @.str, i32 0, i32 0)
}