forked from OSchip/llvm-project
34 lines
1.4 KiB
TableGen
34 lines
1.4 KiB
TableGen
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// RUN: llvm-tblgen -gen-global-isel -I %p/../../include -I %p/Common %s -o - | FileCheck %s
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// Boilerplate code.
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include "llvm/Target/Target.td"
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include "GlobalISelEmitterCommon.td"
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let TargetPrefix = "mytarget" in {
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def int_mytarget_anyptr : Intrinsic<[llvm_i32_ty], [llvm_anyptr_ty]>;
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}
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// Ensure that llvm_anyptr_ty on an intrinsic results in a
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// GIM_CheckPointerToAny rather than a GIM_CheckType.
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//
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// CHECK: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIPFP_MI_Predicate_frag_anyptr,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK-NEXT: // MIs[0] src
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// CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32,
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// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/MyTarget::GPR32RegClassID,
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// CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<<P:Predicate_frag_anyptr>> => (ANYLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src)
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// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/MyTarget::ANYLOAD,
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let hasSideEffects = 1 in {
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def ANYLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1),
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[(set GPR32:$dst, (load GPR32:$src1))]>;
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}
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def frag_anyptr : PatFrag<(ops node:$src),
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(int_mytarget_anyptr node:$src),
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[{ return true; // C++ code }]> {
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let GISelPredicateCode = [{ return true; // C++ code }];
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}
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def : Pat<(frag_anyptr GPR32:$src),
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(p0 (ANYLOAD GPR32:$src))>;
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