forked from OSchip/llvm-project
38 lines
1.2 KiB
TableGen
38 lines
1.2 KiB
TableGen
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// RUN: llvm-tblgen --gen-fast-isel -I %p/../../include %s 2>&1 | FileCheck %s
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include "llvm/Target/Target.td"
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//===- Define the necessary boilerplate for our test target. --------------===//
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def MyTargetISA : InstrInfo;
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def MyTarget : Target { let InstructionSet = MyTargetISA; }
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def R0 : Register<"r0"> { let Namespace = "MyTarget"; }
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def R1 : Register<"r0"> { let Namespace = "MyTarget"; }
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def GPR32M : RegisterClass<"MyTarget", [i32], 32, (add R0)>;
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def GPR32MOp : RegisterOperand<GPR32M>;
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def GPR32 : RegisterClass<"MyTarget", [i32], 32, (add R0, R1)>;
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def GPR32Op : RegisterOperand<GPR32>;
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class I<dag OOps, dag IOps, list<dag> Pat> : Instruction {
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let Namespace = "MyTarget";
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let OutOperandList = OOps;
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let InOperandList = IOps;
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let Pattern = Pat;
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}
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def HasA : Predicate<"Subtarget->hasA()">;
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let Predicates = [HasA] in {
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def ADD : I<(outs GPR32Op:$rd), (ins GPR32Op:$rs, GPR32Op:$rt),
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[(set GPR32Op:$rd, (add GPR32Op:$rs, GPR32Op:$rt))]>;
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let FastISelShouldIgnore = 1 in
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def ADD_M : I<(outs GPR32MOp:$rd), (ins GPR32MOp:$rs, GPR32MOp:$rt),
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[(set GPR32MOp:$rd, (add GPR32MOp:$rs, GPR32MOp:$rt))]>;
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}
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// CHECK-NOT: error: Duplicate predicate in FastISel table!
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