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llvm-project/llvm/test/MC/RISCV/fixups-expr.s

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[RISCV] Add symbol diff relocation support for RISC-V For RISC-V it is desirable to have relaxation happen in the linker once addresses are known, and as such the size between two instructions/byte sequences in a section could change. For most assembler expressions, this is fine, as the absolute address results in the expression being converted to a fixup, and finally relocations. However, for expressions such as .quad .L2-.L1, the assembler folds this down to a constant once fragments are laid out, under the assumption that the difference can no longer change, although in the case of linker relaxation the differences can change at link time, so the constant is incorrect. One place where this commonly appears is in debug information, where the size of a function expression is in a form similar to the above. This patch extends the assembler to allow an AsmBackend to declare that it does not want the assembler to fold down this expression, and instead generate a pair of relocations that allow the linker to carry out the calculation. In this case, the expression is not folded, but when it comes to emitting a fixup, the generic FK_Data_* fixups are converted into a pair, one for the addition half, one for the subtraction, and this is passed to the relocation generating methods as usual. I have named these FK_Data_Add_* and FK_Data_Sub_* to indicate which half these are for. For RISC-V, which supports this via e.g. the R_RISCV_ADD64, R_RISCV_SUB64 pair of relocations, these are also set to always emit relocations relative to local symbols rather than section offsets. This is to deal with the fact that if relocations were calculated on e.g. .text+8 and .text+4, the result 12 would be stored rather than 4 as both addends are added in the linker. Differential Revision: https://reviews.llvm.org/D45181 Patch by Simon Cook. llvm-svn: 333079
2018-05-23 20:36:18 +08:00
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+relax %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX %s
# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=-relax %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=NORELAX %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+relax %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=RELAX %s
# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=-relax %s \
# RUN: | llvm-readobj -r | FileCheck -check-prefix=NORELAX %s
# Check that subtraction expressions are emitted as two relocations
# only when relaxation is enabled
.globl G1
.globl G2
.L1:
G1:
addi a0, a0, 0
.L2:
G2:
.data
.dword .L2-.L1
.dword G2-G1
.word .L2-.L1
.word G2-G1
.half .L2-.L1
.half G2-G1
.byte .L2-.L1
.byte G2-G1
# RELAX: 0x0 R_RISCV_ADD64 .L2 0x0
# RELAX: 0x0 R_RISCV_SUB64 .L1 0x0
# RELAX: 0x8 R_RISCV_ADD64 G2 0x0
# RELAX: 0x8 R_RISCV_SUB64 G1 0x0
# RELAX: 0x10 R_RISCV_ADD32 .L2 0x0
# RELAX: 0x10 R_RISCV_SUB32 .L1 0x0
# RELAX: 0x14 R_RISCV_ADD32 G2 0x0
# RELAX: 0x14 R_RISCV_SUB32 G1 0x0
# RELAX: 0x18 R_RISCV_ADD16 .L2 0x0
# RELAX: 0x18 R_RISCV_SUB16 .L1 0x0
# RELAX: 0x1A R_RISCV_ADD16 G2 0x0
# RELAX: 0x1A R_RISCV_SUB16 G1 0x0
# RELAX: 0x1C R_RISCV_ADD8 .L2 0x0
# RELAX: 0x1C R_RISCV_SUB8 .L1 0x0
# RELAX: 0x1D R_RISCV_ADD8 G2 0x0
# RELAX: 0x1D R_RISCV_SUB8 G1 0x0
# NORELAX-NOT: R_RISCV