2017-10-30 22:50:10 +08:00
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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2021-04-14 01:54:00 +08:00
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; RUN: llc -O0 -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X64-O0
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2021-01-12 01:20:45 +08:00
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; RUN: llc -mtriple=x86_64-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X64
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2021-04-14 01:54:00 +08:00
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; RUN: llc -O0 -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X86-O0
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; RUN: llc -mtriple=i686-unknown -mcpu=skx -o - %s | FileCheck %s --check-prefix=X86
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2017-03-23 23:01:50 +08:00
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2020-12-05 05:51:01 +08:00
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@c = external dso_local constant i8, align 1
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2017-03-23 23:01:50 +08:00
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define void @foo() {
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2021-04-14 01:54:00 +08:00
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; X64-O0-LABEL: foo:
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; X64-O0: # %bb.0: # %entry
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; X64-O0-NEXT: movzbl c, %ecx
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; X64-O0-NEXT: xorl %eax, %eax
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; X64-O0-NEXT: subl %ecx, %eax
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; X64-O0-NEXT: movslq %eax, %rcx
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; X64-O0-NEXT: xorl %eax, %eax
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; X64-O0-NEXT: # kill: def $rax killed $eax
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; X64-O0-NEXT: subq %rcx, %rax
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; X64-O0-NEXT: # kill: def $al killed $al killed $rax
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; X64-O0-NEXT: cmpb $0, %al
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; X64-O0-NEXT: setne %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; X64-O0-NEXT: cmpb $0, c
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; X64-O0-NEXT: setne %al
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; X64-O0-NEXT: xorb $-1, %al
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; X64-O0-NEXT: xorb $-1, %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movzbl %al, %eax
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; X64-O0-NEXT: movzbl c, %ecx
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; X64-O0-NEXT: cmpl %ecx, %eax
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; X64-O0-NEXT: setle %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movzbl %al, %eax
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; X64-O0-NEXT: movl %eax, -{{[0-9]+}}(%rsp)
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; X64-O0-NEXT: retq
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;
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; X64-LABEL: foo:
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; X64: # %bb.0: # %entry
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; X64-NEXT: movzbl {{.*}}(%rip), %eax
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; X64-NEXT: xorl %ecx, %ecx
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; X64-NEXT: testl %eax, %eax
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; X64-NEXT: setne -{{[0-9]+}}(%rsp)
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2021-04-14 17:54:18 +08:00
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; X64-NEXT: setne %cl
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2021-04-14 01:54:00 +08:00
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; X64-NEXT: xorl %edx, %edx
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; X64-NEXT: cmpl %eax, %ecx
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; X64-NEXT: setle %dl
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; X64-NEXT: movl %edx, -{{[0-9]+}}(%rsp)
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; X64-NEXT: retq
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;
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2017-10-30 22:50:10 +08:00
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; X86-O0-LABEL: foo:
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2017-12-05 01:18:51 +08:00
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; X86-O0: # %bb.0: # %entry
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2021-04-14 01:54:00 +08:00
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; X86-O0-NEXT: subl $8, %esp
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; X86-O0-NEXT: .cfi_def_cfa_offset 12
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; X86-O0-NEXT: movb c, %al
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2020-09-15 21:16:14 +08:00
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; X86-O0-NEXT: cmpb $0, %al
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; X86-O0-NEXT: setne %al
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; X86-O0-NEXT: andb $1, %al
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2021-04-14 01:54:00 +08:00
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; X86-O0-NEXT: movb %al, {{[0-9]+}}(%esp)
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2017-10-30 22:50:11 +08:00
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; X86-O0-NEXT: cmpb $0, c
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2020-09-15 21:16:14 +08:00
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; X86-O0-NEXT: setne %al
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; X86-O0-NEXT: xorb $-1, %al
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; X86-O0-NEXT: xorb $-1, %al
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; X86-O0-NEXT: andb $1, %al
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; X86-O0-NEXT: movzbl %al, %eax
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; X86-O0-NEXT: movzbl c, %ecx
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; X86-O0-NEXT: cmpl %ecx, %eax
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; X86-O0-NEXT: setle %al
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; X86-O0-NEXT: andb $1, %al
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; X86-O0-NEXT: movzbl %al, %eax
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2021-04-14 01:54:00 +08:00
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; X86-O0-NEXT: movl %eax, (%esp)
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; X86-O0-NEXT: addl $8, %esp
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; X86-O0-NEXT: .cfi_def_cfa_offset 4
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; X86-O0-NEXT: retl
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2017-10-30 22:50:10 +08:00
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;
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2021-04-14 01:54:00 +08:00
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; X86-LABEL: foo:
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; X86: # %bb.0: # %entry
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; X86-NEXT: subl $8, %esp
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; X86-NEXT: .cfi_def_cfa_offset 12
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; X86-NEXT: movzbl c, %eax
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: testl %eax, %eax
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; X86-NEXT: setne {{[0-9]+}}(%esp)
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; X86-NEXT: setne %cl
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; X86-NEXT: xorl %edx, %edx
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; X86-NEXT: cmpl %eax, %ecx
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; X86-NEXT: setle %dl
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; X86-NEXT: movl %edx, {{[0-9]+}}(%esp)
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; X86-NEXT: addl $8, %esp
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; X86-NEXT: .cfi_def_cfa_offset 4
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; X86-NEXT: retl
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2017-03-23 23:01:50 +08:00
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entry:
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%a = alloca i8, align 1
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%b = alloca i32, align 4
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%0 = load i8, i8* @c, align 1
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%conv = zext i8 %0 to i32
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%sub = sub nsw i32 0, %conv
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%conv1 = sext i32 %sub to i64
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%sub2 = sub nsw i64 0, %conv1
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%conv3 = trunc i64 %sub2 to i8
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%tobool = icmp ne i8 %conv3, 0
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%frombool = zext i1 %tobool to i8
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store i8 %frombool, i8* %a, align 1
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%1 = load i8, i8* @c, align 1
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%tobool4 = icmp ne i8 %1, 0
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%lnot = xor i1 %tobool4, true
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%lnot5 = xor i1 %lnot, true
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%conv6 = zext i1 %lnot5 to i32
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%2 = load i8, i8* @c, align 1
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%conv7 = zext i8 %2 to i32
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%cmp = icmp sle i32 %conv6, %conv7
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%conv8 = zext i1 %cmp to i32
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store i32 %conv8, i32* %b, align 4
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ret void
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}
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2017-06-02 03:33:50 +08:00
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2020-12-05 05:51:01 +08:00
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@var_5 = external dso_local global i32, align 4
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@var_57 = external dso_local global i64, align 8
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@_ZN8struct_210member_2_0E = external dso_local global i64, align 8
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2017-06-02 03:33:50 +08:00
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define void @f1() {
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2021-04-14 01:54:00 +08:00
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; X64-O0-LABEL: f1:
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; X64-O0: # %bb.0: # %entry
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; X64-O0-NEXT: movslq var_5, %rax
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; X64-O0-NEXT: movabsq $8381627093, %rcx # imm = 0x1F3957AD5
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; X64-O0-NEXT: addq %rcx, %rax
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; X64-O0-NEXT: cmpq $0, %rax
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; X64-O0-NEXT: setne %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movb %al, -{{[0-9]+}}(%rsp)
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; X64-O0-NEXT: movl var_5, %eax
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; X64-O0-NEXT: xorl $-1, %eax
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; X64-O0-NEXT: cmpl $0, %eax
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; X64-O0-NEXT: setne %al
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; X64-O0-NEXT: xorb $-1, %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movzbl %al, %eax
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; X64-O0-NEXT: # kill: def $rax killed $eax
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; X64-O0-NEXT: movslq var_5, %rcx
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; X64-O0-NEXT: addq $7093, %rcx # imm = 0x1BB5
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; X64-O0-NEXT: cmpq %rcx, %rax
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; X64-O0-NEXT: setg %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movzbl %al, %eax
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; X64-O0-NEXT: # kill: def $rax killed $eax
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; X64-O0-NEXT: movq %rax, var_57
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; X64-O0-NEXT: movl var_5, %eax
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; X64-O0-NEXT: xorl $-1, %eax
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; X64-O0-NEXT: cmpl $0, %eax
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; X64-O0-NEXT: setne %al
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; X64-O0-NEXT: xorb $-1, %al
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; X64-O0-NEXT: andb $1, %al
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; X64-O0-NEXT: movzbl %al, %eax
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; X64-O0-NEXT: # kill: def $rax killed $eax
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; X64-O0-NEXT: movq %rax, _ZN8struct_210member_2_0E
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; X64-O0-NEXT: retq
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2017-10-30 22:50:10 +08:00
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;
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; X64-LABEL: f1:
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2017-12-05 01:18:51 +08:00
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; X64: # %bb.0: # %entry
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2017-10-30 22:50:10 +08:00
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; X64-NEXT: movslq {{.*}}(%rip), %rax
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2018-05-12 02:40:10 +08:00
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; X64-NEXT: movabsq $-8381627093, %rcx # imm = 0xFFFFFFFE0C6A852B
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; X64-NEXT: cmpq %rcx, %rax
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; X64-NEXT: setne -{{[0-9]+}}(%rsp)
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2017-10-30 22:50:10 +08:00
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; X64-NEXT: xorl %ecx, %ecx
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; X64-NEXT: cmpq $-1, %rax
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; X64-NEXT: sete %cl
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; X64-NEXT: xorl %edx, %edx
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; X64-NEXT: cmpl $-1, %eax
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; X64-NEXT: sete %dl
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; X64-NEXT: addq $7093, %rax # imm = 0x1BB5
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; X64-NEXT: xorl %esi, %esi
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; X64-NEXT: cmpq %rax, %rdx
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; X64-NEXT: setg %sil
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; X64-NEXT: movq %rsi, {{.*}}(%rip)
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; X64-NEXT: movq %rcx, {{.*}}(%rip)
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; X64-NEXT: retq
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;
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2021-04-14 01:54:00 +08:00
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; X86-O0-LABEL: f1:
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; X86-O0: # %bb.0: # %entry
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; X86-O0-NEXT: subl $1, %esp
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; X86-O0-NEXT: .cfi_def_cfa_offset 5
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; X86-O0-NEXT: movl var_5, %eax
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; X86-O0-NEXT: movl %eax, %ecx
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; X86-O0-NEXT: sarl $31, %ecx
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; X86-O0-NEXT: xorl $208307499, %eax # imm = 0xC6A852B
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; X86-O0-NEXT: xorl $-2, %ecx
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; X86-O0-NEXT: orl %ecx, %eax
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; X86-O0-NEXT: setne (%esp)
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; X86-O0-NEXT: movl var_5, %ecx
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; X86-O0-NEXT: movl %ecx, %eax
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; X86-O0-NEXT: sarl $31, %eax
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; X86-O0-NEXT: movl %ecx, %edx
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; X86-O0-NEXT: subl $-1, %edx
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; X86-O0-NEXT: sete %dl
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; X86-O0-NEXT: movzbl %dl, %edx
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; X86-O0-NEXT: addl $7093, %ecx # imm = 0x1BB5
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; X86-O0-NEXT: adcl $0, %eax
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; X86-O0-NEXT: subl %edx, %ecx
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; X86-O0-NEXT: sbbl $0, %eax
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; X86-O0-NEXT: setl %al
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; X86-O0-NEXT: movzbl %al, %eax
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; X86-O0-NEXT: movl %eax, var_57
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; X86-O0-NEXT: movl $0, var_57+4
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; X86-O0-NEXT: movl var_5, %eax
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; X86-O0-NEXT: subl $-1, %eax
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; X86-O0-NEXT: sete %al
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; X86-O0-NEXT: movzbl %al, %eax
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; X86-O0-NEXT: movl %eax, _ZN8struct_210member_2_0E
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; X86-O0-NEXT: movl $0, _ZN8struct_210member_2_0E+4
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; X86-O0-NEXT: addl $1, %esp
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; X86-O0-NEXT: .cfi_def_cfa_offset 4
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; X86-O0-NEXT: retl
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2017-10-30 22:50:10 +08:00
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;
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2021-04-14 01:54:00 +08:00
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; X86-LABEL: f1:
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; X86: # %bb.0: # %entry
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; X86-NEXT: pushl %esi
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; X86-NEXT: .cfi_def_cfa_offset 8
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; X86-NEXT: subl $1, %esp
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; X86-NEXT: .cfi_def_cfa_offset 9
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; X86-NEXT: .cfi_offset %esi, -8
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; X86-NEXT: movl var_5, %edx
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; X86-NEXT: movl %edx, %eax
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; X86-NEXT: xorl $208307499, %eax # imm = 0xC6A852B
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; X86-NEXT: movl %edx, %esi
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; X86-NEXT: sarl $31, %esi
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; X86-NEXT: movl %esi, %ecx
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; X86-NEXT: xorl $-2, %ecx
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; X86-NEXT: orl %eax, %ecx
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; X86-NEXT: setne (%esp)
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; X86-NEXT: movl %edx, %ecx
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; X86-NEXT: andl %esi, %ecx
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; X86-NEXT: xorl %eax, %eax
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; X86-NEXT: cmpl $-1, %ecx
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; X86-NEXT: sete %al
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; X86-NEXT: xorl %ecx, %ecx
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; X86-NEXT: cmpl $-1, %edx
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; X86-NEXT: sete %cl
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; X86-NEXT: addl $7093, %edx # imm = 0x1BB5
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; X86-NEXT: adcl $0, %esi
|
|
|
|
|
; X86-NEXT: cmpl %ecx, %edx
|
|
|
|
|
; X86-NEXT: sbbl $0, %esi
|
|
|
|
|
; X86-NEXT: setl %cl
|
|
|
|
|
; X86-NEXT: movzbl %cl, %ecx
|
|
|
|
|
; X86-NEXT: movl %ecx, var_57
|
|
|
|
|
; X86-NEXT: movl $0, var_57+4
|
|
|
|
|
; X86-NEXT: movl %eax, _ZN8struct_210member_2_0E
|
|
|
|
|
; X86-NEXT: movl $0, _ZN8struct_210member_2_0E+4
|
|
|
|
|
; X86-NEXT: addl $1, %esp
|
|
|
|
|
; X86-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
|
; X86-NEXT: popl %esi
|
|
|
|
|
; X86-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
|
; X86-NEXT: retl
|
2017-06-02 03:33:50 +08:00
|
|
|
entry:
|
|
|
|
|
%a = alloca i8, align 1
|
|
|
|
|
%0 = load i32, i32* @var_5, align 4
|
|
|
|
|
%conv = sext i32 %0 to i64
|
|
|
|
|
%add = add nsw i64 %conv, 8381627093
|
|
|
|
|
%tobool = icmp ne i64 %add, 0
|
|
|
|
|
%frombool = zext i1 %tobool to i8
|
|
|
|
|
store i8 %frombool, i8* %a, align 1
|
|
|
|
|
%1 = load i32, i32* @var_5, align 4
|
|
|
|
|
%neg = xor i32 %1, -1
|
|
|
|
|
%tobool1 = icmp ne i32 %neg, 0
|
|
|
|
|
%lnot = xor i1 %tobool1, true
|
|
|
|
|
%conv2 = zext i1 %lnot to i64
|
|
|
|
|
%2 = load i32, i32* @var_5, align 4
|
|
|
|
|
%conv3 = sext i32 %2 to i64
|
|
|
|
|
%add4 = add nsw i64 %conv3, 7093
|
|
|
|
|
%cmp = icmp sgt i64 %conv2, %add4
|
|
|
|
|
%conv5 = zext i1 %cmp to i64
|
|
|
|
|
store i64 %conv5, i64* @var_57, align 8
|
|
|
|
|
%3 = load i32, i32* @var_5, align 4
|
|
|
|
|
%neg6 = xor i32 %3, -1
|
|
|
|
|
%tobool7 = icmp ne i32 %neg6, 0
|
|
|
|
|
%lnot8 = xor i1 %tobool7, true
|
|
|
|
|
%conv9 = zext i1 %lnot8 to i64
|
|
|
|
|
store i64 %conv9, i64* @_ZN8struct_210member_2_0E, align 8
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2020-12-05 05:51:01 +08:00
|
|
|
@var_7 = external dso_local global i8, align 1
|
2017-06-02 03:33:50 +08:00
|
|
|
|
|
|
|
|
define void @f2() {
|
2021-04-14 01:54:00 +08:00
|
|
|
; X64-O0-LABEL: f2:
|
|
|
|
|
; X64-O0: # %bb.0: # %entry
|
|
|
|
|
; X64-O0-NEXT: movzbl var_7, %eax
|
|
|
|
|
; X64-O0-NEXT: cmpb $0, var_7
|
|
|
|
|
; X64-O0-NEXT: setne %cl
|
|
|
|
|
; X64-O0-NEXT: xorb $-1, %cl
|
|
|
|
|
; X64-O0-NEXT: andb $1, %cl
|
|
|
|
|
; X64-O0-NEXT: movzbl %cl, %ecx
|
|
|
|
|
; X64-O0-NEXT: xorl %ecx, %eax
|
|
|
|
|
; X64-O0-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
|
; X64-O0-NEXT: movw %ax, -{{[0-9]+}}(%rsp)
|
|
|
|
|
; X64-O0-NEXT: movzbl var_7, %eax
|
|
|
|
|
; X64-O0-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
|
; X64-O0-NEXT: cmpw $0, %ax
|
|
|
|
|
; X64-O0-NEXT: setne %al
|
|
|
|
|
; X64-O0-NEXT: xorb $-1, %al
|
|
|
|
|
; X64-O0-NEXT: andb $1, %al
|
|
|
|
|
; X64-O0-NEXT: movzbl %al, %eax
|
|
|
|
|
; X64-O0-NEXT: movzbl var_7, %ecx
|
|
|
|
|
; X64-O0-NEXT: cmpl %ecx, %eax
|
|
|
|
|
; X64-O0-NEXT: sete %al
|
|
|
|
|
; X64-O0-NEXT: andb $1, %al
|
|
|
|
|
; X64-O0-NEXT: movzbl %al, %eax
|
|
|
|
|
; X64-O0-NEXT: movw %ax, %cx
|
|
|
|
|
; X64-O0-NEXT: # implicit-def: $rax
|
|
|
|
|
; X64-O0-NEXT: movw %cx, (%rax)
|
|
|
|
|
; X64-O0-NEXT: retq
|
|
|
|
|
;
|
|
|
|
|
; X64-LABEL: f2:
|
|
|
|
|
; X64: # %bb.0: # %entry
|
|
|
|
|
; X64-NEXT: movzbl {{.*}}(%rip), %eax
|
|
|
|
|
; X64-NEXT: xorl %ecx, %ecx
|
|
|
|
|
; X64-NEXT: testl %eax, %eax
|
|
|
|
|
; X64-NEXT: sete %cl
|
2021-04-14 17:54:18 +08:00
|
|
|
; X64-NEXT: movl %eax, %edx
|
|
|
|
|
; X64-NEXT: xorl %ecx, %edx
|
|
|
|
|
; X64-NEXT: movw %dx, -{{[0-9]+}}(%rsp)
|
2021-04-14 01:54:00 +08:00
|
|
|
; X64-NEXT: xorl %edx, %edx
|
|
|
|
|
; X64-NEXT: cmpl %eax, %ecx
|
|
|
|
|
; X64-NEXT: sete %dl
|
|
|
|
|
; X64-NEXT: movw %dx, (%rax)
|
|
|
|
|
; X64-NEXT: retq
|
|
|
|
|
;
|
2017-10-30 22:50:10 +08:00
|
|
|
; X86-O0-LABEL: f2:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X86-O0: # %bb.0: # %entry
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-O0-NEXT: subl $2, %esp
|
|
|
|
|
; X86-O0-NEXT: .cfi_def_cfa_offset 6
|
[FastISel] Sink local value materializations to first use
Summary:
Local values are constants, global addresses, and stack addresses that
can't be folded into the instruction that uses them. For example, when
storing the address of a global variable into memory, we need to
materialize that address into a register.
FastISel doesn't want to materialize any given local value more than
once, so it generates all local value materialization code at
EmitStartPt, which always dominates the current insertion point. This
allows it to maintain a map of local value registers, and it knows that
the local value area will always dominate the current insertion point.
The downside is that local value instructions are always emitted without
a source location. This is done to prevent jumpy line tables, but it
means that the local value area will be considered part of the previous
statement. Consider this C code:
call1(); // line 1
++global; // line 2
++global; // line 3
call2(&global, &local); // line 4
Today we end up with assembly and line tables like this:
.loc 1 1
callq call1
leaq global(%rip), %rdi
leaq local(%rsp), %rsi
.loc 1 2
addq $1, global(%rip)
.loc 1 3
addq $1, global(%rip)
.loc 1 4
callq call2
The LEA instructions in the local value area have no source location and
are treated as being on line 1. Stepping through the code in a debugger
and correlating it with the assembly won't make much sense, because
these materializations are only required for line 4.
This is actually problematic for the VS debugger "set next statement"
feature, which effectively assumes that there are no registers live
across statement boundaries. By sinking the local value code into the
statement and fixing up the source location, we can make that feature
work. This was filed as https://bugs.llvm.org/show_bug.cgi?id=35975 and
https://crbug.com/793819.
This change is obviously not enough to make this feature work reliably
in all cases, but I felt that it was worth doing anyway because it
usually generates smaller, more comprehensible -O0 code. I measured a
0.12% regression in code generation time with LLC on the sqlite3
amalgamation, so I think this is worth doing.
There are some special cases worth calling out in the commit message:
1. local values materialized for phis
2. local values used by no-op casts
3. dead local value code
Local values can be materialized for phis, and this does not show up as
a vreg use in MachineRegisterInfo. In this case, if there are no other
uses, this patch sinks the value to the first terminator, EH label, or
the end of the BB if nothing else exists.
Local values may also be used by no-op casts, which adds the register to
the RegFixups table. Without reversing the RegFixups map direction, we
don't have enough information to sink these instructions.
Lastly, if the local value register has no other uses, we can delete it.
This comes up when fastisel tries two instruction selection approaches
and the first materializes the value but fails and the second succeeds
without using the local value.
Reviewers: aprantl, dblaikie, qcolombet, MatzeB, vsk, echristo
Subscribers: dotdash, chandlerc, hans, sdardis, amccarth, javed.absar, zturner, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D43093
llvm-svn: 327581
2018-03-15 05:54:21 +08:00
|
|
|
; X86-O0-NEXT: movzbl var_7, %eax
|
2017-10-30 22:50:11 +08:00
|
|
|
; X86-O0-NEXT: cmpb $0, var_7
|
[FastISel] Sink local value materializations to first use
Summary:
Local values are constants, global addresses, and stack addresses that
can't be folded into the instruction that uses them. For example, when
storing the address of a global variable into memory, we need to
materialize that address into a register.
FastISel doesn't want to materialize any given local value more than
once, so it generates all local value materialization code at
EmitStartPt, which always dominates the current insertion point. This
allows it to maintain a map of local value registers, and it knows that
the local value area will always dominate the current insertion point.
The downside is that local value instructions are always emitted without
a source location. This is done to prevent jumpy line tables, but it
means that the local value area will be considered part of the previous
statement. Consider this C code:
call1(); // line 1
++global; // line 2
++global; // line 3
call2(&global, &local); // line 4
Today we end up with assembly and line tables like this:
.loc 1 1
callq call1
leaq global(%rip), %rdi
leaq local(%rsp), %rsi
.loc 1 2
addq $1, global(%rip)
.loc 1 3
addq $1, global(%rip)
.loc 1 4
callq call2
The LEA instructions in the local value area have no source location and
are treated as being on line 1. Stepping through the code in a debugger
and correlating it with the assembly won't make much sense, because
these materializations are only required for line 4.
This is actually problematic for the VS debugger "set next statement"
feature, which effectively assumes that there are no registers live
across statement boundaries. By sinking the local value code into the
statement and fixing up the source location, we can make that feature
work. This was filed as https://bugs.llvm.org/show_bug.cgi?id=35975 and
https://crbug.com/793819.
This change is obviously not enough to make this feature work reliably
in all cases, but I felt that it was worth doing anyway because it
usually generates smaller, more comprehensible -O0 code. I measured a
0.12% regression in code generation time with LLC on the sqlite3
amalgamation, so I think this is worth doing.
There are some special cases worth calling out in the commit message:
1. local values materialized for phis
2. local values used by no-op casts
3. dead local value code
Local values can be materialized for phis, and this does not show up as
a vreg use in MachineRegisterInfo. In this case, if there are no other
uses, this patch sinks the value to the first terminator, EH label, or
the end of the BB if nothing else exists.
Local values may also be used by no-op casts, which adds the register to
the RegFixups table. Without reversing the RegFixups map direction, we
don't have enough information to sink these instructions.
Lastly, if the local value register has no other uses, we can delete it.
This comes up when fastisel tries two instruction selection approaches
and the first materializes the value but fails and the second succeeds
without using the local value.
Reviewers: aprantl, dblaikie, qcolombet, MatzeB, vsk, echristo
Subscribers: dotdash, chandlerc, hans, sdardis, amccarth, javed.absar, zturner, llvm-commits, hiraditya
Differential Revision: https://reviews.llvm.org/D43093
llvm-svn: 327581
2018-03-15 05:54:21 +08:00
|
|
|
; X86-O0-NEXT: setne %cl
|
|
|
|
|
; X86-O0-NEXT: xorb $-1, %cl
|
|
|
|
|
; X86-O0-NEXT: andb $1, %cl
|
2020-09-15 21:16:14 +08:00
|
|
|
; X86-O0-NEXT: movzbl %cl, %ecx
|
|
|
|
|
; X86-O0-NEXT: xorl %ecx, %eax
|
2019-05-16 20:50:39 +08:00
|
|
|
; X86-O0-NEXT: # kill: def $ax killed $ax killed $eax
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-O0-NEXT: movw %ax, (%esp)
|
2020-09-15 21:16:14 +08:00
|
|
|
; X86-O0-NEXT: movzbl var_7, %eax
|
|
|
|
|
; X86-O0-NEXT: # kill: def $ax killed $ax killed $eax
|
|
|
|
|
; X86-O0-NEXT: cmpw $0, %ax
|
|
|
|
|
; X86-O0-NEXT: setne %al
|
|
|
|
|
; X86-O0-NEXT: xorb $-1, %al
|
|
|
|
|
; X86-O0-NEXT: andb $1, %al
|
|
|
|
|
; X86-O0-NEXT: movzbl %al, %eax
|
|
|
|
|
; X86-O0-NEXT: movzbl var_7, %ecx
|
|
|
|
|
; X86-O0-NEXT: cmpl %ecx, %eax
|
|
|
|
|
; X86-O0-NEXT: sete %al
|
|
|
|
|
; X86-O0-NEXT: andb $1, %al
|
|
|
|
|
; X86-O0-NEXT: movzbl %al, %eax
|
2020-09-22 20:55:54 +08:00
|
|
|
; X86-O0-NEXT: movw %ax, %cx
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-O0-NEXT: # implicit-def: $eax
|
|
|
|
|
; X86-O0-NEXT: movw %cx, (%eax)
|
|
|
|
|
; X86-O0-NEXT: addl $2, %esp
|
|
|
|
|
; X86-O0-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
|
; X86-O0-NEXT: retl
|
2017-10-30 22:50:10 +08:00
|
|
|
;
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-LABEL: f2:
|
|
|
|
|
; X86: # %bb.0: # %entry
|
|
|
|
|
; X86-NEXT: subl $2, %esp
|
|
|
|
|
; X86-NEXT: .cfi_def_cfa_offset 6
|
2021-04-14 17:54:18 +08:00
|
|
|
; X86-NEXT: movzbl var_7, %ecx
|
|
|
|
|
; X86-NEXT: xorl %eax, %eax
|
|
|
|
|
; X86-NEXT: testl %ecx, %ecx
|
|
|
|
|
; X86-NEXT: sete %al
|
|
|
|
|
; X86-NEXT: movl %ecx, %edx
|
|
|
|
|
; X86-NEXT: xorl %eax, %edx
|
|
|
|
|
; X86-NEXT: movw %dx, (%esp)
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-NEXT: xorl %edx, %edx
|
2021-04-14 17:54:18 +08:00
|
|
|
; X86-NEXT: cmpl %ecx, %eax
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-NEXT: sete %dl
|
|
|
|
|
; X86-NEXT: movw %dx, (%eax)
|
|
|
|
|
; X86-NEXT: addl $2, %esp
|
|
|
|
|
; X86-NEXT: .cfi_def_cfa_offset 4
|
|
|
|
|
; X86-NEXT: retl
|
2017-06-02 03:33:50 +08:00
|
|
|
entry:
|
|
|
|
|
%a = alloca i16, align 2
|
|
|
|
|
%0 = load i8, i8* @var_7, align 1
|
|
|
|
|
%conv = zext i8 %0 to i32
|
|
|
|
|
%1 = load i8, i8* @var_7, align 1
|
|
|
|
|
%tobool = icmp ne i8 %1, 0
|
|
|
|
|
%lnot = xor i1 %tobool, true
|
|
|
|
|
%conv1 = zext i1 %lnot to i32
|
|
|
|
|
%xor = xor i32 %conv, %conv1
|
|
|
|
|
%conv2 = trunc i32 %xor to i16
|
|
|
|
|
store i16 %conv2, i16* %a, align 2
|
|
|
|
|
%2 = load i8, i8* @var_7, align 1
|
|
|
|
|
%conv3 = zext i8 %2 to i16
|
|
|
|
|
%tobool4 = icmp ne i16 %conv3, 0
|
|
|
|
|
%lnot5 = xor i1 %tobool4, true
|
|
|
|
|
%conv6 = zext i1 %lnot5 to i32
|
|
|
|
|
%3 = load i8, i8* @var_7, align 1
|
|
|
|
|
%conv7 = zext i8 %3 to i32
|
|
|
|
|
%cmp = icmp eq i32 %conv6, %conv7
|
|
|
|
|
%conv8 = zext i1 %cmp to i32
|
|
|
|
|
%conv9 = trunc i32 %conv8 to i16
|
|
|
|
|
store i16 %conv9, i16* undef, align 2
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
2020-12-05 05:51:01 +08:00
|
|
|
@var_13 = external dso_local global i32, align 4
|
|
|
|
|
@var_16 = external dso_local global i32, align 4
|
|
|
|
|
@var_46 = external dso_local global i32, align 4
|
2017-06-02 03:33:50 +08:00
|
|
|
|
|
|
|
|
define void @f3() #0 {
|
2021-04-14 01:54:00 +08:00
|
|
|
; X64-O0-LABEL: f3:
|
|
|
|
|
; X64-O0: # %bb.0: # %entry
|
|
|
|
|
; X64-O0-NEXT: movl var_13, %eax
|
|
|
|
|
; X64-O0-NEXT: xorl $-1, %eax
|
|
|
|
|
; X64-O0-NEXT: movl %eax, %eax
|
|
|
|
|
; X64-O0-NEXT: # kill: def $rax killed $eax
|
|
|
|
|
; X64-O0-NEXT: cmpl $0, var_13
|
|
|
|
|
; X64-O0-NEXT: setne %cl
|
|
|
|
|
; X64-O0-NEXT: xorb $-1, %cl
|
|
|
|
|
; X64-O0-NEXT: andb $1, %cl
|
|
|
|
|
; X64-O0-NEXT: movzbl %cl, %ecx
|
|
|
|
|
; X64-O0-NEXT: # kill: def $rcx killed $ecx
|
|
|
|
|
; X64-O0-NEXT: movl var_13, %edx
|
|
|
|
|
; X64-O0-NEXT: xorl $-1, %edx
|
|
|
|
|
; X64-O0-NEXT: xorl var_16, %edx
|
|
|
|
|
; X64-O0-NEXT: movl %edx, %edx
|
|
|
|
|
; X64-O0-NEXT: # kill: def $rdx killed $edx
|
|
|
|
|
; X64-O0-NEXT: andq %rdx, %rcx
|
|
|
|
|
; X64-O0-NEXT: orq %rcx, %rax
|
|
|
|
|
; X64-O0-NEXT: movq %rax, -{{[0-9]+}}(%rsp)
|
|
|
|
|
; X64-O0-NEXT: movl var_13, %eax
|
|
|
|
|
; X64-O0-NEXT: xorl $-1, %eax
|
|
|
|
|
; X64-O0-NEXT: movl %eax, %eax
|
|
|
|
|
; X64-O0-NEXT: # kill: def $rax killed $eax
|
|
|
|
|
; X64-O0-NEXT: cmpl $0, var_13
|
|
|
|
|
; X64-O0-NEXT: setne %cl
|
|
|
|
|
; X64-O0-NEXT: xorb $-1, %cl
|
|
|
|
|
; X64-O0-NEXT: andb $1, %cl
|
|
|
|
|
; X64-O0-NEXT: movzbl %cl, %ecx
|
|
|
|
|
; X64-O0-NEXT: # kill: def $rcx killed $ecx
|
|
|
|
|
; X64-O0-NEXT: andq $0, %rcx
|
|
|
|
|
; X64-O0-NEXT: orq %rcx, %rax
|
|
|
|
|
; X64-O0-NEXT: # kill: def $eax killed $eax killed $rax
|
|
|
|
|
; X64-O0-NEXT: movl %eax, var_46
|
|
|
|
|
; X64-O0-NEXT: retq
|
2017-10-30 22:50:10 +08:00
|
|
|
;
|
|
|
|
|
; X64-LABEL: f3:
|
2017-12-05 01:18:51 +08:00
|
|
|
; X64: # %bb.0: # %entry
|
2017-10-30 22:50:10 +08:00
|
|
|
; X64-NEXT: movl {{.*}}(%rip), %eax
|
2018-02-14 00:25:25 +08:00
|
|
|
; X64-NEXT: xorl %ecx, %ecx
|
|
|
|
|
; X64-NEXT: testl %eax, %eax
|
|
|
|
|
; X64-NEXT: notl %eax
|
|
|
|
|
; X64-NEXT: sete %cl
|
|
|
|
|
; X64-NEXT: movl {{.*}}(%rip), %edx
|
|
|
|
|
; X64-NEXT: xorl %eax, %edx
|
|
|
|
|
; X64-NEXT: andl %edx, %ecx
|
|
|
|
|
; X64-NEXT: orl %eax, %ecx
|
|
|
|
|
; X64-NEXT: movq %rcx, -{{[0-9]+}}(%rsp)
|
|
|
|
|
; X64-NEXT: movl %eax, {{.*}}(%rip)
|
2017-10-30 22:50:10 +08:00
|
|
|
; X64-NEXT: retq
|
|
|
|
|
;
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-O0-LABEL: f3:
|
|
|
|
|
; X86-O0: # %bb.0: # %entry
|
|
|
|
|
; X86-O0-NEXT: pushl %ebp
|
|
|
|
|
; X86-O0-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
|
; X86-O0-NEXT: .cfi_offset %ebp, -8
|
|
|
|
|
; X86-O0-NEXT: movl %esp, %ebp
|
|
|
|
|
; X86-O0-NEXT: .cfi_def_cfa_register %ebp
|
|
|
|
|
; X86-O0-NEXT: pushl %esi
|
|
|
|
|
; X86-O0-NEXT: andl $-8, %esp
|
|
|
|
|
; X86-O0-NEXT: subl $16, %esp
|
|
|
|
|
; X86-O0-NEXT: .cfi_offset %esi, -12
|
|
|
|
|
; X86-O0-NEXT: movl var_13, %ecx
|
|
|
|
|
; X86-O0-NEXT: movl %ecx, %eax
|
|
|
|
|
; X86-O0-NEXT: notl %eax
|
|
|
|
|
; X86-O0-NEXT: testl %ecx, %ecx
|
|
|
|
|
; X86-O0-NEXT: sete %cl
|
|
|
|
|
; X86-O0-NEXT: movzbl %cl, %ecx
|
|
|
|
|
; X86-O0-NEXT: movl var_16, %esi
|
|
|
|
|
; X86-O0-NEXT: movl %eax, %edx
|
|
|
|
|
; X86-O0-NEXT: xorl %esi, %edx
|
|
|
|
|
; X86-O0-NEXT: andl %edx, %ecx
|
|
|
|
|
; X86-O0-NEXT: orl %ecx, %eax
|
|
|
|
|
; X86-O0-NEXT: movl %eax, (%esp)
|
|
|
|
|
; X86-O0-NEXT: movl $0, {{[0-9]+}}(%esp)
|
|
|
|
|
; X86-O0-NEXT: movl var_13, %eax
|
|
|
|
|
; X86-O0-NEXT: notl %eax
|
|
|
|
|
; X86-O0-NEXT: movl %eax, var_46
|
|
|
|
|
; X86-O0-NEXT: leal -4(%ebp), %esp
|
|
|
|
|
; X86-O0-NEXT: popl %esi
|
|
|
|
|
; X86-O0-NEXT: popl %ebp
|
|
|
|
|
; X86-O0-NEXT: .cfi_def_cfa %esp, 4
|
|
|
|
|
; X86-O0-NEXT: retl
|
2017-10-30 22:50:10 +08:00
|
|
|
;
|
2021-04-14 01:54:00 +08:00
|
|
|
; X86-LABEL: f3:
|
|
|
|
|
; X86: # %bb.0: # %entry
|
|
|
|
|
; X86-NEXT: pushl %ebp
|
|
|
|
|
; X86-NEXT: .cfi_def_cfa_offset 8
|
|
|
|
|
; X86-NEXT: .cfi_offset %ebp, -8
|
|
|
|
|
; X86-NEXT: movl %esp, %ebp
|
|
|
|
|
; X86-NEXT: .cfi_def_cfa_register %ebp
|
|
|
|
|
; X86-NEXT: andl $-8, %esp
|
|
|
|
|
; X86-NEXT: subl $8, %esp
|
|
|
|
|
; X86-NEXT: movl var_13, %ecx
|
|
|
|
|
; X86-NEXT: xorl %eax, %eax
|
|
|
|
|
; X86-NEXT: testl %ecx, %ecx
|
|
|
|
|
; X86-NEXT: notl %ecx
|
|
|
|
|
; X86-NEXT: sete %al
|
|
|
|
|
; X86-NEXT: movl var_16, %edx
|
|
|
|
|
; X86-NEXT: xorl %ecx, %edx
|
|
|
|
|
; X86-NEXT: andl %eax, %edx
|
|
|
|
|
; X86-NEXT: orl %ecx, %edx
|
|
|
|
|
; X86-NEXT: movl %edx, (%esp)
|
|
|
|
|
; X86-NEXT: movl $0, {{[0-9]+}}(%esp)
|
|
|
|
|
; X86-NEXT: movl %ecx, var_46
|
|
|
|
|
; X86-NEXT: movl %ebp, %esp
|
|
|
|
|
; X86-NEXT: popl %ebp
|
|
|
|
|
; X86-NEXT: .cfi_def_cfa %esp, 4
|
|
|
|
|
; X86-NEXT: retl
|
2017-06-02 03:33:50 +08:00
|
|
|
entry:
|
|
|
|
|
%a = alloca i64, align 8
|
|
|
|
|
%0 = load i32, i32* @var_13, align 4
|
|
|
|
|
%neg = xor i32 %0, -1
|
|
|
|
|
%conv = zext i32 %neg to i64
|
|
|
|
|
%1 = load i32, i32* @var_13, align 4
|
|
|
|
|
%tobool = icmp ne i32 %1, 0
|
|
|
|
|
%lnot = xor i1 %tobool, true
|
|
|
|
|
%conv1 = zext i1 %lnot to i64
|
|
|
|
|
%2 = load i32, i32* @var_13, align 4
|
|
|
|
|
%neg2 = xor i32 %2, -1
|
|
|
|
|
%3 = load i32, i32* @var_16, align 4
|
|
|
|
|
%xor = xor i32 %neg2, %3
|
|
|
|
|
%conv3 = zext i32 %xor to i64
|
|
|
|
|
%and = and i64 %conv1, %conv3
|
|
|
|
|
%or = or i64 %conv, %and
|
|
|
|
|
store i64 %or, i64* %a, align 8
|
|
|
|
|
%4 = load i32, i32* @var_13, align 4
|
|
|
|
|
%neg4 = xor i32 %4, -1
|
|
|
|
|
%conv5 = zext i32 %neg4 to i64
|
|
|
|
|
%5 = load i32, i32* @var_13, align 4
|
|
|
|
|
%tobool6 = icmp ne i32 %5, 0
|
|
|
|
|
%lnot7 = xor i1 %tobool6, true
|
|
|
|
|
%conv8 = zext i1 %lnot7 to i64
|
|
|
|
|
%and9 = and i64 %conv8, 0
|
|
|
|
|
%or10 = or i64 %conv5, %and9
|
|
|
|
|
%conv11 = trunc i64 %or10 to i32
|
|
|
|
|
store i32 %conv11, i32* @var_46, align 4
|
|
|
|
|
ret void
|
|
|
|
|
}
|
|
|
|
|
|