2016-01-21 04:58:56 +08:00
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//===-- llvm/CodeGen/GlobalISel/IRTranslator.cpp - IRTranslator --*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the IRTranslator class.
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/GlobalISel/IRTranslator.h"
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2016-02-12 03:59:41 +08:00
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#include "llvm/ADT/SmallVector.h"
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2016-02-17 03:26:02 +08:00
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#include "llvm/CodeGen/GlobalISel/CallLowering.h"
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2016-02-11 06:59:27 +08:00
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#include "llvm/CodeGen/MachineFunction.h"
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2016-07-23 00:59:52 +08:00
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#include "llvm/CodeGen/MachineFrameInfo.h"
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2016-02-12 01:51:31 +08:00
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Constant.h"
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2016-02-11 06:59:27 +08:00
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#include "llvm/IR/Function.h"
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2016-07-30 06:32:36 +08:00
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#include "llvm/IR/IntrinsicInst.h"
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2016-02-12 01:51:31 +08:00
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Value.h"
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2016-07-30 06:32:36 +08:00
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#include "llvm/Target/TargetIntrinsicInfo.h"
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2016-02-12 02:53:28 +08:00
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#include "llvm/Target/TargetLowering.h"
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2016-02-11 06:59:27 +08:00
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#define DEBUG_TYPE "irtranslator"
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2016-01-21 04:58:56 +08:00
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using namespace llvm;
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char IRTranslator::ID = 0;
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2016-03-08 09:38:55 +08:00
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INITIALIZE_PASS(IRTranslator, "irtranslator", "IRTranslator LLVM IR -> MI",
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2016-07-26 11:29:18 +08:00
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false, false)
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2016-01-21 04:58:56 +08:00
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2016-02-12 01:53:23 +08:00
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IRTranslator::IRTranslator() : MachineFunctionPass(ID), MRI(nullptr) {
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2016-03-08 09:38:55 +08:00
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initializeIRTranslatorPass(*PassRegistry::getPassRegistry());
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2016-02-12 01:53:23 +08:00
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}
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2016-03-12 01:27:54 +08:00
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unsigned IRTranslator::getOrCreateVReg(const Value &Val) {
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unsigned &ValReg = ValToVReg[&Val];
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2016-02-12 01:51:31 +08:00
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// Check if this is the first time we see Val.
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2016-02-12 05:48:32 +08:00
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if (!ValReg) {
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2016-02-12 01:51:31 +08:00
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// Fill ValRegsSequence with the sequence of registers
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// we need to concat together to produce the value.
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assert(Val.getType()->isSized() &&
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"Don't know how to create an empty vreg");
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2016-03-12 01:27:54 +08:00
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assert(!Val.getType()->isAggregateType() && "Not yet implemented");
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2016-07-23 00:59:52 +08:00
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unsigned Size = DL->getTypeSizeInBits(Val.getType());
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2016-02-12 01:51:31 +08:00
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unsigned VReg = MRI->createGenericVirtualRegister(Size);
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2016-02-12 05:48:32 +08:00
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ValReg = VReg;
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2016-08-10 05:28:04 +08:00
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if (auto CV = dyn_cast<Constant>(&Val)) {
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bool Success = translate(*CV, VReg);
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if (!Success)
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report_fatal_error("unable to translate constant");
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}
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2016-02-12 01:51:31 +08:00
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}
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2016-02-12 05:48:32 +08:00
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return ValReg;
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}
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2016-07-27 04:23:26 +08:00
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unsigned IRTranslator::getMemOpAlignment(const Instruction &I) {
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unsigned Alignment = 0;
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Type *ValTy = nullptr;
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if (const StoreInst *SI = dyn_cast<StoreInst>(&I)) {
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Alignment = SI->getAlignment();
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ValTy = SI->getValueOperand()->getType();
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} else if (const LoadInst *LI = dyn_cast<LoadInst>(&I)) {
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Alignment = LI->getAlignment();
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ValTy = LI->getType();
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} else
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llvm_unreachable("unhandled memory instruction");
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return Alignment ? Alignment : DL->getABITypeAlignment(ValTy);
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}
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2016-03-12 01:27:43 +08:00
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MachineBasicBlock &IRTranslator::getOrCreateBB(const BasicBlock &BB) {
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MachineBasicBlock *&MBB = BBToMBB[&BB];
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2016-02-12 01:51:31 +08:00
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if (!MBB) {
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2016-02-12 01:53:23 +08:00
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MachineFunction &MF = MIRBuilder.getMF();
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2016-02-12 01:51:31 +08:00
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MBB = MF.CreateMachineBasicBlock();
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MF.push_back(MBB);
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}
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return *MBB;
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateBinaryOp(unsigned Opcode, const User &U) {
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2016-07-30 02:11:21 +08:00
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// FIXME: handle signed/unsigned wrapping flags.
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2016-02-11 06:59:27 +08:00
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// Get or create a virtual register for each value.
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// Unless the value is a Constant => loadimm cst?
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// or inline constant each time?
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// Creation of a virtual register needs to have a size.
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2016-08-11 07:02:41 +08:00
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unsigned Op0 = getOrCreateVReg(*U.getOperand(0));
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unsigned Op1 = getOrCreateVReg(*U.getOperand(1));
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unsigned Res = getOrCreateVReg(U);
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MIRBuilder.buildInstr(Opcode, LLT{*U.getType()})
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2016-07-30 01:43:52 +08:00
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.addDef(Res)
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.addUse(Op0)
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.addUse(Op1);
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2016-02-12 01:51:31 +08:00
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return true;
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2016-01-21 04:58:56 +08:00
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateRet(const User &U) {
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const ReturnInst &RI = cast<ReturnInst>(U);
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2016-07-30 02:11:21 +08:00
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const Value *Ret = RI.getReturnValue();
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2016-02-12 02:53:28 +08:00
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// The target may mess up with the insertion point, but
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// this is not important as a return is the last instruction
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// of the block anyway.
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2016-04-15 01:23:33 +08:00
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return CLI->lowerReturn(MIRBuilder, Ret, !Ret ? 0 : getOrCreateVReg(*Ret));
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2016-02-12 02:53:28 +08:00
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateBr(const User &U) {
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const BranchInst &BrInst = cast<BranchInst>(U);
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2016-07-30 01:58:00 +08:00
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unsigned Succ = 0;
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if (!BrInst.isUnconditional()) {
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// We want a G_BRCOND to the true BB followed by an unconditional branch.
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unsigned Tst = getOrCreateVReg(*BrInst.getCondition());
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const BasicBlock &TrueTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ++));
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MachineBasicBlock &TrueBB = getOrCreateBB(TrueTgt);
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MIRBuilder.buildBrCond(LLT{*BrInst.getCondition()->getType()}, Tst, TrueBB);
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2016-03-12 01:28:03 +08:00
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}
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2016-07-30 01:58:00 +08:00
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const BasicBlock &BrTgt = *cast<BasicBlock>(BrInst.getSuccessor(Succ));
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MachineBasicBlock &TgtBB = getOrCreateBB(BrTgt);
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MIRBuilder.buildBr(TgtBB);
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2016-03-12 01:28:03 +08:00
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// Link successors.
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MachineBasicBlock &CurBB = MIRBuilder.getMBB();
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for (const BasicBlock *Succ : BrInst.successors())
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CurBB.addSuccessor(&getOrCreateBB(*Succ));
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return true;
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateLoad(const User &U) {
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const LoadInst &LI = cast<LoadInst>(U);
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2016-07-27 04:23:26 +08:00
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assert(LI.isSimple() && "only simple loads are supported at the moment");
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MachineFunction &MF = MIRBuilder.getMF();
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unsigned Res = getOrCreateVReg(LI);
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unsigned Addr = getOrCreateVReg(*LI.getPointerOperand());
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LLT VTy{*LI.getType()}, PTy{*LI.getPointerOperand()->getType()};
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MIRBuilder.buildLoad(
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VTy, PTy, Res, Addr,
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*MF.getMachineMemOperand(MachinePointerInfo(LI.getPointerOperand()),
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MachineMemOperand::MOLoad,
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VTy.getSizeInBits() / 8, getMemOpAlignment(LI)));
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return true;
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateStore(const User &U) {
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const StoreInst &SI = cast<StoreInst>(U);
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2016-07-27 04:23:26 +08:00
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assert(SI.isSimple() && "only simple loads are supported at the moment");
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MachineFunction &MF = MIRBuilder.getMF();
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unsigned Val = getOrCreateVReg(*SI.getValueOperand());
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unsigned Addr = getOrCreateVReg(*SI.getPointerOperand());
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LLT VTy{*SI.getValueOperand()->getType()},
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PTy{*SI.getPointerOperand()->getType()};
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MIRBuilder.buildStore(
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VTy, PTy, Val, Addr,
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*MF.getMachineMemOperand(MachinePointerInfo(SI.getPointerOperand()),
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MachineMemOperand::MOStore,
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VTy.getSizeInBits() / 8, getMemOpAlignment(SI)));
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return true;
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateBitCast(const User &U) {
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if (LLT{*U.getOperand(0)->getType()} == LLT{*U.getType()}) {
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unsigned &Reg = ValToVReg[&U];
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2016-08-11 00:51:14 +08:00
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if (Reg)
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2016-08-11 07:02:41 +08:00
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MIRBuilder.buildCopy(Reg, getOrCreateVReg(*U.getOperand(0)));
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2016-08-11 00:51:14 +08:00
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else
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2016-08-11 07:02:41 +08:00
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Reg = getOrCreateVReg(*U.getOperand(0));
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2016-07-26 05:01:29 +08:00
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return true;
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}
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2016-08-11 07:02:41 +08:00
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return translateCast(TargetOpcode::G_BITCAST, U);
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2016-07-26 05:01:29 +08:00
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateCast(unsigned Opcode, const User &U) {
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unsigned Op = getOrCreateVReg(*U.getOperand(0));
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unsigned Res = getOrCreateVReg(U);
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MIRBuilder
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.buildInstr(Opcode, {LLT{*U.getType()}, LLT{*U.getOperand(0)->getType()}})
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2016-07-30 01:43:52 +08:00
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.addDef(Res)
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.addUse(Op);
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2016-07-26 05:01:29 +08:00
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return true;
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translateCall(const User &U) {
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const CallInst &CI = cast<CallInst>(U);
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2016-07-30 06:32:36 +08:00
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auto TII = MIRBuilder.getMF().getTarget().getIntrinsicInfo();
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2016-08-11 05:44:01 +08:00
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const Function *F = CI.getCalledFunction();
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if (!F || !F->isIntrinsic()) {
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// FIXME: handle multiple return values.
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unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
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SmallVector<unsigned, 8> Args;
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for (auto &Arg: CI.arg_operands())
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Args.push_back(getOrCreateVReg(*Arg));
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return CLI->lowerCall(MIRBuilder, CI,
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F ? 0 : getOrCreateVReg(*CI.getCalledValue()), Res,
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Args);
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}
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Intrinsic::ID ID = F->getIntrinsicID();
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2016-07-30 06:32:36 +08:00
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if (TII && ID == Intrinsic::not_intrinsic)
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2016-08-11 05:44:01 +08:00
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ID = static_cast<Intrinsic::ID>(TII->getIntrinsicID(F));
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2016-07-30 06:32:36 +08:00
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2016-08-11 05:44:01 +08:00
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assert(ID != Intrinsic::not_intrinsic && "unknown intrinsic");
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2016-07-30 06:32:36 +08:00
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// Need types (starting with return) & args.
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SmallVector<LLT, 4> Tys;
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Tys.emplace_back(*CI.getType());
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for (auto &Arg : CI.arg_operands())
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Tys.emplace_back(*Arg->getType());
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unsigned Res = CI.getType()->isVoidTy() ? 0 : getOrCreateVReg(CI);
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MachineInstrBuilder MIB =
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MIRBuilder.buildIntrinsic(Tys, ID, Res, !CI.doesNotAccessMemory());
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for (auto &Arg : CI.arg_operands()) {
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if (ConstantInt *CI = dyn_cast<ConstantInt>(Arg))
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MIB.addImm(CI->getSExtValue());
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else
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MIB.addUse(getOrCreateVReg(*Arg));
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}
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return true;
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}
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2016-07-23 00:59:52 +08:00
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bool IRTranslator::translateStaticAlloca(const AllocaInst &AI) {
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assert(AI.isStaticAlloca() && "only handle static allocas now");
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MachineFunction &MF = MIRBuilder.getMF();
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unsigned ElementSize = DL->getTypeStoreSize(AI.getAllocatedType());
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unsigned Size =
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ElementSize * cast<ConstantInt>(AI.getArraySize())->getZExtValue();
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2016-07-28 01:47:54 +08:00
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// Always allocate at least one byte.
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Size = std::max(Size, 1u);
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2016-07-23 00:59:52 +08:00
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unsigned Alignment = AI.getAlignment();
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if (!Alignment)
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Alignment = DL->getABITypeAlignment(AI.getAllocatedType());
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unsigned Res = getOrCreateVReg(AI);
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2016-07-29 04:13:42 +08:00
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int FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false, &AI);
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2016-07-23 00:59:52 +08:00
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MIRBuilder.buildFrameIndex(LLT::pointer(0), Res, FI);
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return true;
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}
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2016-08-11 07:02:41 +08:00
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bool IRTranslator::translatePHI(const User &U) {
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const PHINode &PI = cast<PHINode>(U);
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2016-08-06 01:16:40 +08:00
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MachineInstrBuilder MIB = MIRBuilder.buildInstr(TargetOpcode::PHI);
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MIB.addDef(getOrCreateVReg(PI));
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PendingPHIs.emplace_back(&PI, MIB.getInstr());
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return true;
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}
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void IRTranslator::finishPendingPhis() {
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for (std::pair<const PHINode *, MachineInstr *> &Phi : PendingPHIs) {
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const PHINode *PI = Phi.first;
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MachineInstrBuilder MIB(MIRBuilder.getMF(), Phi.second);
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// All MachineBasicBlocks exist, add them to the PHI. We assume IRTranslator
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// won't create extra control flow here, otherwise we need to find the
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// dominating predecessor here (or perhaps force the weirder IRTranslators
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// to provide a simple boundary).
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for (unsigned i = 0; i < PI->getNumIncomingValues(); ++i) {
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assert(BBToMBB[PI->getIncomingBlock(i)]->isSuccessor(MIB->getParent()) &&
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"I appear to have misunderstood Machine PHIs");
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MIB.addUse(getOrCreateVReg(*PI->getIncomingValue(i)));
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MIB.addMBB(BBToMBB[PI->getIncomingBlock(i)]);
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}
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}
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2016-08-06 01:50:36 +08:00
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PendingPHIs.clear();
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2016-08-06 01:16:40 +08:00
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}
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2016-02-11 06:59:27 +08:00
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bool IRTranslator::translate(const Instruction &Inst) {
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2016-02-12 01:53:23 +08:00
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MIRBuilder.setDebugLoc(Inst.getDebugLoc());
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2016-02-11 06:59:27 +08:00
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switch(Inst.getOpcode()) {
|
2016-08-11 07:02:41 +08:00
|
|
|
#define HANDLE_INST(NUM, OPCODE, CLASS) \
|
|
|
|
case Instruction::OPCODE: return translate##OPCODE(Inst);
|
|
|
|
#include "llvm/IR/Instruction.def"
|
2016-02-12 02:53:28 +08:00
|
|
|
default:
|
2016-08-11 07:02:41 +08:00
|
|
|
llvm_unreachable("unknown opcode");
|
2016-02-11 06:59:27 +08:00
|
|
|
}
|
2016-01-21 04:58:56 +08:00
|
|
|
}
|
|
|
|
|
2016-08-10 05:28:04 +08:00
|
|
|
bool IRTranslator::translate(const Constant &C, unsigned Reg) {
|
2016-08-10 07:01:30 +08:00
|
|
|
if (auto CI = dyn_cast<ConstantInt>(&C))
|
2016-08-10 05:28:04 +08:00
|
|
|
EntryBuilder.buildConstant(LLT{*CI->getType()}, Reg, CI->getZExtValue());
|
2016-08-10 07:01:30 +08:00
|
|
|
else if (isa<UndefValue>(C))
|
|
|
|
EntryBuilder.buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Reg);
|
2016-08-11 07:02:41 +08:00
|
|
|
else if (auto CE = dyn_cast<ConstantExpr>(&C)) {
|
|
|
|
switch(CE->getOpcode()) {
|
|
|
|
#define HANDLE_INST(NUM, OPCODE, CLASS) \
|
|
|
|
case Instruction::OPCODE: return translate##OPCODE(*CE);
|
|
|
|
#include "llvm/IR/Instruction.def"
|
|
|
|
default:
|
|
|
|
llvm_unreachable("unknown opcode");
|
|
|
|
}
|
|
|
|
} else
|
2016-08-10 07:01:30 +08:00
|
|
|
llvm_unreachable("unhandled constant kind");
|
2016-08-10 05:28:04 +08:00
|
|
|
|
2016-08-10 07:01:30 +08:00
|
|
|
return true;
|
2016-08-10 05:28:04 +08:00
|
|
|
}
|
|
|
|
|
2016-01-21 04:58:56 +08:00
|
|
|
|
2016-08-12 00:21:29 +08:00
|
|
|
void IRTranslator::finalizeFunction() {
|
|
|
|
finishPendingPhis();
|
|
|
|
|
2016-02-11 06:59:27 +08:00
|
|
|
// Release the memory used by the different maps we
|
|
|
|
// needed during the translation.
|
2016-02-12 05:48:32 +08:00
|
|
|
ValToVReg.clear();
|
2016-02-11 06:59:27 +08:00
|
|
|
Constants.clear();
|
2016-01-21 04:58:56 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
bool IRTranslator::runOnMachineFunction(MachineFunction &MF) {
|
2016-02-11 06:59:27 +08:00
|
|
|
const Function &F = *MF.getFunction();
|
2016-02-12 03:59:41 +08:00
|
|
|
if (F.empty())
|
|
|
|
return false;
|
2016-02-17 03:26:02 +08:00
|
|
|
CLI = MF.getSubtarget().getCallLowering();
|
2016-03-12 01:27:51 +08:00
|
|
|
MIRBuilder.setMF(MF);
|
2016-08-10 05:28:04 +08:00
|
|
|
EntryBuilder.setMF(MF);
|
2016-02-12 01:51:31 +08:00
|
|
|
MRI = &MF.getRegInfo();
|
2016-07-23 00:59:52 +08:00
|
|
|
DL = &F.getParent()->getDataLayout();
|
|
|
|
|
2016-08-06 01:50:36 +08:00
|
|
|
assert(PendingPHIs.empty() && "stale PHIs");
|
|
|
|
|
2016-02-12 03:59:41 +08:00
|
|
|
// Setup the arguments.
|
2016-03-12 01:27:43 +08:00
|
|
|
MachineBasicBlock &MBB = getOrCreateBB(F.front());
|
2016-03-12 01:27:47 +08:00
|
|
|
MIRBuilder.setMBB(MBB);
|
2016-02-12 03:59:41 +08:00
|
|
|
SmallVector<unsigned, 8> VRegArgs;
|
|
|
|
for (const Argument &Arg: F.args())
|
2016-03-12 01:27:54 +08:00
|
|
|
VRegArgs.push_back(getOrCreateVReg(Arg));
|
2016-02-17 03:26:02 +08:00
|
|
|
bool Succeeded =
|
2016-04-15 01:23:33 +08:00
|
|
|
CLI->lowerFormalArguments(MIRBuilder, F.getArgumentList(), VRegArgs);
|
2016-02-12 03:59:41 +08:00
|
|
|
if (!Succeeded)
|
|
|
|
report_fatal_error("Unable to lower arguments");
|
|
|
|
|
2016-08-10 05:28:04 +08:00
|
|
|
// Now that we've got the ABI handling code, it's safe to set a location for
|
|
|
|
// any Constants we find in the IR.
|
|
|
|
if (MBB.empty())
|
|
|
|
EntryBuilder.setMBB(MBB);
|
|
|
|
else
|
|
|
|
EntryBuilder.setInstr(MBB.back(), /* Before */ false);
|
|
|
|
|
2016-02-11 06:59:27 +08:00
|
|
|
for (const BasicBlock &BB: F) {
|
2016-03-12 01:27:43 +08:00
|
|
|
MachineBasicBlock &MBB = getOrCreateBB(BB);
|
2016-03-12 01:27:47 +08:00
|
|
|
// Set the insertion point of all the following translations to
|
|
|
|
// the end of this basic block.
|
|
|
|
MIRBuilder.setMBB(MBB);
|
2016-02-11 06:59:27 +08:00
|
|
|
for (const Instruction &Inst: BB) {
|
|
|
|
bool Succeeded = translate(Inst);
|
|
|
|
if (!Succeeded) {
|
|
|
|
DEBUG(dbgs() << "Cannot translate: " << Inst << '\n');
|
|
|
|
report_fatal_error("Unable to translate instruction");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2016-07-13 06:23:42 +08:00
|
|
|
|
2016-08-12 00:21:29 +08:00
|
|
|
finalizeFunction();
|
2016-08-06 01:16:40 +08:00
|
|
|
|
2016-07-13 06:23:42 +08:00
|
|
|
// Now that the MachineFrameInfo has been configured, no further changes to
|
|
|
|
// the reserved registers are possible.
|
|
|
|
MRI->freezeReservedRegs(MF);
|
|
|
|
|
2016-01-21 04:58:56 +08:00
|
|
|
return false;
|
|
|
|
}
|