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llvm-project/llvm/test/CodeGen/Mips/msa/i8.ll

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[mips][msa] Summarize tests Adds a comment to the start of each test summarizing the area the test covers. llvm-svn: 189465
2013-08-28 18:02:29 +08:00
; Test the MSA intrinsics that are encoded with the I8 instruction format.
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
; RUN: llc -march=mips -mattr=+msa < %s | FileCheck %s
@llvm_mips_andi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_andi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_andi_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_andi_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.andi.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_andi_b_RES
ret void
}
declare <16 x i8> @llvm.mips.andi.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_andi_b_test:
; CHECK: ld.b
; CHECK: andi.b
; CHECK: st.b
; CHECK: .size llvm_mips_andi_b_test
;
@llvm_mips_bmnzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bmnzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_bmnzi_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bmnzi_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.bmnzi.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_bmnzi_b_RES
ret void
}
declare <16 x i8> @llvm.mips.bmnzi.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_bmnzi_b_test:
; CHECK: ld.b
; CHECK: bmnzi.b
; CHECK: st.b
; CHECK: .size llvm_mips_bmnzi_b_test
;
@llvm_mips_bmzi_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bmzi_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_bmzi_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bmzi_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.bmzi.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_bmzi_b_RES
ret void
}
declare <16 x i8> @llvm.mips.bmzi.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_bmzi_b_test:
; CHECK: ld.b
; CHECK: bmzi.b
; CHECK: st.b
; CHECK: .size llvm_mips_bmzi_b_test
;
@llvm_mips_bseli_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_bseli_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_bseli_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_bseli_b_ARG1
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
%1 = tail call <16 x i8> @llvm.mips.bseli.b(<16 x i8> %0, <16 x i8> %0, i32 25)
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
store <16 x i8> %1, <16 x i8>* @llvm_mips_bseli_b_RES
ret void
}
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
declare <16 x i8> @llvm.mips.bseli.b(<16 x i8>, <16 x i8>, i32) nounwind
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
; CHECK: llvm_mips_bseli_b_test:
; CHECK: ld.b
; CHECK: bseli.b
; CHECK: st.b
; CHECK: .size llvm_mips_bseli_b_test
;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
@llvm_mips_nori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_nori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_nori_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_nori_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.nori.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_nori_b_RES
ret void
}
declare <16 x i8> @llvm.mips.nori.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_nori_b_test:
; CHECK: ld.b
; CHECK: nori.b
; CHECK: st.b
; CHECK: .size llvm_mips_nori_b_test
;
@llvm_mips_ori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_ori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_ori_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_ori_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.ori.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_ori_b_RES
ret void
}
declare <16 x i8> @llvm.mips.ori.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_ori_b_test:
; CHECK: ld.b
; CHECK: ori.b
; CHECK: st.b
; CHECK: .size llvm_mips_ori_b_test
;
@llvm_mips_shf_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_shf_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_shf_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_shf_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.shf.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_shf_b_RES
ret void
}
declare <16 x i8> @llvm.mips.shf.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_shf_b_test:
; CHECK: ld.b
; CHECK: shf.b
; CHECK: st.b
; CHECK: .size llvm_mips_shf_b_test
;
@llvm_mips_shf_h_ARG1 = global <8 x i16> <i16 0, i16 1, i16 2, i16 3, i16 4, i16 5, i16 6, i16 7>, align 16
@llvm_mips_shf_h_RES = global <8 x i16> <i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0, i16 0>, align 16
define void @llvm_mips_shf_h_test() nounwind {
entry:
%0 = load <8 x i16>* @llvm_mips_shf_h_ARG1
%1 = tail call <8 x i16> @llvm.mips.shf.h(<8 x i16> %0, i32 25)
store <8 x i16> %1, <8 x i16>* @llvm_mips_shf_h_RES
ret void
}
declare <8 x i16> @llvm.mips.shf.h(<8 x i16>, i32) nounwind
; CHECK: llvm_mips_shf_h_test:
; CHECK: ld.h
; CHECK: shf.h
; CHECK: st.h
; CHECK: .size llvm_mips_shf_h_test
;
@llvm_mips_shf_w_ARG1 = global <4 x i32> <i32 0, i32 1, i32 2, i32 3>, align 16
@llvm_mips_shf_w_RES = global <4 x i32> <i32 0, i32 0, i32 0, i32 0>, align 16
define void @llvm_mips_shf_w_test() nounwind {
entry:
%0 = load <4 x i32>* @llvm_mips_shf_w_ARG1
%1 = tail call <4 x i32> @llvm.mips.shf.w(<4 x i32> %0, i32 25)
store <4 x i32> %1, <4 x i32>* @llvm_mips_shf_w_RES
ret void
}
declare <4 x i32> @llvm.mips.shf.w(<4 x i32>, i32) nounwind
; CHECK: llvm_mips_shf_w_test:
; CHECK: ld.w
; CHECK: shf.w
; CHECK: st.w
; CHECK: .size llvm_mips_shf_w_test
;
@llvm_mips_xori_b_ARG1 = global <16 x i8> <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15>, align 16
@llvm_mips_xori_b_RES = global <16 x i8> <i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0, i8 0>, align 16
define void @llvm_mips_xori_b_test() nounwind {
entry:
%0 = load <16 x i8>* @llvm_mips_xori_b_ARG1
%1 = tail call <16 x i8> @llvm.mips.xori.b(<16 x i8> %0, i32 25)
store <16 x i8> %1, <16 x i8>* @llvm_mips_xori_b_RES
ret void
}
declare <16 x i8> @llvm.mips.xori.b(<16 x i8>, i32) nounwind
; CHECK: llvm_mips_xori_b_test:
; CHECK: ld.b
; CHECK: xori.b
; CHECK: st.b
; CHECK: .size llvm_mips_xori_b_test
;