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llvm-project/llvm/test/CodeGen/RISCV/machineoutliner.mir

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[RISCV] Enable the machine outliner for RISC-V This patch enables the machine outliner for RISC-V and adds the necessary logic for checking whether sequences can be safely outlined, and describing how they should be outlined. Outlined functions are called using the register t0 (x5) as the return address register, which must be available for an occurrence of a sequence to be safely outlined. Differential Revision: https://reviews.llvm.org/D66210
2019-12-20 00:41:53 +08:00
# RUN: llc -march=riscv32 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=RV32I-MO %s
# RUN: llc -march=riscv64 -x mir -run-pass=machine-outliner -simplify-mir -verify-machineinstrs < %s \
# RUN: | FileCheck -check-prefix=RV64I-MO %s
--- |
define i32 @outline_0(i32 %a, i32 %b) { ret i32 0 }
define i32 @outline_1(i32 %a, i32 %b) { ret i32 0 }
define i32 @outline_2(i32 %a, i32 %b) { ret i32 0 }
; Should not outline linkonce_odr functions which could be deduplicated by the
; linker.
define linkonce_odr i32 @dont_outline_0(i32 %a, i32 %b) { ret i32 0 }
; Should not outline functions with named linker sections
define i32 @dont_outline_1(i32 %a, i32 %b) section "named" { ret i32 0 }
; Cannot outline if the X5 (t0) register is not free
define i32 @dont_outline_2(i32 %a, i32 %b) { ret i32 0 }
...
---
name: outline_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: outline_0
; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
;
; RV64I-MO-LABEL: name: outline_0
; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x10
...
---
name: outline_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: outline_1
; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
;
; RV64I-MO-LABEL: name: outline_1
; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x10
...
---
name: outline_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: outline_2
; RV32I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
;
; RV64I-MO-LABEL: name: outline_2
; RV64I-MO: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x10
...
---
name: dont_outline_0
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: dont_outline_0
; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
;
; RV64I-MO-LABEL: name: dont_outline_0
; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x10
...
---
name: dont_outline_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11
; RV32I-MO-LABEL: name: dont_outline_1
; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
;
; RV64I-MO-LABEL: name: dont_outline_1
; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
PseudoRET implicit $x10
...
---
name: dont_outline_2
tracksRegLiveness: true
body: |
bb.0:
liveins: $x10, $x11, $x5
; RV32I-MO-LABEL: name: dont_outline_2
; RV32I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
;
; RV64I-MO-LABEL: name: dont_outline_2
; RV64I-MO-NOT: $x5 = PseudoCALLReg {{.*}} @OUTLINED_FUNCTION_0
$x11 = ORI $x11, 1023
$x12 = ADDI $x10, 17
$x11 = AND $x12, $x11
$x10 = SUB $x10, $x11
$x10 = ADD $x10, $x5
PseudoRET implicit $x10
...