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llvm-project/llvm/test/CodeGen/AArch64/swiftcc.ll

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Swift Calling Convetion: add support for AArch64. It will just be the same as the regular calling convention. rdar://28029509 llvm-svn: 279853
2016-08-27 03:28:17 +08:00
; RUN: llc -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
; RUN: llc -O0 -verify-machineinstrs -mtriple=aarch64-apple-ios -o - %s | FileCheck %s
AArch64: support arm64_32, an ILP32 slice for watchOS. This is the main CodeGen patch to support the arm64_32 watchOS ABI in LLVM. FastISel is mostly disabled for now since it would generate incorrect code for ILP32. llvm-svn: 371722
2019-09-12 18:22:23 +08:00
; RUN: llc -verify-machineinstrs -mtriple=arm64_32-apple-ios -o - %s | FileCheck %s
; RUN: llc -O0 -verify-machineinstrs -mtriple=arm64_32-apple-ios -o - %s | FileCheck %s
Swift Calling Convetion: add support for AArch64. It will just be the same as the regular calling convention. rdar://28029509 llvm-svn: 279853
2016-08-27 03:28:17 +08:00
; CHECK: t1
; CHECK: fadd s0, s0, s1
; CHECK: ret
define swiftcc float @t1(float %a, float %b) {
entry:
%add = fadd float %a, %b
ret float %add
}