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llvm-project/llvm/test/CodeGen/ARM/vuzp.ll

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ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
; RUN: llc -mtriple=arm-eabi -mattr=+neon %s -o - | FileCheck %s
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
define <8 x i8> @vuzpi8(<8 x i8>* %A, <8 x i8>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpi8:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vuzp.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <16 x i8> @vuzpi8_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpi8_Qres:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d19, [r0]
; CHECK-NEXT: vldr d18, [r1]
; CHECK-NEXT: vmov.u8 r0, d19[0]
; CHECK-NEXT: vmov.8 d16[0], r0
; CHECK-NEXT: vmov.u8 r0, d19[2]
; CHECK-NEXT: vmov.8 d16[1], r0
; CHECK-NEXT: vmov.u8 r0, d19[4]
; CHECK-NEXT: vmov.8 d16[2], r0
; CHECK-NEXT: vmov.u8 r0, d19[6]
; CHECK-NEXT: vmov.8 d16[3], r0
; CHECK-NEXT: vmov.u8 r0, d18[0]
; CHECK-NEXT: vmov.8 d16[4], r0
; CHECK-NEXT: vmov.u8 r0, d18[2]
; CHECK-NEXT: vmov.8 d16[5], r0
; CHECK-NEXT: vmov.u8 r0, d18[4]
; CHECK-NEXT: vmov.8 d16[6], r0
; CHECK-NEXT: vmov.u8 r0, d18[6]
; CHECK-NEXT: vmov.8 d16[7], r0
; CHECK-NEXT: vmov.u8 r0, d19[1]
; CHECK-NEXT: vmov.8 d17[0], r0
; CHECK-NEXT: vmov.u8 r0, d19[3]
; CHECK-NEXT: vmov.8 d17[1], r0
; CHECK-NEXT: vmov.u8 r0, d19[5]
; CHECK-NEXT: vmov.8 d17[2], r0
; CHECK-NEXT: vmov.u8 r0, d19[7]
; CHECK-NEXT: vmov.8 d17[3], r0
; CHECK-NEXT: vmov.u8 r0, d18[1]
; CHECK-NEXT: vmov.8 d17[4], r0
; CHECK-NEXT: vmov.u8 r0, d18[3]
; CHECK-NEXT: vmov.8 d17[5], r0
; CHECK-NEXT: vmov.u8 r0, d18[5]
; CHECK-NEXT: vmov.8 d17[6], r0
; CHECK-NEXT: vmov.u8 r0, d18[7]
; CHECK-NEXT: vmov.8 d17[7], r0
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <16 x i8> %tmp3
}
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
define <4 x i16> @vuzpi16(<4 x i16>* %A, <4 x i16>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpi16:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vuzp.16 d17, d16
; CHECK-NEXT: vadd.i16 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = add <4 x i16> %tmp3, %tmp4
ret <4 x i16> %tmp5
}
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <8 x i16> @vuzpi16_Qres(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpi16_Qres:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r0]
; CHECK-NEXT: vldr d17, [r1]
; CHECK-NEXT: vmov.u16 r0, d16[0]
; CHECK-NEXT: vmov.16 d18[0], r0
; CHECK-NEXT: vmov.u16 r0, d16[2]
; CHECK-NEXT: vmov.16 d18[1], r0
; CHECK-NEXT: vmov.u16 r0, d17[0]
; CHECK-NEXT: vmov.16 d18[2], r0
; CHECK-NEXT: vmov.u16 r0, d17[2]
; CHECK-NEXT: vmov.16 d18[3], r0
; CHECK-NEXT: vmov.u16 r0, d16[1]
; CHECK-NEXT: vmov.16 d19[0], r0
; CHECK-NEXT: vmov.u16 r0, d16[3]
; CHECK-NEXT: vmov.16 d19[1], r0
; CHECK-NEXT: vmov.u16 r0, d17[1]
; CHECK-NEXT: vmov.16 d19[2], r0
; CHECK-NEXT: vmov.u16 r0, d17[3]
; CHECK-NEXT: vmov.16 d19[3], r0
; CHECK-NEXT: vmov r0, r1, d18
; CHECK-NEXT: vmov r2, r3, d19
; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = shufflevector <4 x i16> %tmp1, <4 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x i16> %tmp3
}
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
; VUZP.32 is equivalent to VTRN.32 for 64-bit vectors.
define <16 x i8> @vuzpQi8(<16 x i8>* %A, <16 x i8>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpQi8:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.8 q9, q8
; CHECK-NEXT: vadd.i8 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30>
%tmp4 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <16 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
%tmp5 = add <16 x i8> %tmp3, %tmp4
ret <16 x i8> %tmp5
}
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <32 x i8> @vuzpQi8_QQres(<16 x i8>* %A, <16 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpQi8_QQres:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.8 q9, q8
; CHECK-NEXT: vst1.8 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <16 x i8>, <16 x i8>* %A
%tmp2 = load <16 x i8>, <16 x i8>* %B
%tmp3 = shufflevector <16 x i8> %tmp1, <16 x i8> %tmp2, <32 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 16, i32 18, i32 20, i32 22, i32 24, i32 26, i32 28, i32 30, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15, i32 17, i32 19, i32 21, i32 23, i32 25, i32 27, i32 29, i32 31>
ret <32 x i8> %tmp3
}
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
define <8 x i16> @vuzpQi16(<8 x i16>* %A, <8 x i16>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpQi16:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vadd.i16 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <16 x i16> @vuzpQi16_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpQi16_QQres:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 9, i32 11, i32 13, i32 15>
ret <16 x i16> %tmp3
}
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
define <4 x i32> @vuzpQi32(<4 x i32>* %A, <4 x i32>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpQi32:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vadd.i32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
%tmp5 = add <4 x i32> %tmp3, %tmp4
ret <4 x i32> %tmp5
}
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <8 x i32> @vuzpQi32_QQres(<4 x i32>* %A, <4 x i32>* %B) nounwind {
; CHECK-LABEL: vuzpQi32_QQres:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i32>, <4 x i32>* %B
%tmp3 = shufflevector <4 x i32> %tmp1, <4 x i32> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x i32> %tmp3
}
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
define <4 x float> @vuzpQf(<4 x float>* %A, <4 x float>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpQf:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vadd.f32 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 0, i32 2, i32 4, i32 6>
%tmp4 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <4 x i32> <i32 1, i32 3, i32 5, i32 7>
Fix tests to use fadd, fsub, and fmul, instead of add, sub, and mul, when the type is floating-point. llvm-svn: 102969
2010-05-04 06:36:46 +08:00
%tmp5 = fadd <4 x float> %tmp3, %tmp4
Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations, now using shuffles instead of intrinsics. llvm-svn: 79673
2009-08-22 04:54:19 +08:00
ret <4 x float> %tmp5
}
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <8 x float> @vuzpQf_QQres(<4 x float>* %A, <4 x float>* %B) nounwind {
; CHECK-LABEL: vuzpQf_QQres:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.32 q9, q8
; CHECK-NEXT: vst1.32 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <4 x float>, <4 x float>* %A
%tmp2 = load <4 x float>, <4 x float>* %B
%tmp3 = shufflevector <4 x float> %tmp1, <4 x float> %tmp2, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 1, i32 3, i32 5, i32 7>
ret <8 x float> %tmp3
}
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
; Undef shuffle indices should not prevent matching to VUZP:
define <8 x i8> @vuzpi8_undef(<8 x i8>* %A, <8 x i8>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpi8_undef:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d16, [r1]
; CHECK-NEXT: vldr d17, [r0]
; CHECK-NEXT: vuzp.8 d17, d16
; CHECK-NEXT: vadd.i8 d16, d17, d16
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
%tmp5 = add <8 x i8> %tmp3, %tmp4
ret <8 x i8> %tmp5
}
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <16 x i8> @vuzpi8_undef_Qres(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: vuzpi8_undef_Qres:
; CHECK: @ BB#0:
; CHECK-NEXT: vldr d18, [r0]
; CHECK-NEXT: vldr d19, [r1]
; CHECK-NEXT: vmov.u8 r0, d18[0]
; CHECK-NEXT: vmov.8 d16[0], r0
; CHECK-NEXT: vmov.u8 r0, d18[2]
; CHECK-NEXT: vmov.8 d16[1], r0
; CHECK-NEXT: vmov.u8 r0, d19[0]
; CHECK-NEXT: vmov.8 d16[4], r0
; CHECK-NEXT: vmov.u8 r0, d19[2]
; CHECK-NEXT: vmov.8 d16[5], r0
; CHECK-NEXT: vmov.u8 r0, d19[4]
; CHECK-NEXT: vmov.8 d16[6], r0
; CHECK-NEXT: vmov.u8 r0, d19[6]
; CHECK-NEXT: vmov.8 d16[7], r0
; CHECK-NEXT: vmov.u8 r0, d18[1]
; CHECK-NEXT: vmov.8 d17[0], r0
; CHECK-NEXT: vmov.u8 r0, d18[3]
; CHECK-NEXT: vmov.8 d17[1], r0
; CHECK-NEXT: vmov.u8 r0, d18[5]
; CHECK-NEXT: vmov.8 d17[2], r0
; CHECK-NEXT: vmov.u8 r0, d18[7]
; CHECK-NEXT: vmov.8 d17[3], r0
; CHECK-NEXT: vmov.u8 r0, d19[5]
; CHECK-NEXT: vmov.8 d17[6], r0
; CHECK-NEXT: vmov.u8 r0, d19[7]
; CHECK-NEXT: vmov.8 d17[7], r0
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = shufflevector <8 x i8> %tmp1, <8 x i8> %tmp2, <16 x i32> <i32 0, i32 2, i32 undef, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 7, i32 undef, i32 undef, i32 13, i32 15>
ret <16 x i8> %tmp3
}
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
define <8 x i16> @vuzpQi16_undef(<8 x i16>* %A, <8 x i16>* %B) nounwind {
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
; CHECK-LABEL: vuzpQi16_undef:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vadd.i16 q8, q9, q8
; CHECK-NEXT: vmov r0, r1, d16
; CHECK-NEXT: vmov r2, r3, d17
; CHECK-NEXT: mov pc, lr
[opaque pointer type] Add textual IR support for explicit type parameter to load instruction Essentially the same as the GEP change in r230786. A similar migration script can be used to update test cases, though a few more test case improvements/changes were required this time around: (r229269-r229278) import fileinput import sys import re pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)") for line in sys.stdin: sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line)) Reviewers: rafael, dexonsmith, grosser Differential Revision: http://reviews.llvm.org/D7649 llvm-svn: 230794
2015-02-28 05:17:42 +08:00
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
Allow more cases of undef shuffle indices and add tests for them. llvm-svn: 111226
2010-08-17 13:54:34 +08:00
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14>
%tmp4 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <8 x i32> <i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
%tmp5 = add <8 x i16> %tmp3, %tmp4
ret <8 x i16> %tmp5
}
[ARM] Add D-sized vtrn/vuzp/vzip tests, and cleanup. NFC. llvm-svn: 240114
2015-06-19 10:15:34 +08:00
define <16 x i16> @vuzpQi16_undef_QQres(<8 x i16>* %A, <8 x i16>* %B) nounwind {
; CHECK-LABEL: vuzpQi16_undef_QQres:
; CHECK: @ BB#0:
; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
; CHECK-NEXT: vuzp.16 q9, q8
; CHECK-NEXT: vst1.16 {d18, d19}, [r0:128]!
; CHECK-NEXT: vst1.64 {d16, d17}, [r0:128]
; CHECK-NEXT: mov pc, lr
%tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i16>, <8 x i16>* %B
%tmp3 = shufflevector <8 x i16> %tmp1, <8 x i16> %tmp2, <16 x i32> <i32 0, i32 undef, i32 4, i32 undef, i32 8, i32 10, i32 12, i32 14, i32 1, i32 3, i32 5, i32 undef, i32 undef, i32 11, i32 13, i32 15>
ret <16 x i16> %tmp3
}