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llvm-project/llvm/test/CodeGen/Mips/tailcall/tail-call-arguments-clobber.ll

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[mips] Disable tail calls temporarily Disable tail calls while the remaining bugs are fixed. Enable only for tests. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24912 llvm-svn: 282487
2016-09-27 21:15:54 +08:00
; RUN: llc -march=mips -mcpu=mips32 -O0 -relocation-model=pic -mips-tail-calls=1 < %s | FileCheck \
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
; RUN: %s -check-prefix=MIPS32
; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n64 \
[mips] Disable tail calls temporarily Disable tail calls while the remaining bugs are fixed. Enable only for tests. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24912 llvm-svn: 282487
2016-09-27 21:15:54 +08:00
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
; RUN: llc -march=mips64 -mcpu=mips64 -O0 -relocation-model=pic -target-abi n32 \
[mips] Disable tail calls temporarily Disable tail calls while the remaining bugs are fixed. Enable only for tests. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24912 llvm-svn: 282487
2016-09-27 21:15:54 +08:00
; RUN: -mips-tail-calls=1 < %s | FileCheck %s -check-prefix=MIPS64
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
; LLVM PR/30197
; Test that the scheduler does not order loads and stores of arguments that
; are passed on the stack such that the arguments of the caller are clobbered
; too early.
; This test is more fragile than I'd like. The -NEXT directives enforce an
; assumption that any GOT related instructions will not appear between the
; loads and stores.
; O32 case: The last two arguments should appear at 16(sp), 20(sp). The order
; of the loads doesn't matter, but they have to become before the
; stores
[mips] Restrict tail call optimization The tail call optimization was being used without proper consideration of ABI requirements for saving and restoring the GP. This patch restricts tail call optimization to functions within the same translation unit. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D24763 llvm-svn: 287505
2016-11-21 05:23:08 +08:00
define internal i32 @func2(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f) {
%1 = add i32 %a, %b
%2 = add i32 %1, %c
%3 = add i32 %2, %d
%4 = add i32 %3, %e
%5 = add i32 %4, %f
ret i32 %5
}
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
define i32 @func1(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f){
[mips][FastISel] Instantiate the MipsFastISel class only for targets that support FastISel. Summary: Instead of instantiating the MipsFastISel class and checking if the target is supported in the overriden methods, we should perform that check before creating the class. This allows us to enable FastISel *only* for targets that truly support it, ie. MIPS32 to MIPS32R5. Reviewers: sdardis Subscribers: ehostunreach, llvm-commits Differential Revision: https://reviews.llvm.org/D24824 llvm-svn: 284475
2016-10-18 21:05:42 +08:00
; MIPS32-LABEL: func1:
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
; MIPS32: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
; MIPS32-NEXT: lw ${{[0-9]+}}, {{[0-9]+}}($sp)
; MIPS32-NEXT: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
; MIPS32-NEXT: sw ${{[0-9]+}}, {{[0-9]+}}($sp)
[mips] Restrict tail call optimization The tail call optimization was being used without proper consideration of ABI requirements for saving and restoring the GP. This patch restricts tail call optimization to functions within the same translation unit. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D24763 llvm-svn: 287505
2016-11-21 05:23:08 +08:00
%retval = tail call i32 @func2(i32 %a, i32 %f, i32 %c, i32 %d, i32 %e, i32 %b)
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
ret i32 %retval
}
; N64, N32 cases: N64 and N32 both pass 8 arguments in registers. The order
; of the loads doesn't matter, but they have to become before the
; stores
[mips] Restrict tail call optimization The tail call optimization was being used without proper consideration of ABI requirements for saving and restoring the GP. This patch restricts tail call optimization to functions within the same translation unit. Reviewers: vkalintiris Differential Revision: https://reviews.llvm.org/D24763 llvm-svn: 287505
2016-11-21 05:23:08 +08:00
define internal i64 @func4(i64 %a, i64 %b, i64 %c, i64 %d, i64 %e,
i64 %f, i64 %g, i64 %h, i64 %i, i64 %j) {
%1 = add i64 %a, %b
%2 = add i64 %1, %c
%3 = add i64 %2, %d
%4 = add i64 %3, %e
%5 = add i64 %4, %f
%6 = add i64 %1, %g
%7 = add i64 %2, %h
%8 = add i64 %3, %i
%9 = add i64 %4, %j
ret i64 %5
}
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
define i64 @func3(i64 %a, i64 %b, i64 %c, i64 %d,
i64 %e, i64 %f, i64 %g, i64 %h,
i64 %i, i64 %j){
[mips][FastISel] Instantiate the MipsFastISel class only for targets that support FastISel. Summary: Instead of instantiating the MipsFastISel class and checking if the target is supported in the overriden methods, we should perform that check before creating the class. This allows us to enable FastISel *only* for targets that truly support it, ie. MIPS32 to MIPS32R5. Reviewers: sdardis Subscribers: ehostunreach, llvm-commits Differential Revision: https://reviews.llvm.org/D24824 llvm-svn: 284475
2016-10-18 21:05:42 +08:00
; MIPS64-LABEL: func3:
[mips] LLVM PR/30197 - Tail call incorrectly clobbers arguments for mips The postRA scheduler performs alias analysis to determine if stores and loads can moved past each other. When a function has more arguments than argument registers for the calling convention used, excess arguments are spilled onto the stack. LLVM by default assumes that argument slots are immutable, unless the function contains a tail call. Without the knowledge of that a function contains a tail call site, stores and loads to fixed stack slots may be re-ordered causing the out-going arguments to clobber the incoming arguments before the incoming arguments are supposed to be dead. Reviewers: vkalintiris Differential Review: https://reviews.llvm.org/D24077 llvm-svn: 282063
2016-09-21 17:43:40 +08:00
; MIPS64: ld ${{[0-9]+}}, {{[0-9]+}}($sp)
; MIPS64-NEXT: ld ${{[0-9]+}}, {{[0-9]+}}($sp)
; MIPS64-NEXT: sd ${{[0-9]+}}, {{[0-9]+}}($sp)
; MIPS64-NEXT: sd ${{[0-9]+}}, {{[0-9]+}}($sp)
%retval = tail call i64 @func4(i64 %a, i64 %j, i64 %c, i64 %d, i64 %e, i64 %f, i64 %g, i64 %h, i64 %i, i64 %b)
ret i64 %retval
}