2021-12-22 02:21:41 +08:00
|
|
|
//===- bolt/Passes/RegReAssign.cpp ----------------------------------------===//
|
2017-11-15 10:20:40 +08:00
|
|
|
//
|
2021-03-16 09:04:18 +08:00
|
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
2017-11-15 10:20:40 +08:00
|
|
|
//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//
|
2021-12-22 02:21:41 +08:00
|
|
|
// This file implements the RegReAssign class.
|
|
|
|
//
|
2017-11-15 10:20:40 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
|
2021-10-09 02:47:10 +08:00
|
|
|
#include "bolt/Passes/RegReAssign.h"
|
|
|
|
#include "bolt/Core/MCPlus.h"
|
|
|
|
#include "bolt/Passes/BinaryFunctionCallGraph.h"
|
|
|
|
#include "bolt/Passes/DataflowAnalysis.h"
|
|
|
|
#include "bolt/Passes/DataflowInfoManager.h"
|
|
|
|
#include "bolt/Utils/Utils.h"
|
2017-11-15 10:20:40 +08:00
|
|
|
#include <numeric>
|
|
|
|
|
|
|
|
#define DEBUG_TYPE "regreassign"
|
|
|
|
|
|
|
|
using namespace llvm;
|
|
|
|
|
|
|
|
namespace opts {
|
|
|
|
extern cl::OptionCategory BoltOptCategory;
|
|
|
|
extern cl::opt<bool> UpdateDebugSections;
|
|
|
|
|
2022-06-06 04:29:49 +08:00
|
|
|
static cl::opt<bool> AggressiveReAssign(
|
|
|
|
"use-aggr-reg-reassign",
|
|
|
|
cl::desc("use register liveness analysis to try to find more opportunities "
|
|
|
|
"for -reg-reassign optimization"),
|
|
|
|
cl::cat(BoltOptCategory));
|
2017-11-15 10:20:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
namespace llvm {
|
|
|
|
namespace bolt {
|
|
|
|
|
2021-10-26 15:06:34 +08:00
|
|
|
void RegReAssign::swap(BinaryFunction &Function, MCPhysReg A, MCPhysReg B) {
|
|
|
|
BinaryContext &BC = Function.getBinaryContext();
|
2018-03-10 01:45:13 +08:00
|
|
|
const BitVector &AliasA = BC.MIB->getAliases(A, false);
|
|
|
|
const BitVector &AliasB = BC.MIB->getAliases(B, false);
|
2017-11-15 10:20:40 +08:00
|
|
|
|
|
|
|
// Regular instructions
|
2021-04-08 15:19:26 +08:00
|
|
|
for (BinaryBasicBlock &BB : Function) {
|
|
|
|
for (MCInst &Inst : BB) {
|
2022-05-12 00:34:10 +08:00
|
|
|
for (MCOperand &Operand : MCPlus::primeOperands(Inst)) {
|
2017-11-15 10:20:40 +08:00
|
|
|
if (!Operand.isReg())
|
|
|
|
continue;
|
|
|
|
|
2021-04-08 15:19:26 +08:00
|
|
|
unsigned Reg = Operand.getReg();
|
2017-11-15 10:20:40 +08:00
|
|
|
if (AliasA.test(Reg)) {
|
2018-03-10 01:45:13 +08:00
|
|
|
Operand.setReg(BC.MIB->getAliasSized(B, BC.MIB->getRegSize(Reg)));
|
2017-11-15 10:20:40 +08:00
|
|
|
--StaticBytesSaved;
|
|
|
|
DynBytesSaved -= BB.getKnownExecutionCount();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
if (!AliasB.test(Reg))
|
|
|
|
continue;
|
2018-03-10 01:45:13 +08:00
|
|
|
Operand.setReg(BC.MIB->getAliasSized(A, BC.MIB->getRegSize(Reg)));
|
2017-11-15 10:20:40 +08:00
|
|
|
++StaticBytesSaved;
|
|
|
|
DynBytesSaved += BB.getKnownExecutionCount();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
// CFI
|
|
|
|
DenseSet<const MCCFIInstruction *> Changed;
|
2021-04-08 15:19:26 +08:00
|
|
|
for (BinaryBasicBlock &BB : Function) {
|
|
|
|
for (MCInst &Inst : BB) {
|
2018-03-10 01:45:13 +08:00
|
|
|
if (!BC.MIB->isCFI(Inst))
|
2017-11-15 10:20:40 +08:00
|
|
|
continue;
|
2020-12-02 08:29:39 +08:00
|
|
|
const MCCFIInstruction *CFI = Function.getCFIFor(Inst);
|
2017-11-15 10:20:40 +08:00
|
|
|
if (Changed.count(CFI))
|
|
|
|
continue;
|
|
|
|
Changed.insert(CFI);
|
|
|
|
|
|
|
|
switch (CFI->getOperation()) {
|
|
|
|
case MCCFIInstruction::OpRegister: {
|
2021-04-08 15:19:26 +08:00
|
|
|
const unsigned CFIReg2 = CFI->getRegister2();
|
2020-12-02 08:29:39 +08:00
|
|
|
const MCPhysReg Reg2 = *BC.MRI->getLLVMRegNum(CFIReg2, /*isEH=*/false);
|
2017-11-15 10:20:40 +08:00
|
|
|
if (AliasA.test(Reg2)) {
|
2020-12-02 08:29:39 +08:00
|
|
|
Function.setCFIFor(
|
|
|
|
Inst, MCCFIInstruction::createRegister(
|
|
|
|
nullptr, CFI->getRegister(),
|
|
|
|
BC.MRI->getDwarfRegNum(
|
|
|
|
BC.MIB->getAliasSized(B, BC.MIB->getRegSize(Reg2)),
|
|
|
|
false)));
|
2017-11-15 10:20:40 +08:00
|
|
|
} else if (AliasB.test(Reg2)) {
|
2020-12-02 08:29:39 +08:00
|
|
|
Function.setCFIFor(
|
|
|
|
Inst, MCCFIInstruction::createRegister(
|
|
|
|
nullptr, CFI->getRegister(),
|
|
|
|
BC.MRI->getDwarfRegNum(
|
|
|
|
BC.MIB->getAliasSized(A, BC.MIB->getRegSize(Reg2)),
|
|
|
|
false)));
|
2017-11-15 10:20:40 +08:00
|
|
|
}
|
|
|
|
}
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_FALLTHROUGH;
|
2017-11-15 10:20:40 +08:00
|
|
|
case MCCFIInstruction::OpUndefined:
|
|
|
|
case MCCFIInstruction::OpDefCfa:
|
|
|
|
case MCCFIInstruction::OpOffset:
|
|
|
|
case MCCFIInstruction::OpRestore:
|
|
|
|
case MCCFIInstruction::OpSameValue:
|
|
|
|
case MCCFIInstruction::OpDefCfaRegister:
|
|
|
|
case MCCFIInstruction::OpRelOffset:
|
2020-12-02 08:29:39 +08:00
|
|
|
case MCCFIInstruction::OpEscape: {
|
|
|
|
unsigned CFIReg;
|
|
|
|
if (CFI->getOperation() != MCCFIInstruction::OpEscape) {
|
|
|
|
CFIReg = CFI->getRegister();
|
|
|
|
} else {
|
|
|
|
Optional<uint8_t> Reg =
|
|
|
|
readDWARFExpressionTargetReg(CFI->getValues());
|
|
|
|
// Handle DW_CFA_def_cfa_expression
|
|
|
|
if (!Reg)
|
|
|
|
break;
|
|
|
|
CFIReg = *Reg;
|
|
|
|
}
|
|
|
|
const MCPhysReg Reg = *BC.MRI->getLLVMRegNum(CFIReg, /*isEH=*/false);
|
2021-12-29 08:36:17 +08:00
|
|
|
if (AliasA.test(Reg))
|
2020-12-02 08:29:39 +08:00
|
|
|
Function.mutateCFIRegisterFor(
|
|
|
|
Inst,
|
|
|
|
BC.MRI->getDwarfRegNum(
|
|
|
|
BC.MIB->getAliasSized(B, BC.MIB->getRegSize(Reg)), false));
|
2021-12-29 08:36:17 +08:00
|
|
|
else if (AliasB.test(Reg))
|
2020-12-02 08:29:39 +08:00
|
|
|
Function.mutateCFIRegisterFor(
|
|
|
|
Inst,
|
|
|
|
BC.MRI->getDwarfRegNum(
|
|
|
|
BC.MIB->getAliasSized(A, BC.MIB->getRegSize(Reg)), false));
|
2017-11-15 10:20:40 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-26 15:06:34 +08:00
|
|
|
void RegReAssign::rankRegisters(BinaryFunction &Function) {
|
|
|
|
BinaryContext &BC = Function.getBinaryContext();
|
2017-11-15 10:20:40 +08:00
|
|
|
std::fill(RegScore.begin(), RegScore.end(), 0);
|
|
|
|
std::fill(RankedRegs.begin(), RankedRegs.end(), 0);
|
|
|
|
|
2021-04-08 15:19:26 +08:00
|
|
|
for (BinaryBasicBlock &BB : Function) {
|
|
|
|
for (MCInst &Inst : BB) {
|
2018-03-10 01:45:13 +08:00
|
|
|
const bool CannotUseREX = BC.MIB->cannotUseREX(Inst);
|
2021-04-08 15:19:26 +08:00
|
|
|
const MCInstrDesc &Desc = BC.MII->get(Inst.getOpcode());
|
2017-11-15 10:20:40 +08:00
|
|
|
|
|
|
|
// Disallow substituitions involving regs in implicit uses lists
|
2021-04-08 15:19:26 +08:00
|
|
|
const MCPhysReg *ImplicitUses = Desc.getImplicitUses();
|
2017-11-15 10:20:40 +08:00
|
|
|
while (ImplicitUses && *ImplicitUses) {
|
|
|
|
const size_t RegEC =
|
2018-03-10 01:45:13 +08:00
|
|
|
BC.MIB->getAliases(*ImplicitUses, false).find_first();
|
2017-11-15 10:20:40 +08:00
|
|
|
RegScore[RegEC] =
|
|
|
|
std::numeric_limits<decltype(RegScore)::value_type>::min();
|
|
|
|
++ImplicitUses;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Disallow substituitions involving regs in implicit defs lists
|
2021-04-08 15:19:26 +08:00
|
|
|
const MCPhysReg *ImplicitDefs = Desc.getImplicitDefs();
|
2017-11-15 10:20:40 +08:00
|
|
|
while (ImplicitDefs && *ImplicitDefs) {
|
|
|
|
const size_t RegEC =
|
2018-03-10 01:45:13 +08:00
|
|
|
BC.MIB->getAliases(*ImplicitDefs, false).find_first();
|
2017-11-15 10:20:40 +08:00
|
|
|
RegScore[RegEC] =
|
|
|
|
std::numeric_limits<decltype(RegScore)::value_type>::min();
|
|
|
|
++ImplicitDefs;
|
|
|
|
}
|
|
|
|
|
[BOLT][Refactoring] Isolate changes to MC layer
Summary:
Changes that we made to MCInst, MCOperand, MCExpr, etc. are now all
moved into tools/llvm-bolt. That required a change to the way we handle
annotations and any extra operands for MCInst.
Any MCPlus information is now attached via an extra operand of type
MCInst with an opcode ANNOTATION_LABEL. Since this operand is MCInst, we
attach extra info as operands to this instruction. For first-level
annotations use functions to access the information, such as
getConditionalTailCall() or getEHInfo(), etc. For the rest, optional or
second-class annotations, use a general named-annotation interface such
as getAnnotationAs<uint64_t>(Inst, "Count").
I did a test on HHVM binary, and a memory consumption went down a little
bit while the runtime remained the same.
(cherry picked from FBD7405412)
2018-03-20 09:32:12 +08:00
|
|
|
for (int I = 0, E = MCPlus::getNumPrimeOperands(Inst); I != E; ++I) {
|
2021-04-08 15:19:26 +08:00
|
|
|
const MCOperand &Operand = Inst.getOperand(I);
|
2017-11-15 10:20:40 +08:00
|
|
|
if (!Operand.isReg())
|
|
|
|
continue;
|
|
|
|
|
|
|
|
if (Desc.getOperandConstraint(I, MCOI::TIED_TO) != -1)
|
|
|
|
continue;
|
|
|
|
|
2021-04-08 15:19:26 +08:00
|
|
|
unsigned Reg = Operand.getReg();
|
2018-03-10 01:45:13 +08:00
|
|
|
size_t RegEC = BC.MIB->getAliases(Reg, false).find_first();
|
2017-11-15 10:20:40 +08:00
|
|
|
if (RegEC == 0)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
// Disallow substituitions involving regs in instrs that cannot use REX
|
|
|
|
if (CannotUseREX) {
|
|
|
|
RegScore[RegEC] =
|
|
|
|
std::numeric_limits<decltype(RegScore)::value_type>::min();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Unsupported substitution, cannot swap BH with R* regs, bail
|
2018-03-10 01:45:13 +08:00
|
|
|
if (BC.MIB->isUpper8BitReg(Reg) && ClassicCSR.test(Reg)) {
|
2017-11-15 10:20:40 +08:00
|
|
|
RegScore[RegEC] =
|
|
|
|
std::numeric_limits<decltype(RegScore)::value_type>::min();
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
RegScore[RegEC] += BB.getKnownExecutionCount();
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
std::iota(RankedRegs.begin(), RankedRegs.end(), 0); // 0, 1, 2, 3...
|
|
|
|
std::sort(RankedRegs.begin(), RankedRegs.end(),
|
|
|
|
[&](size_t A, size_t B) { return RegScore[A] > RegScore[B]; });
|
|
|
|
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG({
|
2021-04-08 15:19:26 +08:00
|
|
|
for (size_t Reg : RankedRegs) {
|
2017-11-15 10:20:40 +08:00
|
|
|
if (RegScore[Reg] == 0)
|
|
|
|
continue;
|
|
|
|
dbgs() << Reg << " ";
|
|
|
|
if (RegScore[Reg] > 0)
|
|
|
|
dbgs() << BC.MRI->getName(Reg) << ": " << RegScore[Reg] << "\n";
|
|
|
|
else
|
|
|
|
dbgs() << BC.MRI->getName(Reg) << ": (blacklisted)\n";
|
|
|
|
}
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
2021-10-26 15:06:34 +08:00
|
|
|
void RegReAssign::aggressivePassOverFunction(BinaryFunction &Function) {
|
|
|
|
BinaryContext &BC = Function.getBinaryContext();
|
|
|
|
rankRegisters(Function);
|
2017-11-15 10:20:40 +08:00
|
|
|
|
|
|
|
// Bail early if our registers are all black listed, before running expensive
|
|
|
|
// analysis passes
|
|
|
|
bool Bail = true;
|
|
|
|
int64_t LowScoreClassic = std::numeric_limits<int64_t>::max();
|
2022-05-12 07:23:27 +08:00
|
|
|
for (int J : ClassicRegs.set_bits()) {
|
2017-11-15 10:20:40 +08:00
|
|
|
if (RegScore[J] <= 0)
|
|
|
|
continue;
|
|
|
|
Bail = false;
|
|
|
|
if (RegScore[J] < LowScoreClassic)
|
|
|
|
LowScoreClassic = RegScore[J];
|
|
|
|
}
|
|
|
|
if (Bail)
|
|
|
|
return;
|
|
|
|
BitVector Extended = ClassicRegs;
|
|
|
|
Extended.flip();
|
|
|
|
Extended &= GPRegs;
|
|
|
|
Bail = true;
|
|
|
|
int64_t HighScoreExtended = 0;
|
2022-05-12 07:23:27 +08:00
|
|
|
for (int J : Extended.set_bits()) {
|
2017-11-15 10:20:40 +08:00
|
|
|
if (RegScore[J] <= 0)
|
|
|
|
continue;
|
|
|
|
Bail = false;
|
|
|
|
if (RegScore[J] > HighScoreExtended)
|
|
|
|
HighScoreExtended = RegScore[J];
|
|
|
|
}
|
|
|
|
// Also bail early if there is no profitable substitution even if we assume
|
|
|
|
// all registers can be exchanged
|
|
|
|
if (Bail || (LowScoreClassic << 1) >= HighScoreExtended)
|
|
|
|
return;
|
|
|
|
|
|
|
|
// -- expensive pass -- determine all regs alive during func start
|
2021-10-26 15:06:34 +08:00
|
|
|
DataflowInfoManager Info(Function, RA.get(), nullptr);
|
2021-04-08 15:19:26 +08:00
|
|
|
BitVector AliveAtStart = *Info.getLivenessAnalysis().getStateAt(
|
2017-11-15 10:20:40 +08:00
|
|
|
ProgramPoint::getFirstPointAt(*Function.begin()));
|
2021-12-29 08:36:17 +08:00
|
|
|
for (BinaryBasicBlock &BB : Function)
|
2017-11-15 10:20:40 +08:00
|
|
|
if (BB.pred_size() == 0)
|
|
|
|
AliveAtStart |= *Info.getLivenessAnalysis().getStateAt(
|
|
|
|
ProgramPoint::getFirstPointAt(BB));
|
2021-12-29 08:36:17 +08:00
|
|
|
|
2017-11-15 10:20:40 +08:00
|
|
|
// Mark frame pointer alive because of CFI
|
2018-03-10 01:45:13 +08:00
|
|
|
AliveAtStart |= BC.MIB->getAliases(BC.MIB->getFramePointer(), false);
|
2017-11-15 10:20:40 +08:00
|
|
|
// Never touch return registers
|
2018-03-10 01:45:13 +08:00
|
|
|
BC.MIB->getDefaultLiveOut(AliveAtStart);
|
2017-11-15 10:20:40 +08:00
|
|
|
|
|
|
|
// Try swapping more profitable options first
|
|
|
|
auto Begin = RankedRegs.begin();
|
|
|
|
auto End = std::prev(RankedRegs.end());
|
|
|
|
while (Begin != End) {
|
|
|
|
MCPhysReg ClassicReg = *End;
|
|
|
|
if (!ClassicRegs[ClassicReg] || RegScore[ClassicReg] <= 0) {
|
|
|
|
--End;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
MCPhysReg ExtReg = *Begin;
|
|
|
|
if (!Extended[ExtReg] || RegScore[ExtReg] <= 0) {
|
|
|
|
++Begin;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (RegScore[ClassicReg] << 1 >= RegScore[ExtReg]) {
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG(dbgs() << " Ending at " << BC.MRI->getName(ClassicReg)
|
|
|
|
<< " with " << BC.MRI->getName(ExtReg)
|
|
|
|
<< " because exchange is not profitable\n");
|
2017-11-15 10:20:40 +08:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
BitVector AnyAliasAlive = AliveAtStart;
|
2018-03-10 01:45:13 +08:00
|
|
|
AnyAliasAlive &= BC.MIB->getAliases(ClassicReg);
|
2017-11-15 10:20:40 +08:00
|
|
|
if (AnyAliasAlive.any()) {
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg)
|
|
|
|
<< " with " << BC.MRI->getName(ExtReg)
|
|
|
|
<< " because classic reg is alive\n");
|
2017-11-15 10:20:40 +08:00
|
|
|
--End;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
AnyAliasAlive = AliveAtStart;
|
2018-03-10 01:45:13 +08:00
|
|
|
AnyAliasAlive &= BC.MIB->getAliases(ExtReg);
|
2017-11-15 10:20:40 +08:00
|
|
|
if (AnyAliasAlive.any()) {
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG(dbgs() << " Bailed on " << BC.MRI->getName(ClassicReg)
|
|
|
|
<< " with " << BC.MRI->getName(ExtReg)
|
|
|
|
<< " because extended reg is alive\n");
|
2017-11-15 10:20:40 +08:00
|
|
|
++Begin;
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Opportunity detected. Swap.
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\n ** Swapping " << BC.MRI->getName(ClassicReg)
|
|
|
|
<< " with " << BC.MRI->getName(ExtReg) << "\n\n");
|
2021-10-26 15:06:34 +08:00
|
|
|
swap(Function, ClassicReg, ExtReg);
|
2017-11-15 10:20:40 +08:00
|
|
|
FuncsChanged.insert(&Function);
|
|
|
|
++Begin;
|
|
|
|
if (Begin == End)
|
|
|
|
break;
|
|
|
|
--End;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2021-10-26 15:06:34 +08:00
|
|
|
bool RegReAssign::conservativePassOverFunction(BinaryFunction &Function) {
|
|
|
|
BinaryContext &BC = Function.getBinaryContext();
|
|
|
|
rankRegisters(Function);
|
2017-11-15 10:20:40 +08:00
|
|
|
|
|
|
|
// Try swapping R12, R13, R14 or R15 with RBX (we work with all callee-saved
|
|
|
|
// regs except RBP)
|
|
|
|
MCPhysReg Candidate = 0;
|
2022-05-12 07:23:27 +08:00
|
|
|
for (int J : ExtendedCSR.set_bits())
|
2017-11-15 10:20:40 +08:00
|
|
|
if (RegScore[J] > RegScore[Candidate])
|
|
|
|
Candidate = J;
|
|
|
|
|
|
|
|
if (!Candidate || RegScore[Candidate] < 0)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
// Check if our classic callee-saved reg (RBX is the only one) has lower
|
|
|
|
// score / utilization rate
|
|
|
|
MCPhysReg RBX = 0;
|
2022-05-12 07:23:27 +08:00
|
|
|
for (int I : ClassicCSR.set_bits()) {
|
2021-04-08 15:19:26 +08:00
|
|
|
int64_t ScoreRBX = RegScore[I];
|
2017-11-15 10:20:40 +08:00
|
|
|
if (ScoreRBX <= 0)
|
|
|
|
continue;
|
|
|
|
|
2021-12-29 08:36:17 +08:00
|
|
|
if (RegScore[Candidate] > (ScoreRBX + 10))
|
2017-11-15 10:20:40 +08:00
|
|
|
RBX = I;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!RBX)
|
|
|
|
return false;
|
|
|
|
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\n ** Swapping " << BC.MRI->getName(RBX) << " with "
|
|
|
|
<< BC.MRI->getName(Candidate) << "\n\n");
|
2022-05-14 02:56:45 +08:00
|
|
|
(void)BC;
|
2021-10-26 15:06:34 +08:00
|
|
|
swap(Function, RBX, Candidate);
|
2017-11-15 10:20:40 +08:00
|
|
|
FuncsChanged.insert(&Function);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void RegReAssign::setupAggressivePass(BinaryContext &BC,
|
2021-12-15 08:52:51 +08:00
|
|
|
std::map<uint64_t, BinaryFunction> &BFs) {
|
2017-11-15 10:20:40 +08:00
|
|
|
setupConservativePass(BC, BFs);
|
2019-04-04 06:52:01 +08:00
|
|
|
CG.reset(new BinaryFunctionCallGraph(buildCallGraph(BC)));
|
2018-06-12 04:18:44 +08:00
|
|
|
RA.reset(new RegAnalysis(BC, &BFs, &*CG));
|
2017-11-15 10:20:40 +08:00
|
|
|
|
|
|
|
GPRegs = BitVector(BC.MRI->getNumRegs(), false);
|
2018-03-10 01:45:13 +08:00
|
|
|
BC.MIB->getGPRegs(GPRegs);
|
2017-11-15 10:20:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void RegReAssign::setupConservativePass(
|
|
|
|
BinaryContext &BC, std::map<uint64_t, BinaryFunction> &BFs) {
|
|
|
|
// Set up constant bitvectors used throughout this analysis
|
|
|
|
ClassicRegs = BitVector(BC.MRI->getNumRegs(), false);
|
|
|
|
CalleeSaved = BitVector(BC.MRI->getNumRegs(), false);
|
|
|
|
ClassicCSR = BitVector(BC.MRI->getNumRegs(), false);
|
|
|
|
ExtendedCSR = BitVector(BC.MRI->getNumRegs(), false);
|
|
|
|
// Never consider the frame pointer
|
2018-03-10 01:45:13 +08:00
|
|
|
BC.MIB->getClassicGPRegs(ClassicRegs);
|
2017-11-15 10:20:40 +08:00
|
|
|
ClassicRegs.flip();
|
2018-03-10 01:45:13 +08:00
|
|
|
ClassicRegs |= BC.MIB->getAliases(BC.MIB->getFramePointer(), false);
|
2017-11-15 10:20:40 +08:00
|
|
|
ClassicRegs.flip();
|
2018-03-10 01:45:13 +08:00
|
|
|
BC.MIB->getCalleeSavedRegs(CalleeSaved);
|
2017-11-15 10:20:40 +08:00
|
|
|
ClassicCSR |= ClassicRegs;
|
|
|
|
ClassicCSR &= CalleeSaved;
|
2018-03-10 01:45:13 +08:00
|
|
|
BC.MIB->getClassicGPRegs(ClassicRegs);
|
2017-11-15 10:20:40 +08:00
|
|
|
ExtendedCSR |= ClassicRegs;
|
|
|
|
ExtendedCSR.flip();
|
|
|
|
ExtendedCSR &= CalleeSaved;
|
|
|
|
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG({
|
2017-11-15 10:20:40 +08:00
|
|
|
RegStatePrinter P(BC);
|
|
|
|
dbgs() << "Starting register reassignment\nClassicRegs: ";
|
|
|
|
P.print(dbgs(), ClassicRegs);
|
|
|
|
dbgs() << "\nCalleeSaved: ";
|
|
|
|
P.print(dbgs(), CalleeSaved);
|
|
|
|
dbgs() << "\nClassicCSR: ";
|
|
|
|
P.print(dbgs(), ClassicCSR);
|
|
|
|
dbgs() << "\nExtendedCSR: ";
|
|
|
|
P.print(dbgs(), ExtendedCSR);
|
|
|
|
dbgs() << "\n";
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
2019-04-04 06:52:01 +08:00
|
|
|
void RegReAssign::runOnFunctions(BinaryContext &BC) {
|
2017-11-15 10:20:40 +08:00
|
|
|
RegScore = std::vector<int64_t>(BC.MRI->getNumRegs(), 0);
|
|
|
|
RankedRegs = std::vector<size_t>(BC.MRI->getNumRegs(), 0);
|
|
|
|
|
|
|
|
if (opts::AggressiveReAssign)
|
2019-04-04 06:52:01 +08:00
|
|
|
setupAggressivePass(BC, BC.getBinaryFunctions());
|
2017-11-15 10:20:40 +08:00
|
|
|
else
|
2019-04-04 06:52:01 +08:00
|
|
|
setupConservativePass(BC, BC.getBinaryFunctions());
|
2017-11-15 10:20:40 +08:00
|
|
|
|
2019-04-04 06:52:01 +08:00
|
|
|
for (auto &I : BC.getBinaryFunctions()) {
|
2021-04-08 15:19:26 +08:00
|
|
|
BinaryFunction &Function = I.second;
|
2017-11-15 10:20:40 +08:00
|
|
|
|
2020-05-04 04:54:45 +08:00
|
|
|
if (!Function.isSimple() || Function.isIgnored())
|
2017-11-15 10:20:40 +08:00
|
|
|
continue;
|
|
|
|
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "====================================\n");
|
|
|
|
LLVM_DEBUG(dbgs() << " - " << Function.getPrintName() << "\n");
|
2021-10-26 15:06:34 +08:00
|
|
|
if (!conservativePassOverFunction(Function) && opts::AggressiveReAssign) {
|
|
|
|
aggressivePassOverFunction(Function);
|
2020-12-02 08:29:39 +08:00
|
|
|
LLVM_DEBUG({
|
2021-12-29 08:36:17 +08:00
|
|
|
if (FuncsChanged.count(&Function))
|
2017-11-15 10:20:40 +08:00
|
|
|
dbgs() << "Aggressive pass successful on " << Function.getPrintName()
|
|
|
|
<< "\n";
|
|
|
|
});
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (FuncsChanged.empty()) {
|
|
|
|
outs() << "BOLT-INFO: Reg Reassignment Pass: no changes were made.\n";
|
|
|
|
return;
|
|
|
|
}
|
2021-12-29 08:36:17 +08:00
|
|
|
if (opts::UpdateDebugSections)
|
2017-11-15 10:20:40 +08:00
|
|
|
outs() << "BOLT-WARNING: You used -reg-reassign and -update-debug-sections."
|
|
|
|
<< " Some registers were changed but associated AT_LOCATION for "
|
|
|
|
<< "impacted variables were NOT updated! This operation is "
|
2018-06-15 05:27:20 +08:00
|
|
|
<< "currently unsupported by BOLT.\n";
|
2017-11-15 10:20:40 +08:00
|
|
|
outs() << "BOLT-INFO: Reg Reassignment Pass Stats:\n";
|
|
|
|
outs() << "\t " << FuncsChanged.size() << " functions affected.\n";
|
|
|
|
outs() << "\t " << StaticBytesSaved << " static bytes saved.\n";
|
|
|
|
outs() << "\t " << DynBytesSaved << " dynamic bytes saved.\n";
|
|
|
|
}
|
|
|
|
|
2021-12-15 08:52:51 +08:00
|
|
|
} // namespace bolt
|
|
|
|
} // namespace llvm
|