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llvm-project/llvm/test/CodeGen/ARM/fp16-litpool-thumb.mir

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[ARM] Allow half types in ConstantPool Change ARMConstantIslandPass to: - accept f16 literals as litpool entries, - if the litpool needs to be inserted in the middle of a big block, then we need to 4-byte align the next instruction in ARM mode. Differential Revision: https://reviews.llvm.org/D42784 llvm-svn: 325012
2018-02-13 23:34:09 +08:00
# RUN: llc -mtriple=thumbv7-none-eabi -run-pass=arm-cp-islands %s -o - | FileCheck %s
Recommit: [ARM] f16 constant pool fix This recommits r325754; the modified and failing test case actually didn't need any modifications. llvm-svn: 325765
2018-02-22 18:43:57 +08:00
#
# This checks alignment of a new block when a big basic block is split up.
#
[ARM] Allow half types in ConstantPool Change ARMConstantIslandPass to: - accept f16 literals as litpool entries, - if the litpool needs to be inserted in the middle of a big block, then we need to 4-byte align the next instruction in ARM mode. Differential Revision: https://reviews.llvm.org/D42784 llvm-svn: 325012
2018-02-13 23:34:09 +08:00
--- |
; ModuleID = '<stdin>'
source_filename = "<stdin>"
target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
target triple = "thumbv7-arm--eabi"
declare i32 @llvm.arm.space(i32, i32) #0
define dso_local i32 @THUMB(i32 %A.coerce) local_unnamed_addr #1 {
entry:
%F = alloca float, align 4
%S = alloca half, align 2
%tmp.0.extract.trunc = trunc i32 %A.coerce to i16
%0 = bitcast i16 %tmp.0.extract.trunc to half
store volatile float 4.200000e+01, float* %F, align 4
store volatile half 0xH3C00, half* %S, align 2
%S.0.S.0.142 = load volatile half, half* %S, align 2
%1 = call i32 @llvm.arm.space(i32 1230, i32 undef)
%add42 = fadd half %S.0.S.0.142, 0xH2E66
store volatile half %add42, half* %S, align 2
%2 = call i32 @llvm.arm.space(i32 1330, i32 undef)
%S.0.S.0.119 = load volatile half, half* %S, align 2
%3 = bitcast half %add42 to i16
%tmp87.0.insert.ext = zext i16 %3 to i32
ret i32 %tmp87.0.insert.ext
}
attributes #0 = { nounwind }
attributes #1 = { minsize nounwind optsize "target-features"="+crc,+crypto,+dsp,+fp-armv8,+fullfp16,+hwdiv,+hwdiv-arm,+neon,+ras,+strict-align,+thumb-mode" }
...
---
name: THUMB
alignment: 1
tracksRegLiveness: true
frameInfo:
stackSize: 8
maxAlignment: 4
maxCallFrameSize: 0
stack:
Describe stack-id as an enum This patch changes MIR stack-id from an integer to an enum, and adds printing/parsing support for this in MIR files. The default stack-id '0' is now renamed to 'default'. This should make MIR tests that have stack objects with different stack-ids more descriptive. It also clarifies code operating on StackID. Reviewers: arsenm, thegameg, qcolombet Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D60137 llvm-svn: 363533
2019-06-17 17:13:29 +08:00
- { id: 0, name: F, offset: -4, size: 4, alignment: 4, stack-id: default, local-offset: -4 }
- { id: 1, name: S, offset: -6, size: 2, alignment: 2, stack-id: default, local-offset: -6 }
[ARM] Allow half types in ConstantPool Change ARMConstantIslandPass to: - accept f16 literals as litpool entries, - if the litpool needs to be inserted in the middle of a big block, then we need to 4-byte align the next instruction in ARM mode. Differential Revision: https://reviews.llvm.org/D42784 llvm-svn: 325012
2018-02-13 23:34:09 +08:00
constants:
- id: 0
value: i32 1109917696
alignment: 4
- id: 1
value: half 0xH2E66
alignment: 2
#CHECK: t2B %[[BB3:bb.[0-9]]]
[LLVM][Alignment] Make functions using log of alignment explicit Summary: This patch renames functions that takes or returns alignment as log2, this patch will help with the transition to llvm::Align. The renaming makes it explicit that we deal with log(alignment) instead of a power of two alignment. A few renames uncovered dubious assignments: - `MirParser`/`MirPrinter` was expecting powers of two but `MachineFunction` and `MachineBasicBlock` were using deal with log2(align). This patch fixes it and updates the documentation. - `MachineBlockPlacement` exposes two flags (`align-all-blocks` and `align-all-nofallthru-blocks`) supposedly interpreted as power of two alignments, internally these values are interpreted as log2(align). This patch updates the documentation, - `MachineFunctionexposes` exposes `align-all-functions` also interpreted as power of two alignment, internally this value is interpreted as log2(align). This patch updates the documentation, Reviewers: lattner, thegameg, courbet Subscribers: dschuff, arsenm, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, PkmX, jocewei, jsji, Jim, s.egerton, llvm-commits, courbet Tags: #llvm Differential Revision: https://reviews.llvm.org/D65945 llvm-svn: 371045
2019-09-05 18:00:22 +08:00
#CHECK: bb.{{.}} (align 4):
[ARM] Allow half types in ConstantPool Change ARMConstantIslandPass to: - accept f16 literals as litpool entries, - if the litpool needs to be inserted in the middle of a big block, then we need to 4-byte align the next instruction in ARM mode. Differential Revision: https://reviews.llvm.org/D42784 llvm-svn: 325012
2018-02-13 23:34:09 +08:00
#CHECK: successors:
#CHECK: CONSTPOOL_ENTRY 2, %const.{{.}}, 4
[LLVM][Alignment] Make functions using log of alignment explicit Summary: This patch renames functions that takes or returns alignment as log2, this patch will help with the transition to llvm::Align. The renaming makes it explicit that we deal with log(alignment) instead of a power of two alignment. A few renames uncovered dubious assignments: - `MirParser`/`MirPrinter` was expecting powers of two but `MachineFunction` and `MachineBasicBlock` were using deal with log2(align). This patch fixes it and updates the documentation. - `MachineBlockPlacement` exposes two flags (`align-all-blocks` and `align-all-nofallthru-blocks`) supposedly interpreted as power of two alignments, internally these values are interpreted as log2(align). This patch updates the documentation, - `MachineFunctionexposes` exposes `align-all-functions` also interpreted as power of two alignment, internally this value is interpreted as log2(align). This patch updates the documentation, Reviewers: lattner, thegameg, courbet Subscribers: dschuff, arsenm, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, PkmX, jocewei, jsji, Jim, s.egerton, llvm-commits, courbet Tags: #llvm Differential Revision: https://reviews.llvm.org/D65945 llvm-svn: 371045
2019-09-05 18:00:22 +08:00
#CHECK: bb.{{.}} (align 2):
[ARM] Allow half types in ConstantPool Change ARMConstantIslandPass to: - accept f16 literals as litpool entries, - if the litpool needs to be inserted in the middle of a big block, then we need to 4-byte align the next instruction in ARM mode. Differential Revision: https://reviews.llvm.org/D42784 llvm-svn: 325012
2018-02-13 23:34:09 +08:00
#CHECK: successors:
#CHECK: CONSTPOOL_ENTRY 3, %const.{{.}}, 2
[LLVM][Alignment] Make functions using log of alignment explicit Summary: This patch renames functions that takes or returns alignment as log2, this patch will help with the transition to llvm::Align. The renaming makes it explicit that we deal with log(alignment) instead of a power of two alignment. A few renames uncovered dubious assignments: - `MirParser`/`MirPrinter` was expecting powers of two but `MachineFunction` and `MachineBasicBlock` were using deal with log2(align). This patch fixes it and updates the documentation. - `MachineBlockPlacement` exposes two flags (`align-all-blocks` and `align-all-nofallthru-blocks`) supposedly interpreted as power of two alignments, internally these values are interpreted as log2(align). This patch updates the documentation, - `MachineFunctionexposes` exposes `align-all-functions` also interpreted as power of two alignment, internally this value is interpreted as log2(align). This patch updates the documentation, Reviewers: lattner, thegameg, courbet Subscribers: dschuff, arsenm, jyknight, dylanmckay, sdardis, nemanjai, jvesely, nhaehnle, javed.absar, hiraditya, kbarton, fedor.sergeev, asb, rbar, johnrusso, simoncook, apazos, sabuasal, niosHD, jrtc27, MaskRay, zzheng, edward-jones, atanasyan, rogfer01, MartinMosbeck, brucehoult, the_o, dexonsmith, PkmX, jocewei, jsji, Jim, s.egerton, llvm-commits, courbet Tags: #llvm Differential Revision: https://reviews.llvm.org/D65945 llvm-svn: 371045
2019-09-05 18:00:22 +08:00
#CHECK: [[BB3]].entry (align 2):
[ARM] Allow half types in ConstantPool Change ARMConstantIslandPass to: - accept f16 literals as litpool entries, - if the litpool needs to be inserted in the middle of a big block, then we need to 4-byte align the next instruction in ARM mode. Differential Revision: https://reviews.llvm.org/D42784 llvm-svn: 325012
2018-02-13 23:34:09 +08:00
body: |
bb.0.entry:
$sp = frame-setup tSUBspi $sp, 2, 14, $noreg
frame-setup CFI_INSTRUCTION def_cfa_offset 8
renamable $r0 = tLDRpci %const.0, 14, $noreg :: (load 4 from constant-pool)
renamable $s0 = FCONSTH 112, 14, $noreg
tSTRspi killed renamable $r0, $sp, 1, 14, $noreg :: (volatile store 4 into %ir.F)
VSTRH killed renamable $s0, $sp, 1, 14, $noreg :: (volatile store 2 into %ir.S)
renamable $s2 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load 2 from %ir.S)
renamable $s0 = VLDRH %const.1, 0, 14, $noreg :: (load 2 from constant-pool)
dead renamable $r0 = SPACE 1230, undef renamable $r0
renamable $s0 = VADDH killed renamable $s2, killed renamable $s0, 14, $noreg
VSTRH renamable $s0, $sp, 1, 14, $noreg :: (volatile store 2 into %ir.S)
renamable $r0 = VMOVRH killed renamable $s0, 14, $noreg
dead renamable $r1 = SPACE 1330, undef renamable $r0
dead renamable $s0 = VLDRH $sp, 1, 14, $noreg :: (volatile dereferenceable load 2 from %ir.S)
$sp = tADDspi $sp, 2, 14, $noreg
tBX_RET 14, $noreg, implicit killed $r0
...