2016-10-12 21:44:24 +08:00
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -O0 | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK_O0
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; RUN: llc < %s -mtriple=arm-eabi -mattr=+v4t -O1 | FileCheck %s -check-prefix=CHECK -check-prefix=CHECK_O1
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; In /O0, the addition must not be eliminated. This happens when the load
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; and store are folded by the DAGCombiner. In /O1 and above, the optimization
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; must be executed.
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; CHECK-LABEL: {{^}}main
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; CHECK: mov [[TMP:r[0-9]+]], #0
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; CHECK-NEXT: str [[TMP]], [sp, #4]
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Elide stores which are overwritten without being observed.
Summary:
In SelectionDAG, when a store is immediately chained to another store
to the same address, elide the first store as it has no observable
effects. This is causes small improvements dealing with intrinsics
lowered to stores.
Test notes:
* Many testcases overwrite store addresses multiple times and needed
minor changes, mainly making stores volatile to prevent the
optimization from optimizing the test away.
* Many X86 test cases optimized out instructions associated with
associated with va_start.
* Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has
dependencies to check and can probably be removed and potentially
replaced with another test.
Reviewers: rnk, john.brawn
Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits
Differential Revision: https://reviews.llvm.org/D33206
llvm-svn: 303198
2017-05-17 03:43:56 +08:00
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; CHECK_O0: str [[TMP]], [sp]
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2016-10-12 21:44:24 +08:00
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; CHECK_O0: ldr [[TMP:r[0-9]+]], [sp]
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; CHECK_O0-NEXT: add [[TMP]], [[TMP]], #2
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; CHECK_O1-NOT: ldr [[TMP:r[0-9]+]], [sp]
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; CHECK_O1-NOT: add [[TMP]], [[TMP]], #2
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define i32 @main() {
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bb:
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%tmp = alloca i32, align 4
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%tmp1 = alloca i32, align 4
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store i32 0, i32* %tmp, align 4
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store i32 0, i32* %tmp1, align 4
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%tmp2 = load i32, i32* %tmp1, align 4
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%tmp3 = add nsw i32 %tmp2, 2
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store i32 %tmp3, i32* %tmp1, align 4
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%tmp4 = load i32, i32* %tmp1, align 4
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%tmp5 = icmp eq i32 %tmp4, 2
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br i1 %tmp5, label %bb6, label %bb7
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bb6: ; preds = %bb
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store i32 0, i32* %tmp, align 4
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br label %bb8
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bb7: ; preds = %bb
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store i32 5, i32* %tmp, align 4
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br label %bb8
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bb8: ; preds = %bb7, %bb6
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%tmp9 = load i32, i32* %tmp, align 4
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ret i32 %tmp9
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}
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