2013-08-24 04:46:35 +08:00
|
|
|
; RUN: llc < %s -march=x86 -mattr=+sse4.2 | FileCheck %s
|
2008-12-19 04:05:58 +08:00
|
|
|
|
|
|
|
; widening shuffle v3float and then a add
|
|
|
|
define void @shuf(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
|
|
|
|
entry:
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: shuf:
|
Change handling of illegal vector types to widen when possible instead of
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This
affects two places in the code: handling cross block values and handling
function return and arguments. Since vectors are already widened by
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.
For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
br label %BB
BB:
%D = fadd <2 x float> %C, %C
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
}
Now compiles into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
addps %xmm0, %xmm0
ret
previously it compiled into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
pshufd $1, %xmm0, %xmm1
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm1, %xmm0
addps %xmm0, %xmm0
ret
This implements rdar://8230384
llvm-svn: 112101
2010-08-26 06:49:25 +08:00
|
|
|
; CHECK: extractps
|
2010-06-04 09:20:10 +08:00
|
|
|
; CHECK: extractps
|
2008-12-19 04:05:58 +08:00
|
|
|
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 1, i32 2>
|
2010-01-06 01:55:26 +08:00
|
|
|
%val = fadd <3 x float> %x, %src2
|
2008-12-19 04:05:58 +08:00
|
|
|
store <3 x float> %val, <3 x float>* %dst.addr
|
|
|
|
ret void
|
2012-01-18 05:44:01 +08:00
|
|
|
; CHECK: ret
|
2008-12-19 04:05:58 +08:00
|
|
|
}
|
2010-06-04 09:20:10 +08:00
|
|
|
|
|
|
|
|
|
|
|
; widening shuffle v3float with a different mask and then a add
|
|
|
|
define void @shuf2(<3 x float>* %dst.addr, <3 x float> %src1,<3 x float> %src2) nounwind {
|
|
|
|
entry:
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: shuf2:
|
Change handling of illegal vector types to widen when possible instead of
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This
affects two places in the code: handling cross block values and handling
function return and arguments. Since vectors are already widened by
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.
For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
br label %BB
BB:
%D = fadd <2 x float> %C, %C
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
}
Now compiles into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
addps %xmm0, %xmm0
ret
previously it compiled into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
pshufd $1, %xmm0, %xmm1
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm1, %xmm0
addps %xmm0, %xmm0
ret
This implements rdar://8230384
llvm-svn: 112101
2010-08-26 06:49:25 +08:00
|
|
|
; CHECK: extractps
|
2010-06-04 09:20:10 +08:00
|
|
|
; CHECK: extractps
|
|
|
|
%x = shufflevector <3 x float> %src1, <3 x float> %src2, <3 x i32> < i32 0, i32 4, i32 2>
|
|
|
|
%val = fadd <3 x float> %x, %src2
|
|
|
|
store <3 x float> %val, <3 x float>* %dst.addr
|
|
|
|
ret void
|
2012-01-18 05:44:01 +08:00
|
|
|
; CHECK: ret
|
2010-06-04 09:20:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
; Example of when widening a v3float operation causes the DAG to replace a node
|
|
|
|
; with the operation that we are currently widening, i.e. when replacing
|
|
|
|
; opA with opB, the DAG will produce new operations with opA.
|
Change handling of illegal vector types to widen when possible instead of
expanding: e.g. <2 x float> -> <4 x float> instead of -> 2 floats. This
affects two places in the code: handling cross block values and handling
function return and arguments. Since vectors are already widened by
legalizetypes, this gives us much better code and unblocks x86-64 abi
and SPU abi work.
For example, this (which is a silly example of a cross-block value):
define <4 x float> @test2(<4 x float> %A) nounwind {
%B = shufflevector <4 x float> %A, <4 x float> undef, <2 x i32> <i32 0, i32 1>
%C = fadd <2 x float> %B, %B
br label %BB
BB:
%D = fadd <2 x float> %C, %C
%E = shufflevector <2 x float> %D, <2 x float> undef, <4 x i32> <i32 0, i32 1, i32 undef, i32 undef>
ret <4 x float> %E
}
Now compiles into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
addps %xmm0, %xmm0
ret
previously it compiled into:
_test2: ## @test2
## BB#0:
addps %xmm0, %xmm0
pshufd $1, %xmm0, %xmm1
## kill: XMM0<def> XMM0<kill> XMM0<def>
insertps $0, %xmm0, %xmm0
insertps $16, %xmm1, %xmm0
addps %xmm0, %xmm0
ret
This implements rdar://8230384
llvm-svn: 112101
2010-08-26 06:49:25 +08:00
|
|
|
define void @shuf3(<4 x float> %tmp10, <4 x float> %vecinit15, <4 x float>* %dst) nounwind {
|
2010-06-04 09:20:10 +08:00
|
|
|
entry:
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: shuf3:
|
[DAG] Further improve the logic in DAGCombiner that folds a pair of shuffles into a single shuffle if the resulting mask is legal.
This patch teaches the DAGCombiner how to fold shuffles according to the
following new rules:
1. shuffle(shuffle(x, y), undef) -> x
2. shuffle(shuffle(x, y), undef) -> y
3. shuffle(shuffle(x, y), undef) -> shuffle(x, undef)
4. shuffle(shuffle(x, y), undef) -> shuffle(y, undef)
The backend avoids to combine shuffles according to rules 3. and 4. if
the resulting shuffle does not have a legal mask. This is to avoid introducing
illegal shuffles that are potentially expanded into a sub-optimal sequence of
target specific dag nodes during vector legalization.
Added test case combine-vec-shuffle-2.ll to verify that we correctly triggers
the new rules when combining shuffles.
llvm-svn: 212748
2014-07-11 02:04:55 +08:00
|
|
|
; CHECK-NOT: movlhps
|
|
|
|
; CHECK-NOT: shufps
|
|
|
|
; CHECK: pshufd
|
2010-06-04 09:20:10 +08:00
|
|
|
%shuffle.i.i.i12 = shufflevector <4 x float> %tmp10, <4 x float> %vecinit15, <4 x i32> <i32 0, i32 1, i32 4, i32 5>
|
|
|
|
%tmp25.i.i = shufflevector <4 x float> %shuffle.i.i.i12, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
|
|
|
|
%tmp1.i.i = shufflevector <3 x float> %tmp25.i.i, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%tmp3.i13 = shufflevector <4 x float> %tmp1.i.i, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2> ; <<3 x float>>
|
|
|
|
%tmp6.i14 = shufflevector <3 x float> %tmp3.i13, <3 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
|
|
|
|
%tmp97.i = shufflevector <4 x float> %tmp6.i14, <4 x float> undef, <3 x i32> <i32 0, i32 1, i32 2>
|
|
|
|
%tmp2.i18 = shufflevector <3 x float> %tmp97.i, <3 x float> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 2>
|
|
|
|
%t5 = bitcast <4 x float> %tmp2.i18 to <4 x i32>
|
|
|
|
%shr.i.i19 = lshr <4 x i32> %t5, <i32 19, i32 19, i32 19, i32 19>
|
|
|
|
%and.i.i20 = and <4 x i32> %shr.i.i19, <i32 4080, i32 4080, i32 4080, i32 4080>
|
|
|
|
%shuffle.i.i.i21 = shufflevector <4 x float> %tmp2.i18, <4 x float> undef, <4 x i32> <i32 2, i32 3, i32 2, i32 3>
|
|
|
|
store <4 x float> %shuffle.i.i.i21, <4 x float>* %dst
|
|
|
|
ret void
|
2012-01-18 05:44:01 +08:00
|
|
|
; CHECK: ret
|
2010-06-04 09:20:10 +08:00
|
|
|
}
|
|
|
|
|
2011-07-21 02:14:33 +08:00
|
|
|
; PR10421: make sure we correctly handle extreme widening with CONCAT_VECTORS
|
|
|
|
define <8 x i8> @shuf4(<4 x i8> %a, <4 x i8> %b) nounwind readnone {
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: shuf4:
|
2011-10-17 04:31:33 +08:00
|
|
|
; CHECK-NOT: punpckldq
|
2011-07-21 02:14:33 +08:00
|
|
|
%vshuf = shufflevector <4 x i8> %a, <4 x i8> %b, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
|
|
|
|
ret <8 x i8> %vshuf
|
2012-01-18 05:44:01 +08:00
|
|
|
; CHECK: ret
|
2011-07-21 02:14:33 +08:00
|
|
|
}
|
2011-11-16 10:52:39 +08:00
|
|
|
|
|
|
|
; PR11389: another CONCAT_VECTORS case
|
|
|
|
define void @shuf5(<8 x i8>* %p) nounwind {
|
2013-07-14 14:24:09 +08:00
|
|
|
; CHECK-LABEL: shuf5:
|
2011-11-16 10:52:39 +08:00
|
|
|
%v = shufflevector <2 x i8> <i8 4, i8 33>, <2 x i8> undef, <8 x i32> <i32 1, i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
|
|
|
|
store <8 x i8> %v, <8 x i8>* %p, align 8
|
|
|
|
ret void
|
2012-01-18 05:44:01 +08:00
|
|
|
; CHECK: ret
|
2011-11-16 10:52:39 +08:00
|
|
|
}
|