2017-07-22 05:37:46 +08:00
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//===- DemandedBits.cpp - Determine demanded bits -------------------------===//
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2015-08-14 19:09:09 +08:00
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass implements a demanded bits analysis. A demanded bit is one that
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// contributes to a result; bits that are not demanded can be either zero or
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// one without affecting control or data flow. For example in this sequence:
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//
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// %1 = add i32 %x, %y
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// %2 = trunc i32 %1 to i16
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//
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// Only the lowest 16 bits of %1 are demanded; the rest are removed by the
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// trunc.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/Analysis/DemandedBits.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/ADT/APInt.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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2015-10-08 20:39:59 +08:00
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#include "llvm/ADT/StringExtras.h"
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2016-12-19 16:22:17 +08:00
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#include "llvm/Analysis/AssumptionCache.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/Analysis/ValueTracking.h"
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#include "llvm/IR/BasicBlock.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/IR/Constants.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/IR/DataLayout.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/IR/DerivedTypes.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/IR/Dominators.h"
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#include "llvm/IR/InstIterator.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/IR/InstrTypes.h"
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#include "llvm/IR/Instruction.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/IR/IntrinsicInst.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/IR/Intrinsics.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/IR/Module.h"
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#include "llvm/IR/Operator.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/IR/PassManager.h"
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#include "llvm/IR/Type.h"
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#include "llvm/IR/Use.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/Pass.h"
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2017-07-22 05:37:46 +08:00
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#include "llvm/Support/Casting.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/Support/Debug.h"
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2017-04-27 00:39:58 +08:00
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#include "llvm/Support/KnownBits.h"
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2015-08-14 19:09:09 +08:00
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#include "llvm/Support/raw_ostream.h"
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2017-07-22 05:37:46 +08:00
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#include <algorithm>
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#include <cstdint>
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2015-08-14 19:09:09 +08:00
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using namespace llvm;
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#define DEBUG_TYPE "demanded-bits"
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2016-04-19 07:55:01 +08:00
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char DemandedBitsWrapperPass::ID = 0;
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2017-07-22 05:37:46 +08:00
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2016-04-19 07:55:01 +08:00
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INITIALIZE_PASS_BEGIN(DemandedBitsWrapperPass, "demanded-bits",
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"Demanded bits analysis", false, false)
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2016-12-19 16:22:17 +08:00
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INITIALIZE_PASS_DEPENDENCY(AssumptionCacheTracker)
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2015-08-14 19:09:09 +08:00
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INITIALIZE_PASS_DEPENDENCY(DominatorTreeWrapperPass)
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2016-04-19 07:55:01 +08:00
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INITIALIZE_PASS_END(DemandedBitsWrapperPass, "demanded-bits",
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"Demanded bits analysis", false, false)
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2015-08-14 19:09:09 +08:00
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2016-04-19 07:55:01 +08:00
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DemandedBitsWrapperPass::DemandedBitsWrapperPass() : FunctionPass(ID) {
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initializeDemandedBitsWrapperPassPass(*PassRegistry::getPassRegistry());
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2015-08-14 19:09:09 +08:00
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}
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2016-04-19 07:55:01 +08:00
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void DemandedBitsWrapperPass::getAnalysisUsage(AnalysisUsage &AU) const {
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2015-08-14 19:09:09 +08:00
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AU.setPreservesCFG();
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2016-12-19 16:22:17 +08:00
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AU.addRequired<AssumptionCacheTracker>();
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2015-08-14 19:09:09 +08:00
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AU.addRequired<DominatorTreeWrapperPass>();
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AU.setPreservesAll();
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}
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2016-04-19 07:55:01 +08:00
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void DemandedBitsWrapperPass::print(raw_ostream &OS, const Module *M) const {
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DB->print(OS);
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}
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2015-08-14 19:09:09 +08:00
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static bool isAlwaysLive(Instruction *I) {
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2018-08-26 17:51:22 +08:00
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return I->isTerminator() || isa<DbgInfoIntrinsic>(I) || I->isEHPad() ||
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I->mayHaveSideEffects();
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2015-08-14 19:09:09 +08:00
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}
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2015-09-22 19:15:07 +08:00
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void DemandedBits::determineLiveOperandBits(
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const Instruction *UserI, const Instruction *I, unsigned OperandNo,
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2017-04-27 00:39:58 +08:00
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const APInt &AOut, APInt &AB, KnownBits &Known, KnownBits &Known2) {
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2015-08-14 19:09:09 +08:00
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unsigned BitWidth = AB.getBitWidth();
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// We're called once per operand, but for some instructions, we need to
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// compute known bits of both operands in order to determine the live bits of
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// either (when both operands are instructions themselves). We don't,
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// however, want to do this twice, so we cache the result in APInts that live
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// in the caller. For the two-relevant-operands case, both operand values are
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// provided here.
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auto ComputeKnownBits =
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[&](unsigned BitWidth, const Value *V1, const Value *V2) {
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const DataLayout &DL = I->getModule()->getDataLayout();
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2017-04-27 00:39:58 +08:00
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Known = KnownBits(BitWidth);
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2017-05-14 01:22:16 +08:00
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computeKnownBits(V1, Known, DL, 0, &AC, UserI, &DT);
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2015-08-14 19:09:09 +08:00
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if (V2) {
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2017-04-27 00:39:58 +08:00
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Known2 = KnownBits(BitWidth);
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2017-05-14 01:22:16 +08:00
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computeKnownBits(V2, Known2, DL, 0, &AC, UserI, &DT);
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2015-08-14 19:09:09 +08:00
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}
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};
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switch (UserI->getOpcode()) {
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default: break;
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case Instruction::Call:
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case Instruction::Invoke:
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if (const IntrinsicInst *II = dyn_cast<IntrinsicInst>(UserI))
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switch (II->getIntrinsicID()) {
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default: break;
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case Intrinsic::bswap:
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// The alive bits of the input are the swapped alive bits of
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// the output.
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AB = AOut.byteSwap();
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break;
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2017-04-14 00:44:25 +08:00
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case Intrinsic::bitreverse:
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2017-06-20 04:10:41 +08:00
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// The alive bits of the input are the reversed alive bits of
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// the output.
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2017-04-14 00:44:25 +08:00
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AB = AOut.reverseBits();
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break;
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2015-08-14 19:09:09 +08:00
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case Intrinsic::ctlz:
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if (OperandNo == 0) {
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// We need some output bits, so we need all bits of the
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// input to the left of, and including, the leftmost bit
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// known to be one.
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ComputeKnownBits(BitWidth, I, nullptr);
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AB = APInt::getHighBitsSet(BitWidth,
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2017-05-13 01:20:30 +08:00
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std::min(BitWidth, Known.countMaxLeadingZeros()+1));
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2015-08-14 19:09:09 +08:00
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}
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break;
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case Intrinsic::cttz:
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if (OperandNo == 0) {
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// We need some output bits, so we need all bits of the
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// input to the right of, and including, the rightmost bit
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// known to be one.
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ComputeKnownBits(BitWidth, I, nullptr);
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AB = APInt::getLowBitsSet(BitWidth,
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2017-05-13 01:20:30 +08:00
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std::min(BitWidth, Known.countMaxTrailingZeros()+1));
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2015-08-14 19:09:09 +08:00
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}
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break;
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2018-11-26 23:36:57 +08:00
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case Intrinsic::fshl:
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case Intrinsic::fshr:
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if (OperandNo == 2) {
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// Shift amount is modulo the bitwidth. For powers of two we have
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// SA % BW == SA & (BW - 1).
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if (isPowerOf2_32(BitWidth))
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AB = BitWidth - 1;
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} else if (auto *SA = dyn_cast<ConstantInt>(II->getOperand(2))) {
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// TODO: Support vectors.
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// Normalize to funnel shift left. APInt shifts of BitWidth are well-
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// defined, so no need to special-case zero shifts here.
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uint64_t ShiftAmt = SA->getValue().urem(BitWidth);
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if (II->getIntrinsicID() == Intrinsic::fshr)
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ShiftAmt = BitWidth - ShiftAmt;
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if (OperandNo == 0)
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AB = AOut.lshr(ShiftAmt);
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else if (OperandNo == 1)
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AB = AOut.shl(BitWidth - ShiftAmt);
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}
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break;
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2015-08-14 19:09:09 +08:00
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}
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break;
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case Instruction::Add:
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case Instruction::Sub:
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2015-10-08 20:39:59 +08:00
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case Instruction::Mul:
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2015-08-14 19:09:09 +08:00
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// Find the highest live output bit. We don't need any more input
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// bits than that (adds, and thus subtracts, ripple only to the
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// left).
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AB = APInt::getLowBitsSet(BitWidth, AOut.getActiveBits());
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break;
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case Instruction::Shl:
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if (OperandNo == 0)
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2017-07-07 22:39:26 +08:00
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if (auto *ShiftAmtC = dyn_cast<ConstantInt>(UserI->getOperand(1))) {
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uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
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2015-08-14 19:09:09 +08:00
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AB = AOut.lshr(ShiftAmt);
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// If the shift is nuw/nsw, then the high bits are not dead
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// (because we've promised that they *must* be zero).
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const ShlOperator *S = cast<ShlOperator>(UserI);
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if (S->hasNoSignedWrap())
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AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1);
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else if (S->hasNoUnsignedWrap())
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AB |= APInt::getHighBitsSet(BitWidth, ShiftAmt);
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}
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break;
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case Instruction::LShr:
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if (OperandNo == 0)
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2017-07-07 22:39:26 +08:00
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if (auto *ShiftAmtC = dyn_cast<ConstantInt>(UserI->getOperand(1))) {
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uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
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2015-08-14 19:09:09 +08:00
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AB = AOut.shl(ShiftAmt);
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// If the shift is exact, then the low bits are not dead
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// (they must be zero).
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if (cast<LShrOperator>(UserI)->isExact())
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AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
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}
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break;
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case Instruction::AShr:
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if (OperandNo == 0)
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2017-07-07 22:39:26 +08:00
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if (auto *ShiftAmtC = dyn_cast<ConstantInt>(UserI->getOperand(1))) {
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uint64_t ShiftAmt = ShiftAmtC->getLimitedValue(BitWidth - 1);
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2015-08-14 19:09:09 +08:00
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AB = AOut.shl(ShiftAmt);
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// Because the high input bit is replicated into the
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// high-order bits of the result, if we need any of those
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// bits, then we must keep the highest input bit.
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if ((AOut & APInt::getHighBitsSet(BitWidth, ShiftAmt))
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.getBoolValue())
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2017-04-29 00:58:05 +08:00
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AB.setSignBit();
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2015-08-14 19:09:09 +08:00
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// If the shift is exact, then the low bits are not dead
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// (they must be zero).
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if (cast<AShrOperator>(UserI)->isExact())
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AB |= APInt::getLowBitsSet(BitWidth, ShiftAmt);
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}
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break;
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case Instruction::And:
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AB = AOut;
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// For bits that are known zero, the corresponding bits in the
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// other operand are dead (unless they're both zero, in which
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// case they can't both be dead, so just mark the LHS bits as
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// dead).
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if (OperandNo == 0) {
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ComputeKnownBits(BitWidth, I, UserI->getOperand(1));
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2017-04-27 00:39:58 +08:00
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AB &= ~Known2.Zero;
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2015-08-14 19:09:09 +08:00
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} else {
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if (!isa<Instruction>(UserI->getOperand(0)))
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ComputeKnownBits(BitWidth, UserI->getOperand(0), I);
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2017-04-27 00:39:58 +08:00
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AB &= ~(Known.Zero & ~Known2.Zero);
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2015-08-14 19:09:09 +08:00
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}
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break;
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case Instruction::Or:
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AB = AOut;
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// For bits that are known one, the corresponding bits in the
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// other operand are dead (unless they're both one, in which
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// case they can't both be dead, so just mark the LHS bits as
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// dead).
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if (OperandNo == 0) {
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ComputeKnownBits(BitWidth, I, UserI->getOperand(1));
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2017-04-27 00:39:58 +08:00
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AB &= ~Known2.One;
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2015-08-14 19:09:09 +08:00
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} else {
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if (!isa<Instruction>(UserI->getOperand(0)))
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ComputeKnownBits(BitWidth, UserI->getOperand(0), I);
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2017-04-27 00:39:58 +08:00
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AB &= ~(Known.One & ~Known2.One);
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2015-08-14 19:09:09 +08:00
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}
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break;
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case Instruction::Xor:
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case Instruction::PHI:
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AB = AOut;
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break;
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case Instruction::Trunc:
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AB = AOut.zext(BitWidth);
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break;
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case Instruction::ZExt:
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AB = AOut.trunc(BitWidth);
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break;
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case Instruction::SExt:
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AB = AOut.trunc(BitWidth);
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// Because the high input bit is replicated into the
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// high-order bits of the result, if we need any of those
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// bits, then we must keep the highest input bit.
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if ((AOut & APInt::getHighBitsSet(AOut.getBitWidth(),
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AOut.getBitWidth() - BitWidth))
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.getBoolValue())
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2017-04-29 00:58:05 +08:00
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AB.setSignBit();
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2015-08-14 19:09:09 +08:00
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break;
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case Instruction::Select:
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if (OperandNo != 0)
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AB = AOut;
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break;
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}
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}
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2016-04-19 07:55:01 +08:00
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bool DemandedBitsWrapperPass::runOnFunction(Function &F) {
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2016-12-19 16:22:17 +08:00
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auto &AC = getAnalysis<AssumptionCacheTracker>().getAssumptionCache(F);
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2016-04-19 07:55:01 +08:00
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auto &DT = getAnalysis<DominatorTreeWrapperPass>().getDomTree();
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2016-12-19 16:22:17 +08:00
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DB.emplace(F, AC, DT);
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2015-10-08 20:39:50 +08:00
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return false;
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}
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2015-08-14 19:09:09 +08:00
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2016-04-19 07:55:01 +08:00
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void DemandedBitsWrapperPass::releaseMemory() {
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DB.reset();
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}
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2015-10-08 20:39:50 +08:00
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void DemandedBits::performAnalysis() {
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if (Analyzed)
|
|
|
|
// Analysis already completed for this function.
|
|
|
|
return;
|
|
|
|
Analyzed = true;
|
2018-07-31 03:41:25 +08:00
|
|
|
|
2015-08-14 19:09:09 +08:00
|
|
|
Visited.clear();
|
|
|
|
AliveBits.clear();
|
|
|
|
|
|
|
|
SmallVector<Instruction*, 128> Worklist;
|
|
|
|
|
|
|
|
// Collect the set of "root" instructions that are known live.
|
2016-04-19 07:55:01 +08:00
|
|
|
for (Instruction &I : instructions(F)) {
|
2015-08-14 19:09:09 +08:00
|
|
|
if (!isAlwaysLive(&I))
|
|
|
|
continue;
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "DemandedBits: Root: " << I << "\n");
|
2015-08-14 19:09:09 +08:00
|
|
|
// For integer-valued instructions, set up an initial empty set of alive
|
|
|
|
// bits and add the instruction to the work list. For other instructions
|
|
|
|
// add their operands to the work list (for integer values operands, mark
|
|
|
|
// all bits as live).
|
|
|
|
if (IntegerType *IT = dyn_cast<IntegerType>(I.getType())) {
|
2016-07-21 21:37:55 +08:00
|
|
|
if (AliveBits.try_emplace(&I, IT->getBitWidth(), 0).second)
|
2015-08-14 19:09:09 +08:00
|
|
|
Worklist.push_back(&I);
|
|
|
|
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
// Non-integer-typed instructions...
|
|
|
|
for (Use &OI : I.operands()) {
|
|
|
|
if (Instruction *J = dyn_cast<Instruction>(OI)) {
|
|
|
|
if (IntegerType *IT = dyn_cast<IntegerType>(J->getType()))
|
|
|
|
AliveBits[J] = APInt::getAllOnesValue(IT->getBitWidth());
|
|
|
|
Worklist.push_back(J);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
// To save memory, we don't add I to the Visited set here. Instead, we
|
|
|
|
// check isAlwaysLive on every instruction when searching for dead
|
|
|
|
// instructions later (we need to check isAlwaysLive for the
|
|
|
|
// integer-typed instructions anyway).
|
|
|
|
}
|
|
|
|
|
|
|
|
// Propagate liveness backwards to operands.
|
|
|
|
while (!Worklist.empty()) {
|
|
|
|
Instruction *UserI = Worklist.pop_back_val();
|
|
|
|
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "DemandedBits: Visiting: " << *UserI);
|
2015-08-14 19:09:09 +08:00
|
|
|
APInt AOut;
|
|
|
|
if (UserI->getType()->isIntegerTy()) {
|
|
|
|
AOut = AliveBits[UserI];
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << " Alive Out: " << AOut);
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
2018-05-14 20:53:11 +08:00
|
|
|
LLVM_DEBUG(dbgs() << "\n");
|
2015-08-14 19:09:09 +08:00
|
|
|
|
|
|
|
if (!UserI->getType()->isIntegerTy())
|
|
|
|
Visited.insert(UserI);
|
|
|
|
|
2017-04-27 00:39:58 +08:00
|
|
|
KnownBits Known, Known2;
|
2015-08-14 19:09:09 +08:00
|
|
|
// Compute the set of alive bits for each operand. These are anded into the
|
|
|
|
// existing set, if any, and if that changes the set of alive bits, the
|
|
|
|
// operand is added to the work-list.
|
|
|
|
for (Use &OI : UserI->operands()) {
|
|
|
|
if (Instruction *I = dyn_cast<Instruction>(OI)) {
|
|
|
|
if (IntegerType *IT = dyn_cast<IntegerType>(I->getType())) {
|
|
|
|
unsigned BitWidth = IT->getBitWidth();
|
|
|
|
APInt AB = APInt::getAllOnesValue(BitWidth);
|
|
|
|
if (UserI->getType()->isIntegerTy() && !AOut &&
|
|
|
|
!isAlwaysLive(UserI)) {
|
|
|
|
AB = APInt(BitWidth, 0);
|
|
|
|
} else {
|
2015-09-22 19:14:12 +08:00
|
|
|
// If all bits of the output are dead, then all bits of the input
|
2015-08-14 19:09:09 +08:00
|
|
|
// Bits of each operand that are used to compute alive bits of the
|
|
|
|
// output are alive, all others are dead.
|
|
|
|
determineLiveOperandBits(UserI, I, OI.getOperandNo(), AOut, AB,
|
2017-04-27 00:39:58 +08:00
|
|
|
Known, Known2);
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
// If we've added to the set of alive bits (or the operand has not
|
|
|
|
// been previously visited), then re-queue the operand to be visited
|
|
|
|
// again.
|
|
|
|
APInt ABPrev(BitWidth, 0);
|
|
|
|
auto ABI = AliveBits.find(I);
|
|
|
|
if (ABI != AliveBits.end())
|
|
|
|
ABPrev = ABI->second;
|
|
|
|
|
|
|
|
APInt ABNew = AB | ABPrev;
|
|
|
|
if (ABNew != ABPrev || ABI == AliveBits.end()) {
|
|
|
|
AliveBits[I] = std::move(ABNew);
|
|
|
|
Worklist.push_back(I);
|
|
|
|
}
|
|
|
|
} else if (!Visited.count(I)) {
|
|
|
|
Worklist.push_back(I);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
APInt DemandedBits::getDemandedBits(Instruction *I) {
|
2015-10-08 20:39:50 +08:00
|
|
|
performAnalysis();
|
2018-07-31 03:41:25 +08:00
|
|
|
|
2017-08-16 22:28:23 +08:00
|
|
|
const DataLayout &DL = I->getModule()->getDataLayout();
|
2016-07-21 21:37:55 +08:00
|
|
|
auto Found = AliveBits.find(I);
|
|
|
|
if (Found != AliveBits.end())
|
|
|
|
return Found->second;
|
2015-08-14 19:09:09 +08:00
|
|
|
return APInt::getAllOnesValue(DL.getTypeSizeInBits(I->getType()));
|
|
|
|
}
|
|
|
|
|
|
|
|
bool DemandedBits::isInstructionDead(Instruction *I) {
|
2015-10-08 20:39:50 +08:00
|
|
|
performAnalysis();
|
|
|
|
|
2015-08-14 19:09:09 +08:00
|
|
|
return !Visited.count(I) && AliveBits.find(I) == AliveBits.end() &&
|
|
|
|
!isAlwaysLive(I);
|
|
|
|
}
|
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
void DemandedBits::print(raw_ostream &OS) {
|
|
|
|
performAnalysis();
|
2015-10-08 20:39:59 +08:00
|
|
|
for (auto &KV : AliveBits) {
|
2017-12-29 00:58:54 +08:00
|
|
|
OS << "DemandedBits: 0x" << Twine::utohexstr(KV.second.getLimitedValue())
|
|
|
|
<< " for " << *KV.first << '\n';
|
2015-10-08 20:39:59 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-04-19 07:55:01 +08:00
|
|
|
FunctionPass *llvm::createDemandedBitsWrapperPass() {
|
|
|
|
return new DemandedBitsWrapperPass();
|
|
|
|
}
|
|
|
|
|
2016-11-24 01:53:26 +08:00
|
|
|
AnalysisKey DemandedBitsAnalysis::Key;
|
2016-04-19 07:55:01 +08:00
|
|
|
|
|
|
|
DemandedBits DemandedBitsAnalysis::run(Function &F,
|
2016-08-09 08:28:15 +08:00
|
|
|
FunctionAnalysisManager &AM) {
|
2016-12-19 16:22:17 +08:00
|
|
|
auto &AC = AM.getResult<AssumptionAnalysis>(F);
|
2016-04-19 07:55:01 +08:00
|
|
|
auto &DT = AM.getResult<DominatorTreeAnalysis>(F);
|
2016-12-19 16:22:17 +08:00
|
|
|
return DemandedBits(F, AC, DT);
|
2016-04-19 07:55:01 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
PreservedAnalyses DemandedBitsPrinterPass::run(Function &F,
|
|
|
|
FunctionAnalysisManager &AM) {
|
|
|
|
AM.getResult<DemandedBitsAnalysis>(F).print(OS);
|
|
|
|
return PreservedAnalyses::all();
|
2015-08-14 19:09:09 +08:00
|
|
|
}
|