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llvm-project/llvm/test/CodeGen/ARM/rbit.ll

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ARM: Fix codegen for rbit intrinsic LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic. According to ARM ARM, rbit only takes register as argument, not immediate. The correct instruction should be rbit <Rd>, <Rm>. The bug was originally introduced in r211057. Differential Revision: http://reviews.llvm.org/D4980 llvm-svn: 216064
2014-08-20 18:40:20 +08:00
; RUN: llc -mtriple=armv8-eabi %s -o - | FileCheck %s
; CHECK-LABEL: rbit
; CHECK: rbit r0, r0
define i32 @rbit(i32 %t) {
entry:
%rbit = call i32 @llvm.arm.rbit(i32 %t)
ret i32 %rbit
}
; CHECK-LABEL: rbit_constant
; CHECK: mov r0, #0
[SelectionDAG] Add support for BITREVERSE constant folding We were relying on constant folding of the legalized instructions to do what constant folding we had previously llvm-svn: 292114
2017-01-16 21:39:00 +08:00
; CHECK-NOT: rbit
; CHECK: bx lr
ARM: Fix codegen for rbit intrinsic LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic. According to ARM ARM, rbit only takes register as argument, not immediate. The correct instruction should be rbit <Rd>, <Rm>. The bug was originally introduced in r211057. Differential Revision: http://reviews.llvm.org/D4980 llvm-svn: 216064
2014-08-20 18:40:20 +08:00
define i32 @rbit_constant() {
entry:
%rbit.i = call i32 @llvm.arm.rbit(i32 0)
ret i32 %rbit.i
}
declare i32 @llvm.arm.rbit(i32)
[ARM] Replace ARMISD::RBIT with ISD::BITREVERSE ISD::BITREVERSE matches "rbit" completely, so remove ARMISD::RBIT and mark ISD::BITREVERSE as legal, adding a test for lowering. llvm-svn: 253047
2015-11-14 00:05:22 +08:00
declare i32 @llvm.bitreverse.i32(i32) readnone
; CHECK-LABEL: rbit_generic
; CHECK: rbit r0, r0
define i32 @rbit_generic(i32 %t) {
entry:
%rbit = call i32 @llvm.bitreverse.i32(i32 %t)
ret i32 %rbit
}