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llvm-project/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp

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Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
//===- MipsDisassembler.cpp - Disassembler for Mips -------------*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file is part of the Mips Disassembler.
//
//===----------------------------------------------------------------------===//
#include "Mips.h"
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
#include "MipsRegisterInfo.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "MipsSubtarget.h"
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
#include "llvm/MC/MCDisassembler.h"
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
#include "llvm/MC/MCFixedLenDisassembler.h"
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
#include "llvm/MC/MCInst.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/MC/MCSubtargetInfo.h"
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
#include "llvm/Support/MathExtras.h"
Use the new script to sort the includes of every file under lib. Sooooo many of these had incorrect or strange main module includes. I have manually inspected all of these, and fixed the main module include to be the nearest plausible thing I could find. If you own or care about any of these source files, I encourage you to take some time and check that these edits were sensible. I can't have broken anything (I strictly added headers, and reordered them, never removed), but they may not be the headers you'd really like to identify as containing the API being implemented. Many forward declarations and missing includes were added to a header files to allow them to parse cleanly when included first. The main module rule does in fact have its merits. =] llvm-svn: 169131
2012-12-04 00:50:05 +08:00
#include "llvm/Support/MemoryObject.h"
#include "llvm/Support/TargetRegistry.h"
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
using namespace llvm;
typedef MCDisassembler::DecodeStatus DecodeStatus;
Move MipsDisassembler classes into an anonymous namespace. llvm-svn: 155915
2012-05-01 22:34:24 +08:00
namespace {
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
/// MipsDisassemblerBase - a disasembler class for Mips.
class MipsDisassemblerBase : public MCDisassembler {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
public:
/// Constructor - Initializes the disassembler.
///
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
MipsDisassemblerBase(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
bool bigEndian) :
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
MCDisassembler(STI), RegInfo(Info),
IsN64(STI.getFeatureBits() & Mips::FeatureN64), isBigEndian(bigEndian) {}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
virtual ~MipsDisassemblerBase() {}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Stop leaking register infos in the disassemblers. llvm-svn: 187695
2013-08-04 06:16:16 +08:00
const MCRegisterInfo *getRegInfo() const { return RegInfo.get(); }
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
bool isN64() const { return IsN64; }
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
private:
Stop leaking register infos in the disassemblers. llvm-svn: 187695
2013-08-04 06:16:16 +08:00
OwningPtr<const MCRegisterInfo> RegInfo;
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
bool IsN64;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
protected:
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
bool isBigEndian;
};
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
/// MipsDisassembler - a disasembler class for Mips32.
class MipsDisassembler : public MipsDisassemblerBase {
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
bool IsMicroMips;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
public:
/// Constructor - Initializes the disassembler.
///
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
MipsDisassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
bool bigEndian) :
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
MipsDisassemblerBase(STI, Info, bigEndian) {
IsMicroMips = STI.getFeatureBits() & Mips::FeatureMicroMips;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
/// getInstruction - See MCDisassembler.
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
virtual DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const;
};
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
/// Mips64Disassembler - a disasembler class for Mips64.
class Mips64Disassembler : public MipsDisassemblerBase {
public:
/// Constructor - Initializes the disassembler.
///
Mips64Disassembler(const MCSubtargetInfo &STI, const MCRegisterInfo *Info,
bool bigEndian) :
MipsDisassemblerBase(STI, Info, bigEndian) {}
/// getInstruction - See MCDisassembler.
virtual DecodeStatus getInstruction(MCInst &instr,
uint64_t &size,
const MemoryObject &region,
uint64_t address,
raw_ostream &vStream,
raw_ostream &cStream) const;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
};
Move MipsDisassembler classes into an anonymous namespace. llvm-svn: 155915
2012-05-01 22:34:24 +08:00
} // end anonymous namespace
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
// Forward declare these because the autogenerated code will reference them.
// Definitions are further down.
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Remove the form field from Mips16 instruction formats and set things up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. llvm-svn: 175126
2013-02-14 11:05:25 +08:00
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips] Rename DSPRegs. llvm-svn: 188342
2013-08-14 08:53:38 +08:00
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Define register class FGRH32 for the high half of the 64-bit floating point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. llvm-svn: 188842
2013-08-21 06:58:56 +08:00
static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Fix FP branch instructions to have explicit FP condition code register operands. llvm-svn: 187238
2013-07-27 04:13:47 +08:00
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Support for microMIPS jump instructions llvm-svn: 193623
2013-10-30 00:38:59 +08:00
// DecodeJumpTargetMM - Decode microMIPS jump target, which is
// shifted left by 1 bit.
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeMem(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder);
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFMem(MCInst &Inst, unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeSimm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeInsSize(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
static DecodeStatus DecodeExtSize(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder);
namespace llvm {
extern Target TheMipselTarget, TheMipsTarget, TheMips64Target,
TheMips64elTarget;
}
static MCDisassembler *createMipsDisassembler(
const Target &T,
const MCSubtargetInfo &STI) {
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
return new MipsDisassembler(STI, T.createMCRegInfo(""), true);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
static MCDisassembler *createMipselDisassembler(
const Target &T,
const MCSubtargetInfo &STI) {
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
return new MipsDisassembler(STI, T.createMCRegInfo(""), false);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
static MCDisassembler *createMips64Disassembler(
const Target &T,
const MCSubtargetInfo &STI) {
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
return new Mips64Disassembler(STI, T.createMCRegInfo(""), true);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
static MCDisassembler *createMips64elDisassembler(
const Target &T,
const MCSubtargetInfo &STI) {
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
return new Mips64Disassembler(STI, T.createMCRegInfo(""), false);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
extern "C" void LLVMInitializeMipsDisassembler() {
// Register the disassembler.
TargetRegistry::RegisterMCDisassembler(TheMipsTarget,
createMipsDisassembler);
TargetRegistry::RegisterMCDisassembler(TheMipselTarget,
createMipselDisassembler);
TargetRegistry::RegisterMCDisassembler(TheMips64Target,
createMips64Disassembler);
TargetRegistry::RegisterMCDisassembler(TheMips64elTarget,
createMips64elDisassembler);
}
#include "MipsGenDisassemblerTables.inc"
/// readInstruction - read four bytes from the MemoryObject
/// and return 32 bit word sorted according to the given endianess
static DecodeStatus readInstruction32(const MemoryObject &region,
uint64_t address,
uint64_t &size,
uint32_t &insn,
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
bool isBigEndian,
bool IsMicroMips) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
uint8_t Bytes[4];
// We want to read exactly 4 Bytes of data.
Remove the Copied parameter from MemoryObject::readBytes. There was exactly one caller using this API right, the others were relying on specific behavior of the default implementation. Since it's too hard to use it right just remove it and standardize on the default behavior. Defines away PR16132. llvm-svn: 182636
2013-05-24 18:54:58 +08:00
if (region.readBytes(address, 4, Bytes) == -1) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
size = 0;
return MCDisassembler::Fail;
}
if (isBigEndian) {
// Encoded as a big-endian 32-bit word in the stream.
insn = (Bytes[3] << 0) |
(Bytes[2] << 8) |
(Bytes[1] << 16) |
(Bytes[0] << 24);
}
else {
// Encoded as a small-endian 32-bit word in the stream.
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
// Little-endian byte ordering:
// mips32r2: 4 | 3 | 2 | 1
// microMIPS: 2 | 1 | 4 | 3
if (IsMicroMips) {
insn = (Bytes[2] << 0) |
(Bytes[3] << 8) |
(Bytes[0] << 16) |
(Bytes[1] << 24);
} else {
insn = (Bytes[0] << 0) |
(Bytes[1] << 8) |
(Bytes[2] << 16) |
(Bytes[3] << 24);
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
return MCDisassembler::Success;
}
DecodeStatus
MipsDisassembler::getInstruction(MCInst &instr,
uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
raw_ostream &vStream,
raw_ostream &cStream) const {
uint32_t Insn;
DecodeStatus Result = readInstruction32(Region, Address, Size,
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
Insn, isBigEndian, IsMicroMips);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
if (IsMicroMips) {
// Calling the auto-generated decoder function.
Result = decodeInstruction(DecoderTableMicroMips32, instr, Insn, Address,
this, STI);
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
return MCDisassembler::Fail;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
// Calling the auto-generated decoder function.
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
this, STI);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
return MCDisassembler::Fail;
}
DecodeStatus
Mips64Disassembler::getInstruction(MCInst &instr,
uint64_t &Size,
const MemoryObject &Region,
uint64_t Address,
raw_ostream &vStream,
raw_ostream &cStream) const {
uint32_t Insn;
DecodeStatus Result = readInstruction32(Region, Address, Size,
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
Insn, isBigEndian, false);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (Result == MCDisassembler::Fail)
return MCDisassembler::Fail;
// Calling the auto-generated decoder function.
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
this, STI);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
// If we fail to decode in Mips64 decoder space we can try in Mips32
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
this, STI);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (Result != MCDisassembler::Fail) {
Size = 4;
return Result;
}
return MCDisassembler::Fail;
}
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
static unsigned getReg(const void *D, unsigned RC, unsigned RegNo) {
const MipsDisassemblerBase *Dis = static_cast<const MipsDisassemblerBase*>(D);
return *(Dis->getRegInfo()->getRegClass(RC).begin() + RegNo);
}
Remove the form field from Mips16 instruction formats and set things up so that we can apply the direct object emitter patch. This patch should be a nop right now and it's test is to not break what is already there. llvm-svn: 175126
2013-02-14 11:05:25 +08:00
static DecodeStatus DecodeCPU16RegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
return MCDisassembler::Fail;
}
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (RegNo > 31)
return MCDisassembler::Fail;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
unsigned Reg = getReg(Decoder, Mips::GPR64RegClassID, RegNo);
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
static DecodeStatus DecodeGPR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if (RegNo > 31)
return MCDisassembler::Fail;
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
unsigned Reg = getReg(Decoder, Mips::GPR32RegClassID, RegNo);
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Use ptr_rc to simplify definitions of base+index load/store instructions. Also, fix predicates. llvm-svn: 189432
2013-08-28 08:55:15 +08:00
static DecodeStatus DecodePtrRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (static_cast<const MipsDisassembler *>(Decoder)->isN64())
return DecodeGPR64RegisterClass(Inst, RegNo, Address, Decoder);
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
}
[mips] Rename DSPRegs. llvm-svn: 188342
2013-08-14 08:53:38 +08:00
static DecodeStatus DecodeDSPRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
return DecodeGPR32RegisterClass(Inst, RegNo, Address, Decoder);
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
unsigned Reg = getReg(Decoder, Mips::FGR64RegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
static DecodeStatus DecodeFGR32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
unsigned Reg = getReg(Decoder, Mips::FGR32RegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Define register class FGRH32 for the high half of the 64-bit floating point registers. We will need this register class later when we add definitions for instructions mfhc1 and mthc1. Also, remove sub-register indices sub_fpeven and sub_fpodd and use sub_lo and sub_hi instead. llvm-svn: 188842
2013-08-21 06:58:56 +08:00
static DecodeStatus DecodeFGRH32RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FGRH32RegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeCCRRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[Mips Disassembler] Have the DecodeCCRRegisterClass function use the getReg function to lookup the proper tablegen'ed register enumeration. Previously, it was using the encoded value directly. llvm-svn: 185026
2013-06-27 06:23:32 +08:00
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::CCRRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Fix FP branch instructions to have explicit FP condition code register operands. llvm-svn: 187238
2013-07-27 04:13:47 +08:00
static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::FCCRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeMem(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
if(Inst.getOpcode() == Mips::SC){
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
}
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
static DecodeStatus DecodeMSA128Mem(MCInst &Inst, unsigned Insn,
uint64_t Address, const void *Decoder) {
int Offset = SignExtend32<10>(fieldFromInstruction(Insn, 16, 10));
unsigned Reg = fieldFromInstruction(Insn, 6, 5);
unsigned Base = fieldFromInstruction(Insn, 11, 5);
Reg = getReg(Decoder, Mips::MSA128BRegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
This patch adds support for microMIPS disassembler and disassembler make check tests. llvm-svn: 190144
2013-09-06 20:30:36 +08:00
static DecodeStatus DecodeMemMMImm12(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<12>(Insn & 0x0fff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMemMMImm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
unsigned Reg = fieldFromInstruction(Insn, 21, 5);
unsigned Base = fieldFromInstruction(Insn, 16, 5);
Reg = getReg(Decoder, Mips::GPR32RegClassID, Reg);
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeFMem(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
unsigned Reg = fieldFromInstruction(Insn, 16, 5);
unsigned Base = fieldFromInstruction(Insn, 21, 5);
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
[mips] Rename register classes CPURegs and CPU64Regs. llvm-svn: 187832
2013-08-07 07:08:38 +08:00
Base = getReg(Decoder, Mips::GPR32RegClassID, Base);
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
Inst.addOperand(MCOperand::CreateReg(Base));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Inst.addOperand(MCOperand::CreateImm(Offset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeHWRegsRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
// Currently only hardware register 29 is supported.
if (RegNo != 29)
return MCDisassembler::Fail;
Inst.addOperand(MCOperand::CreateReg(Mips::HWR29));
return MCDisassembler::Success;
}
static DecodeStatus DecodeAFGR64RegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
if (RegNo > 30 || RegNo %2)
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Fail;
Reapply r158846. Access mips register classes via MCRegisterInfo's functions instead of via the TargetRegisterClasses defined in MipsGenRegisterInfo.inc. llvm-svn: 159953
2012-07-10 02:46:47 +08:00
;
unsigned Reg = getReg(Decoder, Mips::AFGR64RegClassID, RegNo /2);
Inst.addOperand(MCOperand::CreateReg(Reg));
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
return MCDisassembler::Success;
}
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
static DecodeStatus DecodeACC64DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
if (RegNo >= 4)
return MCDisassembler::Fail;
[mips] Rename accumulator register classes and FP register operands. llvm-svn: 188020
2013-08-09 05:54:26 +08:00
unsigned Reg = getReg(Decoder, Mips::ACC64DSPRegClassID, RegNo);
MIPS DSP: add functions which decode DSP and accumulator registers. llvm-svn: 164748
2012-09-27 10:01:10 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeHI32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
if (RegNo >= 4)
return MCDisassembler::Fail;
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
unsigned Reg = getReg(Decoder, Mips::HI32DSPRegClassID, RegNo);
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
static DecodeStatus DecodeLO32DSPRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
if (RegNo >= 4)
return MCDisassembler::Fail;
[mips] Rename HIRegs and LORegs. llvm-svn: 188341
2013-08-14 08:47:08 +08:00
unsigned Reg = getReg(Decoder, Mips::LO32DSPRegClassID, RegNo);
[mips] DSP-ASE move from HI/LO register instructions. llvm-svn: 179739
2013-04-18 08:52:44 +08:00
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
static DecodeStatus DecodeMSA128BRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128BRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
static DecodeStatus DecodeMSA128HRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128HRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMSA128WRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128WRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
static DecodeStatus DecodeMSA128DRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 31)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSA128DRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
static DecodeStatus DecodeMSACtrlRegisterClass(MCInst &Inst,
unsigned RegNo,
uint64_t Address,
const void *Decoder) {
if (RegNo > 7)
return MCDisassembler::Fail;
unsigned Reg = getReg(Decoder, Mips::MSACtrlRegClassID, RegNo);
Inst.addOperand(MCOperand::CreateReg(Reg));
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeBranchTarget(MCInst &Inst,
unsigned Offset,
uint64_t Address,
const void *Decoder) {
unsigned BranchOffset = Offset & 0xffff;
BranchOffset = SignExtend32<18>(BranchOffset << 2) + 4;
Inst.addOperand(MCOperand::CreateImm(BranchOffset));
return MCDisassembler::Success;
}
static DecodeStatus DecodeJumpTarget(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. llvm-svn: 161888
2012-08-15 03:06:05 +08:00
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
Inst.addOperand(MCOperand::CreateImm(JumpOffset));
return MCDisassembler::Success;
}
Support for microMIPS jump instructions llvm-svn: 193623
2013-10-30 00:38:59 +08:00
static DecodeStatus DecodeJumpTargetMM(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 1;
Inst.addOperand(MCOperand::CreateImm(JumpOffset));
return MCDisassembler::Success;
}
Add disassembler to MIPS. Patch by Vladimir Medic. llvm-svn: 154935
2012-04-18 02:03:21 +08:00
static DecodeStatus DecodeSimm16(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Insn)));
return MCDisassembler::Success;
}
static DecodeStatus DecodeInsSize(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
// First we need to grab the pos(lsb) from MCInst.
int Pos = Inst.getOperand(2).getImm();
int Size = (int) Insn - Pos + 1;
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
return MCDisassembler::Success;
}
static DecodeStatus DecodeExtSize(MCInst &Inst,
unsigned Insn,
uint64_t Address,
const void *Decoder) {
int Size = (int) Insn + 1;
Inst.addOperand(MCOperand::CreateImm(SignExtend32<16>(Size)));
return MCDisassembler::Success;
}