maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/MC/AArch64/SVE/uabd.s

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

63 lines
2.5 KiB
ArmAsm
Raw Normal View History

[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD This patch implements the following varieties: - Unpredicated signed max, e.g. smax z0.h, z1.h, #-128 - Unpredicated signed min, e.g. smin z0.h, z1.h, #-128 - Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255 - Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255 - Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h - Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h - Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h - Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h - Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h - Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h llvm-svn: 336317
2018-07-05 15:54:10 +08:00
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+streaming-sve < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD This patch implements the following varieties: - Unpredicated signed max, e.g. smax z0.h, z1.h, #-128 - Unpredicated signed min, e.g. smin z0.h, z1.h, #-128 - Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255 - Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255 - Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h - Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h - Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h - Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h - Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h - Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h llvm-svn: 336317
2018-07-05 15:54:10 +08:00
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
[test] llvm/test/: change llvm-objdump single-dash long options to double-dash options As announced here: http://lists.llvm.org/pipermail/llvm-dev/2019-April/131786.html Grouped option syntax (POSIX Utility Conventions) does not play well with -long-option A subsequent change will reject -long-option.
2020-03-16 07:17:52 +08:00
// RUN: | llvm-objdump -d --mattr=+sve - | FileCheck %s --check-prefix=CHECK-INST
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD This patch implements the following varieties: - Unpredicated signed max, e.g. smax z0.h, z1.h, #-128 - Unpredicated signed min, e.g. smin z0.h, z1.h, #-128 - Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255 - Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255 - Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h - Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h - Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h - Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h - Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h - Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h llvm-svn: 336317
2018-07-05 15:54:10 +08:00
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sve < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
uabd z31.b, p7/m, z31.b, z31.b
// CHECK-INST: uabd z31.b, p7/m, z31.b, z31.b
// CHECK-ENCODING: [0xff,0x1f,0x0d,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD This patch implements the following varieties: - Unpredicated signed max, e.g. smax z0.h, z1.h, #-128 - Unpredicated signed min, e.g. smin z0.h, z1.h, #-128 - Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255 - Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255 - Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h - Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h - Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h - Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h - Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h - Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h llvm-svn: 336317
2018-07-05 15:54:10 +08:00
// CHECK-UNKNOWN: ff 1f 0d 04 <unknown>
uabd z31.h, p7/m, z31.h, z31.h
// CHECK-INST: uabd z31.h, p7/m, z31.h, z31.h
// CHECK-ENCODING: [0xff,0x1f,0x4d,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD This patch implements the following varieties: - Unpredicated signed max, e.g. smax z0.h, z1.h, #-128 - Unpredicated signed min, e.g. smin z0.h, z1.h, #-128 - Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255 - Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255 - Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h - Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h - Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h - Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h - Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h - Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h llvm-svn: 336317
2018-07-05 15:54:10 +08:00
// CHECK-UNKNOWN: ff 1f 4d 04 <unknown>
uabd z31.s, p7/m, z31.s, z31.s
// CHECK-INST: uabd z31.s, p7/m, z31.s, z31.s
// CHECK-ENCODING: [0xff,0x1f,0x8d,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD This patch implements the following varieties: - Unpredicated signed max, e.g. smax z0.h, z1.h, #-128 - Unpredicated signed min, e.g. smin z0.h, z1.h, #-128 - Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255 - Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255 - Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h - Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h - Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h - Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h - Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h - Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h llvm-svn: 336317
2018-07-05 15:54:10 +08:00
// CHECK-UNKNOWN: ff 1f 8d 04 <unknown>
uabd z31.d, p7/m, z31.d, z31.d
// CHECK-INST: uabd z31.d, p7/m, z31.d, z31.d
// CHECK-ENCODING: [0xff,0x1f,0xcd,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Support for signed/unsigned MIN/MAX/ABD This patch implements the following varieties: - Unpredicated signed max, e.g. smax z0.h, z1.h, #-128 - Unpredicated signed min, e.g. smin z0.h, z1.h, #-128 - Unpredicated unsigned max, e.g. umax z0.h, z1.h, #255 - Unpredicated unsigned min, e.g. umin z0.h, z1.h, #255 - Predicated signed max, e.g. smax z0.h, p0/m, z0.h, z1.h - Predicated signed min, e.g. smin z0.h, p0/m, z0.h, z1.h - Predicated signed abd, e.g. sabd z0.h, p0/m, z0.h, z1.h - Predicated unsigned max, e.g. umax z0.h, p0/m, z0.h, z1.h - Predicated unsigned min, e.g. umin z0.h, p0/m, z0.h, z1.h - Predicated unsigned abd, e.g. uabd z0.h, p0/m, z0.h, z1.h llvm-svn: 336317
2018-07-05 15:54:10 +08:00
// CHECK-UNKNOWN: ff 1f cd 04 <unknown>
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// --------------------------------------------------------------------------//
// Test compatibility with MOVPRFX instruction.
movprfx z4.d, p7/z, z6.d
// CHECK-INST: movprfx z4.d, p7/z, z6.d
// CHECK-ENCODING: [0xc4,0x3c,0xd0,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// CHECK-UNKNOWN: c4 3c d0 04 <unknown>
uabd z4.d, p7/m, z4.d, z31.d
// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// CHECK-UNKNOWN: e4 1f cd 04 <unknown>
movprfx z4, z6
// CHECK-INST: movprfx z4, z6
// CHECK-ENCODING: [0xc4,0xbc,0x20,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// CHECK-UNKNOWN: c4 bc 20 04 <unknown>
uabd z4.d, p7/m, z4.d, z31.d
// CHECK-INST: uabd z4.d, p7/m, z4.d, z31.d
// CHECK-ENCODING: [0xe4,0x1f,0xcd,0x04]
[AArch64][SME] Introduce feature for streaming mode The Scalable Matrix Extension (SME) introduces a new execution mode called Streaming SVE mode. In streaming mode a substantial subset of the SVE and SVE2 instruction set is available, along with new outer product, load, store, extract and insert instructions that operate on the new architectural register state for the matrix. To support streaming mode this patch introduces a new subtarget feature +streaming-sve. If enabled, the subset of SVE(2) instructions are available. The existing behaviour for SVE(2) remains unchanged, the subset of instructions that are legal in streaming mode are enabled if either +sve[2] or +streaming-sve is specified. Instructions that are illegal in streaming mode remain predicated on +sve[2]. The SME target feature has been updated to imply +streaming-sve rather than +sve. The following changes are made to the SVE(2) tests: * For instructions that are legal in streaming mode: - added RUN line to verify +streaming-sve enables the instruction. - updated diagnostic to 'instruction requires: streaming-sve or sve'. * For instructions that are illegal in streaming-mode: - added RUN line to verify +streaming-sve does not enable the instruction. SVE(2) instructions that are legal in streaming mode have: if !HaveSVE[2]() && !HaveSME() then UNDEFINED; at the top of the pseudocode in the XML. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2021-06/SVE-Instructions Reviewed By: sdesmalen, david-arm Differential Revision: https://reviews.llvm.org/D106272
2021-07-30 15:30:45 +08:00
// CHECK-ERROR: instruction requires: streaming-sve or sve
[AArch64][SVE] Asm: Enable instructions to be prefixed. This patch enables instructions that are destructive on their destination- and first source operand, to be prefixed with a MOVPRFX instruction. This patch also adds a variety of tests: - positive tests for all instructions and forms that accept a movprfx for either or both predicated and unpredicated forms. - negative tests for all instructions and forms that do not accept an unpredicated or predicated movprfx. - negative tests for the diagnostics that get emitted when a MOVPRFX instruction is used incorrectly. This is patch [2/2] in a series to add MOVPRFX instructions: - Patch [1/2]: https://reviews.llvm.org/D49592 - Patch [2/2]: https://reviews.llvm.org/D49593 Reviewers: rengolin, SjoerdMeijer, samparker, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D49593 llvm-svn: 338261
2018-07-31 00:05:45 +08:00
// CHECK-UNKNOWN: e4 1f cd 04 <unknown>