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llvm-project/llvm/test/CodeGen/AArch64/large-frame.ll

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Add explicit triples to AArch64 tests Only Linux is supported at the moment, and other platforms quickly fault. As a result these tests would fail on non-Linux hosts. It may be worth making the tests more generic again as more platforms are supported. llvm-svn: 174170
2013-02-01 19:40:47 +08:00
; RUN: llc -verify-machineinstrs -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
Add AArch64 as an experimental target. This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
2013-01-31 20:12:40 +08:00
declare void @use_addr(i8*)
@addr = global i8* null
define void @test_bigframe() {
; CHECK: test_bigframe:
%var1 = alloca i8, i32 20000000
%var2 = alloca i8, i32 16
%var3 = alloca i8, i32 20000000
; CHECK: sub sp, sp, #496
; CHECK: str x30, [sp, #488]
; CHECK: ldr [[FRAMEOFFSET:x[0-9]+]], [[FRAMEOFFSET_CPI:.LCPI0_[0-9]+]]
; CHECK: sub sp, sp, [[FRAMEOFFSET]]
; CHECK: ldr [[VAR1OFFSET:x[0-9]+]], [[VAR1LOC_CPI:.LCPI0_[0-9]+]]
; CHECK: add {{x[0-9]+}}, sp, [[VAR1OFFSET]]
store volatile i8* %var1, i8** @addr
%var1plus2 = getelementptr i8* %var1, i32 2
store volatile i8* %var1plus2, i8** @addr
; CHECK: ldr [[VAR2OFFSET:x[0-9]+]], [[VAR2LOC_CPI:.LCPI0_[0-9]+]]
; CHECK: add {{x[0-9]+}}, sp, [[VAR2OFFSET]]
store volatile i8* %var2, i8** @addr
%var2plus2 = getelementptr i8* %var2, i32 2
store volatile i8* %var2plus2, i8** @addr
store volatile i8* %var3, i8** @addr
%var3plus2 = getelementptr i8* %var3, i32 2
store volatile i8* %var3plus2, i8** @addr
; CHECK: ldr [[FRAMEOFFSET:x[0-9]+]], [[FRAMEOFFSET_CPI]]
; CHECK: add sp, sp, [[FRAMEOFFSET]]
ret void
; CHECK: [[FRAMEOFFSET_CPI]]:
; CHECK-NEXT: 39999536
; CHECK: [[VAR1LOC_CPI]]:
; CHECK-NEXT: 20000024
; CHECK: [[VAR2LOC_CPI]]:
; CHECK-NEXT: 20000008
}
define void @test_mediumframe() {
; CHECK: test_mediumframe:
%var1 = alloca i8, i32 1000000
%var2 = alloca i8, i32 16
%var3 = alloca i8, i32 1000000
; CHECK: sub sp, sp, #496
; CHECK: str x30, [sp, #488]
; CHECK: sub sp, sp, #688
; CHECK-NEXT: sub sp, sp, #488, lsl #12
store volatile i8* %var1, i8** @addr
; CHECK: add [[VAR1ADDR:x[0-9]+]], sp, #600
; CHECK: add [[VAR1ADDR]], [[VAR1ADDR]], #244, lsl #12
%var1plus2 = getelementptr i8* %var1, i32 2
store volatile i8* %var1plus2, i8** @addr
; CHECK: add [[VAR1PLUS2:x[0-9]+]], {{x[0-9]+}}, #2
store volatile i8* %var2, i8** @addr
; CHECK: add [[VAR2ADDR:x[0-9]+]], sp, #584
; CHECK: add [[VAR2ADDR]], [[VAR2ADDR]], #244, lsl #12
%var2plus2 = getelementptr i8* %var2, i32 2
store volatile i8* %var2plus2, i8** @addr
; CHECK: add [[VAR2PLUS2:x[0-9]+]], {{x[0-9]+}}, #2
store volatile i8* %var3, i8** @addr
%var3plus2 = getelementptr i8* %var3, i32 2
store volatile i8* %var3plus2, i8** @addr
; CHECK: add sp, sp, #688
; CHECK: add sp, sp, #488, lsl #12
; CHECK: ldr x30, [sp, #488]
; CHECK: add sp, sp, #496
ret void
}
@bigspace = global [8 x i64] zeroinitializer
; If temporary registers are allocated for adjustment, they should *not* clobber
; argument registers.
define void @test_tempallocation([8 x i64] %val) nounwind {
; CHECK: test_tempallocation:
%var = alloca i8, i32 1000000
; CHECK: sub sp, sp,
; Make sure the prologue is reasonably efficient
; CHECK-NEXT: stp x29, x30, [sp,
; CHECK-NEXT: stp x25, x26, [sp,
; CHECK-NEXT: stp x23, x24, [sp,
; CHECK-NEXT: stp x21, x22, [sp,
; CHECK-NEXT: stp x19, x20, [sp,
; Make sure we don't trash an argument register
; CHECK-NOT: ldr {{x[0-7]}}, .LCPI1
; CHECK: sub sp, sp,
; CHECK-NOT: ldr {{x[0-7]}}, .LCPI1
; CHECK: bl use_addr
call void @use_addr(i8* %var)
store [8 x i64] %val, [8 x i64]* @bigspace
ret void
; CHECK: ret
}