forked from OSchip/llvm-project
24 lines
831 B
LLVM
24 lines
831 B
LLVM
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; RUN: llc -mcpu=hexagonv5 < %s
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; REQUIRES: asserts
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target datalayout = "e-m:e-p:32:32-i1:32-i64:64-a:0-v32:32-n16:32"
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target triple = "hexagon-unknown--elf"
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; Function Attrs: nounwind readnone
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define i64 @foo() #0 {
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entry:
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%0 = tail call i32 @llvm.hexagon.S2.clbp(i64 291)
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%1 = tail call i64 @llvm.hexagon.A4.combineir(i32 0, i32 %0)
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ret i64 %1
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}
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; Function Attrs: nounwind readnone
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declare i32 @llvm.hexagon.S2.clbp(i64) #1
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; Function Attrs: nounwind readnone
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declare i64 @llvm.hexagon.A4.combineir(i32, i32) #1
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attributes #0 = { nounwind readnone "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { nounwind readnone }
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