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llvm-project/llvm/test/CodeGen/ARM/uxt_rot.ll

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[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
; RUN: llc -mtriple=arm-eabi -mattr=+v6 %s -o - | FileCheck %s --check-prefix=CHECK-V6
; RUN: llc -mtriple=arm-eabi -mattr=+v7 %s -o - | FileCheck %s --check-prefix=CHECK-V7
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 11:14:27 +08:00
define zeroext i8 @test1(i32 %A.u) {
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
; CHECK-LABEL: test1
; CHECK-V6: uxtb
; CHECK-V7: uxtb
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
%B.u = trunc i32 %A.u to i8
ret i8 %B.u
}
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 11:14:27 +08:00
define zeroext i32 @test2(i32 %A.u, i32 %B.u) {
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
; CHECK-LABEL: test2
; CHECK-V6: uxtab r0, r0, r1
; CHECK-V7: uxtab r0, r0, r1
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
%C.u = trunc i32 %B.u to i8
%D.u = zext i8 %C.u to i32
%E.u = add i32 %A.u, %D.u
ret i32 %E.u
}
manually upgrade a bunch of tests to modern syntax, and remove some that are either unreduced or only test old syntax. llvm-svn: 133228
2011-06-17 11:14:27 +08:00
define zeroext i32 @test3(i32 %A.u) {
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
; CHECK-LABEL: test3
; CHECK-V6-NOT: ubfx
; CHECK-V7: ubfx r0, r0, #8, #16
Changes to support making the shift instructions be true BinaryOperators. This feature is needed in order to support shifts of more than 255 bits on large integer types. This changes the syntax for llvm assembly to make shl, ashr and lshr instructions look like a binary operator: shl i32 %X, 1 instead of shl i32 %X, i8 1 Additionally, this should help a few passes perform additional optimizations. llvm-svn: 33776
2007-02-02 10:16:23 +08:00
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
ARM test cases contributed by Apple. llvm-svn: 33354
2007-01-19 17:20:23 +08:00
%D.u = or i32 %B.u, %C.u
%E.u = trunc i32 %D.u to i16
%F.u = zext i16 %E.u to i32
ret i32 %F.u
}
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
define zeroext i32 @test4(i32 %A.u) {
; CHECK-LABEL: test4
; CHECK-V6-NOT: ubfx
; CHECK-V7: ubfx r0, r0, #8, #8
%B.u = lshr i32 %A.u, 8
%C.u = shl i32 %A.u, 24
%D.u = or i32 %B.u, %C.u
%E.u = trunc i32 %D.u to i8
%F.u = zext i8 %E.u to i32
ret i32 %F.u
}
define zeroext i16 @test5(i32 %A.u) {
; CHECK-LABEL: test5
; CHECK-V6: uxth
; CHECK-V7: uxth
%B.u = trunc i32 %A.u to i16
ret i16 %B.u
}
define zeroext i32 @test6(i32 %A.u, i32 %B.u) {
; CHECK-LABEL: test6
; CHECK-V6: uxtah r0, r0, r1
; CHECK-V7: uxtah r0, r0, r1
%C.u = trunc i32 %B.u to i16
%D.u = zext i16 %C.u to i32
%E.u = add i32 %A.u, %D.u
ret i32 %E.u
}
define zeroext i32 @test7(i32 %A, i32 %X) {
; CHECK-LABEL: test7
; CHECK-V6: uxtab r0, r1, r0, ror #8
; CHECK-V7: uxtab r0, r1, r0, ror #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
%E = trunc i32 %D to i8
%F = zext i8 %E to i32
%G = add i32 %F, %X
ret i32 %G
}
define zeroext i32 @test8(i32 %A, i32 %X) {
; CHECK-LABEL: test8
; CHECK-V6: uxtab r0, r1, r0, ror #16
; CHECK-V7: uxtab r0, r1, r0, ror #16
%B = lshr i32 %A, 16
%C = shl i32 %A, 16
%D = or i32 %B, %C
%E = trunc i32 %D to i8
%F = zext i8 %E to i32
%G = add i32 %F, %X
ret i32 %G
}
define zeroext i32 @test9(i32 %A, i32 %X) {
; CHECK-LABEL: test9
; CHECK-V6: uxtah r0, r1, r0, ror #8
; CHECK-V7: uxtah r0, r1, r0, ror #8
%B = lshr i32 %A, 8
%C = shl i32 %A, 24
%D = or i32 %B, %C
%E = trunc i32 %D to i16
%F = zext i16 %E to i32
%G = add i32 %F, %X
ret i32 %G
}
define zeroext i32 @test10(i32 %A, i32 %X) {
; CHECK-LABEL: test10
; CHECK-V6: uxtah r0, r1, r0, ror #24
; CHECK-V7: uxtah r0, r1, r0, ror #24
%B = lshr i32 %A, 24
%C = shl i32 %A, 8
%D = or i32 %B, %C
%E = trunc i32 %D to i16
%F = zext i16 %E to i32
%G = add i32 %F, %X
ret i32 %G
}
define zeroext i32 @test11(i32 %A, i32 %X) {
; CHECK-LABEL: test11
; CHECK-V6: uxtab r0, r1, r0
; CHECK-V7: uxtab r0, r1, r0
%B = and i32 %A, 255
%add = add i32 %X, %B
ret i32 %add
}
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
define zeroext i32 @test12(i32 %A, i32 %X) {
; CHECK-LABEL: test12
; CHECK-V6: uxtab r0, r1, r0, ror #8
; CHECK-V7: uxtab r0, r1, r0, ror #8
%B = lshr i32 %A, 8
%and = and i32 %B, 255
%add = add i32 %and, %X
ret i32 %add
}
define zeroext i32 @test13(i32 %A, i32 %X) {
; CHECK-LABEL: test13
; CHECK-V6: uxtab r0, r1, r0, ror #16
; CHECK-V7: uxtab r0, r1, r0, ror #16
%B = lshr i32 %A, 16
%and = and i32 %B, 255
%add = add i32 %and, %X
ret i32 %add
}
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
define zeroext i32 @test14(i32 %A, i32 %X) {
; CHECK-LABEL: test14
; CHECK-V6: uxtah r0, r1, r0
; CHECK-V7: uxtah r0, r1, r0
%B = and i32 %A, 65535
%add = add i32 %X, %B
ret i32 %add
}
ARM: fixup more tests to specify the target more explicitly This changes the tests that were targeting ARM EABI to explicitly specify the environment rather than relying on the default. This breaks with the new Windows on ARM support when running the tests on Windows where the default environment is no longer EABI. Take the opportunity to avoid a pointless redirect (helps when trying to debug with providing a command line invocation which can be copy and pasted) and removing a few greps in favour of FileCheck. llvm-svn: 205541
2014-04-04 00:01:44 +08:00
[ARM] Improve sxta{b|h} and uxta{b|h} tests Created a Thumb2 predicated pattern matcher that uses Thumb2 and HasT2ExtractPack and used it to redefine the patterns for sxta{b|h} and uxta{b|h}. Also used the similar patterns to fill in isel pattern gaps for the corresponding instructions in the ARM backend. The patch is mainly changes to tests since most of this functionality appears not to have been tested. Differential Revision: https://reviews.llvm.org/D23273 llvm-svn: 278207
2016-08-10 17:34:34 +08:00
define zeroext i32 @test15(i32 %A, i32 %X) {
; CHECK-LABEL: test15
; CHECK-V6: uxtah r0, r1, r0, ror #8
; CHECK-V7: uxtah r0, r1, r0, ror #8
%B = lshr i32 %A, 8
%and = and i32 %B, 65535
%add = add i32 %and, %X
ret i32 %add
}
define zeroext i32 @test16(i32 %A, i32 %X) {
; CHECK-LABEL: test16
; CHECK-V6: uxtah r0, r1, r0, ror #24
; CHECK-V7: uxtah r0, r1, r0, ror #24
%B = lshr i32 %A, 24
%C = shl i32 %A, 8
%D = or i32 %B, %C
%E = and i32 %D, 65535
%F = add i32 %E, %X
ret i32 %F
}