2016-08-01 05:55:33 +08:00
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|
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=corei7 | FileCheck %s --check-prefix=SSE
|
2012-08-15 05:24:47 +08:00
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|
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; RUN: llc < %s -mtriple=x86_64-pc-linux -mcpu=core-avx-i | FileCheck %s --check-prefix=AVX
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define <2 x double> @v2f2d_ext_vec(<2 x float> %v1) nounwind {
|
2016-08-01 05:55:33 +08:00
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|
|
; SSE-LABEL: v2f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
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; SSE: # %bb.0: # %entry
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2016-08-01 05:55:33 +08:00
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; SSE-NEXT: cvtps2pd %xmm0, %xmm0
|
|
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; SSE-NEXT: retq
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;
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; AVX-LABEL: v2f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
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; AVX: # %bb.0: # %entry
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2016-08-01 05:55:33 +08:00
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|
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; AVX-NEXT: vcvtps2pd %xmm0, %xmm0
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; AVX-NEXT: retq
|
2012-08-15 05:24:47 +08:00
|
|
|
entry:
|
|
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|
%f1 = fpext <2 x float> %v1 to <2 x double>
|
|
|
|
ret <2 x double> %f1
|
|
|
|
}
|
|
|
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|
|
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|
define <3 x double> @v3f2d_ext_vec(<3 x float> %v1) nounwind {
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-LABEL: v3f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0: # %entry
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: cvtps2pd %xmm0, %xmm2
|
2016-08-22 20:56:54 +08:00
|
|
|
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: cvtps2pd %xmm0, %xmm0
|
|
|
|
; SSE-NEXT: movlps %xmm0, -{{[0-9]+}}(%rsp)
|
2016-08-22 20:56:54 +08:00
|
|
|
; SSE-NEXT: movaps %xmm2, %xmm1
|
[MachineCopyPropagation] Extend pass to do COPY source forwarding
Summary:
This change extends MachineCopyPropagation to do COPY source forwarding
and adds an additional run of the pass to the default pass pipeline just
after register allocation.
This version of this patch uses the newly added
MachineOperand::isRenamable bit to avoid forwarding registers is such a
way as to violate constraints that aren't captured in the
Machine IR (e.g. ABI or ISA constraints).
This change is a continuation of the work started in D30751.
Reviewers: qcolombet, javed.absar, MatzeB, jonpa, tstellar
Subscribers: tpr, mgorny, mcrosier, nhaehnle, nemanjai, jyknight, hfinkel, arsenm, inouehrs, eraman, sdardis, guyblank, fedor.sergeev, aheejin, dschuff, jfb, myatsina, llvm-commits
Differential Revision: https://reviews.llvm.org/D41835
llvm-svn: 323991
2018-02-02 02:54:01 +08:00
|
|
|
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm2[1],xmm1[1]
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: fldl -{{[0-9]+}}(%rsp)
|
2016-08-22 20:56:54 +08:00
|
|
|
; SSE-NEXT: movaps %xmm2, %xmm0
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: v3f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0: # %entry
|
2016-08-01 05:55:33 +08:00
|
|
|
; AVX-NEXT: vcvtps2pd %xmm0, %ymm0
|
|
|
|
; AVX-NEXT: retq
|
2012-08-15 05:24:47 +08:00
|
|
|
entry:
|
|
|
|
%f1 = fpext <3 x float> %v1 to <3 x double>
|
|
|
|
ret <3 x double> %f1
|
|
|
|
}
|
|
|
|
|
|
|
|
define <4 x double> @v4f2d_ext_vec(<4 x float> %v1) nounwind {
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-LABEL: v4f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0: # %entry
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: cvtps2pd %xmm0, %xmm2
|
2016-08-22 20:56:54 +08:00
|
|
|
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: cvtps2pd %xmm0, %xmm1
|
|
|
|
; SSE-NEXT: movaps %xmm2, %xmm0
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: v4f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0: # %entry
|
2016-08-01 05:55:33 +08:00
|
|
|
; AVX-NEXT: vcvtps2pd %xmm0, %ymm0
|
|
|
|
; AVX-NEXT: retq
|
2012-08-15 05:24:47 +08:00
|
|
|
entry:
|
|
|
|
%f1 = fpext <4 x float> %v1 to <4 x double>
|
|
|
|
ret <4 x double> %f1
|
|
|
|
}
|
|
|
|
|
|
|
|
define <8 x double> @v8f2d_ext_vec(<8 x float> %v1) nounwind {
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-LABEL: v8f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0: # %entry
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: cvtps2pd %xmm0, %xmm5
|
|
|
|
; SSE-NEXT: cvtps2pd %xmm1, %xmm2
|
2016-08-22 20:56:54 +08:00
|
|
|
; SSE-NEXT: movhlps {{.*#+}} xmm0 = xmm0[1,1]
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: cvtps2pd %xmm0, %xmm4
|
2016-08-22 20:56:54 +08:00
|
|
|
; SSE-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: cvtps2pd %xmm1, %xmm3
|
|
|
|
; SSE-NEXT: movaps %xmm5, %xmm0
|
|
|
|
; SSE-NEXT: movaps %xmm4, %xmm1
|
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: v8f2d_ext_vec:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0: # %entry
|
2016-08-01 05:55:33 +08:00
|
|
|
; AVX-NEXT: vcvtps2pd %xmm0, %ymm2
|
|
|
|
; AVX-NEXT: vextractf128 $1, %ymm0, %xmm0
|
|
|
|
; AVX-NEXT: vcvtps2pd %xmm0, %ymm1
|
|
|
|
; AVX-NEXT: vmovaps %ymm2, %ymm0
|
|
|
|
; AVX-NEXT: retq
|
2012-08-15 05:24:47 +08:00
|
|
|
entry:
|
|
|
|
%f1 = fpext <8 x float> %v1 to <8 x double>
|
|
|
|
ret <8 x double> %f1
|
|
|
|
}
|
2012-08-21 01:59:18 +08:00
|
|
|
|
|
|
|
define void @test_vector_creation() nounwind {
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-LABEL: test_vector_creation:
|
2017-12-05 01:18:51 +08:00
|
|
|
; SSE: # %bb.0:
|
2017-02-15 19:46:15 +08:00
|
|
|
; SSE-NEXT: xorpd %xmm0, %xmm0
|
|
|
|
; SSE-NEXT: movhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
|
|
|
|
; SSE-NEXT: movapd %xmm0, (%rax)
|
2016-08-01 05:55:33 +08:00
|
|
|
; SSE-NEXT: retq
|
|
|
|
;
|
|
|
|
; AVX-LABEL: test_vector_creation:
|
2017-12-05 01:18:51 +08:00
|
|
|
; AVX: # %bb.0:
|
2017-02-15 19:46:15 +08:00
|
|
|
; AVX-NEXT: vxorpd %xmm0, %xmm0, %xmm0
|
|
|
|
; AVX-NEXT: vmovhpd {{.*#+}} xmm0 = xmm0[0],mem[0]
|
2016-08-01 05:55:33 +08:00
|
|
|
; AVX-NEXT: vinsertf128 $1, %xmm0, %ymm0, %ymm0
|
|
|
|
; AVX-NEXT: vmovaps %ymm0, (%rax)
|
|
|
|
; AVX-NEXT: vzeroupper
|
|
|
|
; AVX-NEXT: retq
|
2012-08-21 01:59:18 +08:00
|
|
|
%1 = insertelement <4 x double> undef, double 0.000000e+00, i32 2
|
2015-02-28 05:17:42 +08:00
|
|
|
%2 = load double, double addrspace(1)* null
|
2012-08-21 01:59:18 +08:00
|
|
|
%3 = insertelement <4 x double> %1, double %2, i32 3
|
|
|
|
store <4 x double> %3, <4 x double>* undef
|
|
|
|
ret void
|
|
|
|
}
|