2012-02-28 15:46:26 +08:00
|
|
|
//===-- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===//
|
2007-06-06 15:42:06 +08:00
|
|
|
//
|
|
|
|
// The LLVM Compiler Infrastructure
|
|
|
|
//
|
2007-12-30 04:36:04 +08:00
|
|
|
// This file is distributed under the University of Illinois Open Source
|
|
|
|
// License. See LICENSE.TXT for details.
|
2007-06-06 15:42:06 +08:00
|
|
|
//
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-18 10:18:07 +08:00
|
|
|
// This is the top level entry point for the Mips target.
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-08-18 10:18:07 +08:00
|
|
|
// Target-independent interfaces
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-11-24 15:34:46 +08:00
|
|
|
include "llvm/Target/Target.td"
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2014-05-07 18:27:09 +08:00
|
|
|
// The overall idea of the PredicateControl class is to chop the Predicates list
|
|
|
|
// into subsets that are usually overridden independently. This allows
|
|
|
|
// subclasses to partially override the predicates of their superclasses without
|
|
|
|
// having to re-add all the existing predicates.
|
|
|
|
class PredicateControl {
|
|
|
|
// Predicates for the encoding scheme in use such as HasStdEnc
|
|
|
|
list<Predicate> EncodingPredicates = [];
|
|
|
|
// Predicates for anything else
|
|
|
|
list<Predicate> AdditionalPredicates = [];
|
|
|
|
list<Predicate> Predicates = !listconcat(EncodingPredicates,
|
|
|
|
AdditionalPredicates);
|
|
|
|
}
|
|
|
|
|
|
|
|
// Like Requires<> but for the AdditionalPredicates list
|
|
|
|
class AdditionalRequires<list<Predicate> preds> {
|
|
|
|
list<Predicate> AdditionalPredicates = preds;
|
|
|
|
}
|
|
|
|
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
// Register File, Calling Conv, Instruction Descriptions
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
|
|
|
|
|
|
|
include "MipsRegisterInfo.td"
|
2007-08-18 10:18:07 +08:00
|
|
|
include "MipsSchedule.td"
|
2007-06-06 15:42:06 +08:00
|
|
|
include "MipsInstrInfo.td"
|
2007-08-18 10:18:07 +08:00
|
|
|
include "MipsCallingConv.td"
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2010-04-05 11:10:20 +08:00
|
|
|
def MipsInstrInfo : InstrInfo;
|
2007-08-18 10:18:07 +08:00
|
|
|
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Mips Subtarget features //
|
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2008-07-09 13:32:22 +08:00
|
|
|
def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true",
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
"General Purpose Registers are 64-bit wide.">;
|
2008-07-09 13:32:22 +08:00
|
|
|
def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true",
|
2013-10-30 10:29:43 +08:00
|
|
|
"Support 64-bit FP registers.">;
|
2014-04-16 23:48:55 +08:00
|
|
|
def FeatureNaN2008 : SubtargetFeature<"nan2008", "IsNaN2008bit", "true",
|
|
|
|
"IEEE 754-2008 NaN encoding.">;
|
2008-07-09 13:32:22 +08:00
|
|
|
def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat",
|
2011-04-16 05:51:11 +08:00
|
|
|
"true", "Only supports single precision float">;
|
2008-07-09 13:32:22 +08:00
|
|
|
def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32",
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
"Enable o32 ABI">;
|
2011-09-21 04:28:08 +08:00
|
|
|
def FeatureN32 : SubtargetFeature<"n32", "MipsABI", "N32",
|
|
|
|
"Enable n32 ABI">;
|
|
|
|
def FeatureN64 : SubtargetFeature<"n64", "MipsABI", "N64",
|
|
|
|
"Enable n64 ABI">;
|
2008-07-09 13:32:22 +08:00
|
|
|
def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI",
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
"Enable eabi ABI">;
|
2010-11-09 05:42:32 +08:00
|
|
|
def FeatureVFPU : SubtargetFeature<"vfpu", "HasVFPU",
|
2008-07-09 13:32:22 +08:00
|
|
|
"true", "Enable vector FPU instructions.">;
|
2010-11-09 05:42:32 +08:00
|
|
|
def FeatureSEInReg : SubtargetFeature<"seinreg", "HasSEInReg", "true",
|
2008-07-09 13:32:22 +08:00
|
|
|
"Enable 'signext in register' instructions.">;
|
2010-11-09 05:42:32 +08:00
|
|
|
def FeatureCondMov : SubtargetFeature<"condmov", "HasCondMov", "true",
|
2008-07-31 01:01:06 +08:00
|
|
|
"Enable 'conditional move' instructions.">;
|
|
|
|
def FeatureSwap : SubtargetFeature<"swap", "HasSwap", "true",
|
|
|
|
"Enable 'byte/half swap' instructions.">;
|
|
|
|
def FeatureBitCount : SubtargetFeature<"bitcount", "HasBitCount", "true",
|
|
|
|
"Enable 'count leading bits' instructions.">;
|
2014-04-10 21:16:49 +08:00
|
|
|
def FeatureFPIdx : SubtargetFeature<"fpidx", "HasFPIdx", "true",
|
2012-11-16 05:17:13 +08:00
|
|
|
"Enable 'FP indexed load/store' instructions.">;
|
2011-04-16 05:51:11 +08:00
|
|
|
def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32",
|
|
|
|
"Mips32 ISA Support",
|
2010-11-10 10:13:22 +08:00
|
|
|
[FeatureCondMov, FeatureBitCount]>;
|
2010-11-09 05:42:32 +08:00
|
|
|
def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion",
|
|
|
|
"Mips32r2", "Mips32r2 ISA Support",
|
2012-11-16 05:17:13 +08:00
|
|
|
[FeatureMips32, FeatureSEInReg, FeatureSwap,
|
|
|
|
FeatureFPIdx]>;
|
2014-04-03 20:13:36 +08:00
|
|
|
def FeatureMips4 : SubtargetFeature<"mips4", "MipsArchVersion",
|
|
|
|
"Mips4", "MIPS IV ISA Support",
|
2014-04-10 21:16:49 +08:00
|
|
|
[FeatureGP64Bit, FeatureFP64Bit, FeatureFPIdx,
|
2014-04-03 20:13:36 +08:00
|
|
|
FeatureCondMov]>;
|
2011-09-21 04:28:08 +08:00
|
|
|
def FeatureMips64 : SubtargetFeature<"mips64", "MipsArchVersion",
|
|
|
|
"Mips64", "Mips64 ISA Support",
|
2014-04-03 20:13:36 +08:00
|
|
|
[FeatureMips4, FeatureMips32, FeatureFPIdx]>;
|
2011-09-21 04:28:08 +08:00
|
|
|
def FeatureMips64r2 : SubtargetFeature<"mips64r2", "MipsArchVersion",
|
|
|
|
"Mips64r2", "Mips64r2 ISA Support",
|
|
|
|
[FeatureMips64, FeatureMips32r2]>;
|
2007-06-06 15:42:06 +08:00
|
|
|
|
2012-05-17 06:19:56 +08:00
|
|
|
def FeatureMips16 : SubtargetFeature<"mips16", "InMips16Mode", "true",
|
|
|
|
"Mips16 mode">;
|
|
|
|
|
2012-09-22 07:41:49 +08:00
|
|
|
def FeatureDSP : SubtargetFeature<"dsp", "HasDSP", "true", "Mips DSP ASE">;
|
|
|
|
def FeatureDSPR2 : SubtargetFeature<"dspr2", "HasDSPR2", "true",
|
|
|
|
"Mips DSP-R2 ASE", [FeatureDSP]>;
|
|
|
|
|
2013-08-14 04:54:07 +08:00
|
|
|
def FeatureMSA : SubtargetFeature<"msa", "HasMSA", "true", "Mips MSA ASE">;
|
|
|
|
|
2013-02-05 17:30:03 +08:00
|
|
|
def FeatureMicroMips : SubtargetFeature<"micromips", "InMicroMipsMode", "true",
|
|
|
|
"microMips mode">;
|
|
|
|
|
2014-03-20 19:51:58 +08:00
|
|
|
def FeatureCnMips : SubtargetFeature<"cnmips", "HasCnMips",
|
|
|
|
"true", "Octeon cnMIPS Support",
|
|
|
|
[FeatureMips64r2]>;
|
|
|
|
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
|
|
|
// Mips processors supported.
|
2011-04-16 05:51:11 +08:00
|
|
|
//===----------------------------------------------------------------------===//
|
2007-06-06 15:42:06 +08:00
|
|
|
|
Several changes to Mips backend, experimental fp support being the most
important.
- Cleanup in the Subtarget info with addition of new features, not all support
yet, but they allow the future inclusion of features easier. Among new features,
we have : Arch family info (mips1, mips2, ...), ABI info (o32, eabi), 64-bit
integer
and float registers, allegrex vector FPU (VFPU), single float only support.
- TargetMachine now detects allegrex core.
- Added allegrex (Mips32r2) sext_inreg instructions.
- *Added Float Point Instructions*, handling single float only, and
aliased accesses for 32-bit FPUs.
- Some cleanup in FP instruction formats and FP register classes.
- Calling conventions improved to support mips 32-bit EABI.
- Added Asm Printer support for fp cond codes.
- Added support for sret copy to a return register.
- EABI support added into LowerCALL and FORMAL_ARGS.
- MipsFunctionInfo now keeps a virtual register per function to track the
sret on function entry until function ret.
- MipsInstrInfo FP support into methods (isMoveInstr, isLoadFromStackSlot, ...),
FP cond codes mapping and initial FP Branch Analysis.
- Two new Mips SDNode to handle fp branch and compare instructions : FPBrcond,
FPCmp
- MipsTargetLowering : handling different FP classes, Allegrex support, sret
return copy, no homing location within EABI, non 32-bit stack objects
arguments, and asm constraint for float.
llvm-svn: 53146
2008-07-06 03:05:21 +08:00
|
|
|
class Proc<string Name, list<SubtargetFeature> Features>
|
|
|
|
: Processor<Name, MipsGenericItineraries, Features>;
|
|
|
|
|
2014-02-20 22:58:19 +08:00
|
|
|
def : Proc<"mips32", [FeatureMips32, FeatureO32]>;
|
|
|
|
def : Proc<"mips32r2", [FeatureMips32r2, FeatureO32]>;
|
2014-04-03 20:13:36 +08:00
|
|
|
def : Proc<"mips4", [FeatureMips4, FeatureN64]>;
|
2014-02-20 22:58:19 +08:00
|
|
|
def : Proc<"mips64", [FeatureMips64, FeatureN64]>;
|
|
|
|
def : Proc<"mips64r2", [FeatureMips64r2, FeatureN64]>;
|
|
|
|
def : Proc<"mips16", [FeatureMips16, FeatureO32]>;
|
2014-03-20 19:51:58 +08:00
|
|
|
def : Proc<"octeon", [FeatureMips64r2, FeatureN64, FeatureCnMips]>;
|
2010-11-09 05:42:32 +08:00
|
|
|
|
2012-08-18 04:16:42 +08:00
|
|
|
def MipsAsmParser : AsmParser {
|
|
|
|
let ShouldEmitMatchRegisterName = 0;
|
2013-08-01 17:25:27 +08:00
|
|
|
let MnemonicContainsDot = 1;
|
2012-08-18 04:16:42 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
def MipsAsmParserVariant : AsmParserVariant {
|
|
|
|
int Variant = 0;
|
|
|
|
|
|
|
|
// Recognize hard coded registers.
|
|
|
|
string RegisterPrefix = "$";
|
|
|
|
}
|
|
|
|
|
2007-06-06 15:42:06 +08:00
|
|
|
def Mips : Target {
|
|
|
|
let InstructionSet = MipsInstrInfo;
|
2012-08-18 04:16:42 +08:00
|
|
|
let AssemblyParsers = [MipsAsmParser];
|
|
|
|
let AssemblyParserVariants = [MipsAsmParserVariant];
|
2007-06-06 15:42:06 +08:00
|
|
|
}
|