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llvm-project/llvm/test/CodeGen/SystemZ/int-cmp-51.ll

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[SystemZ] Make the CCRegs regclass non-allocatable. This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
2015-10-30 00:13:55 +08:00
; Check that modelling of CC/CCRegs does not stop MachineCSE from
; removing a compare. MachineCSE will not extend a live range of an
; allocatable or reserved phys reg.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
declare void @bar(i8)
; Check the low end of the CH range.
define void @f1(i32 %lhs) {
[CodeGen] Unify MBB reference format in both MIR and debug output As part of the unification of the debug format and the MIR format, print MBB references as '%bb.5'. The MIR printer prints the IR name of a MBB only for block definitions. * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)->getNumber\(\)/" << printMBBReference(*\1)/g' * find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#" << ([a-zA-Z0-9_]+)\.getNumber\(\)/" << printMBBReference(\1)/g' * find . \( -name "*.txt" -o -name "*.s" -o -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E 's/BB#([0-9]+)/%bb.\1/g' * grep -nr 'BB#' and fix Differential Revision: https://reviews.llvm.org/D40422 llvm-svn: 319665
2017-12-05 01:18:51 +08:00
; CHECK-LABEL: %bb.1:
[SystemZ] Make the CCRegs regclass non-allocatable. This was discovered to be necessary while running memchr-01.ll with -verify-machinstrs, because it is not allowed to have a phys reg live accross block boundaries while on SSA form, if the register is allocatable (expect in entry block and landing pads). In this test case, stringRRE pseudos are expanded after isel by adding a loop block which produces a live out CC register. To make the test pass, it was also necessary to not say that StringRRELoop pseudo uses R0L, this is only true for the StringRRE opcode. -verify-machineinstrs added to memchr-01.ll test. New test case int-cmp-51.ll to test that MachineCSE can eliminate an identical compare (which it couldn't do before). Reviewed by Ulrich Weigand llvm-svn: 251634
2015-10-30 00:13:55 +08:00
; CHECK-NOT: cijlh %r0, 1, .LBB0_3
entry:
%and188 = and i32 %lhs, 255
%cmp189 = icmp ult i32 %and188, 2
br i1 %cmp189, label %if.then.191, label %if.else.201
if.then.191:
%cmp194 = icmp eq i32 %and188, 1
br i1 %cmp194, label %if.then.196, label %if.else.198
if.then.196:
call void @bar(i8 1);
br label %if.else.201
if.else.198:
call void @bar(i8 0);
br label %if.else.201
if.else.201:
ret void
}