2013-05-07 00:17:29 +08:00
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; Test 64-bit comparisons in which the second operand is zero-extended
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; from a PC-relative i16.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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@g = global i16 1
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2013-05-30 17:45:42 +08:00
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@h = global i16 1, align 1, section "foo"
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2013-05-07 00:17:29 +08:00
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; Check unsigned comparison.
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define i64 @f1(i64 %src1) {
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2013-07-14 14:24:09 +08:00
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; CHECK-LABEL: f1:
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2020-08-18 02:42:57 +08:00
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; CHECK: clghrl %r2, g
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; CHECK-NEXT: jl
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; CHECK: br %r14
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2013-05-07 00:17:29 +08:00
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entry:
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2018-07-20 20:12:10 +08:00
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%val = load i16, i16 *@g
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2013-05-07 00:17:29 +08:00
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%src2 = zext i16 %val to i64
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2017-01-12 03:55:19 +08:00
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%cond = icmp ult i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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2013-05-07 00:17:29 +08:00
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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2016-04-08 00:11:44 +08:00
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%tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i64 %tmp, 1
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2013-05-07 00:17:29 +08:00
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ret i64 %res
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}
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; Check signed comparison.
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define i64 @f2(i64 %src1) {
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2013-07-14 14:24:09 +08:00
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; CHECK-LABEL: f2:
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2020-08-18 02:42:57 +08:00
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; CHECK-NOT: clghrl
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; CHECK: br %r14
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2013-05-07 00:17:29 +08:00
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entry:
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2018-07-20 20:12:10 +08:00
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%val = load i16, i16 *@g
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2013-05-07 00:17:29 +08:00
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%src2 = zext i16 %val to i64
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%cond = icmp slt i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
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2016-04-08 00:11:44 +08:00
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%tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i64 %tmp, 1
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2013-05-07 00:17:29 +08:00
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ret i64 %res
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}
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; Check equality.
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define i64 @f3(i64 %src1) {
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2013-07-14 14:24:09 +08:00
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; CHECK-LABEL: f3:
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2020-08-18 02:42:57 +08:00
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; CHECK: clghrl %r2, g
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; CHECK-NEXT: je
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; CHECK: br %r14
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2013-05-07 00:17:29 +08:00
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entry:
|
2018-07-20 20:12:10 +08:00
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%val = load i16, i16 *@g
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2013-05-07 00:17:29 +08:00
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%src2 = zext i16 %val to i64
|
2017-01-12 03:55:19 +08:00
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%cond = icmp eq i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
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2013-05-07 00:17:29 +08:00
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mulb:
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%mul = mul i64 %src1, %src1
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br label %exit
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exit:
|
2016-04-08 00:11:44 +08:00
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%tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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%res = add i64 %tmp, 1
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2013-05-07 00:17:29 +08:00
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ret i64 %res
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}
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; Check inequality.
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define i64 @f4(i64 %src1) {
|
2013-07-14 14:24:09 +08:00
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; CHECK-LABEL: f4:
|
2020-08-18 02:42:57 +08:00
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; CHECK: clghrl %r2, g
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; CHECK-NEXT: jlh
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; CHECK: br %r14
|
2013-05-07 00:17:29 +08:00
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entry:
|
2018-07-20 20:12:10 +08:00
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|
|
%val = load i16, i16 *@g
|
2013-05-07 00:17:29 +08:00
|
|
|
%src2 = zext i16 %val to i64
|
2017-01-12 03:55:19 +08:00
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|
%cond = icmp ne i64 %src1, %src2
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br i1 %cond, label %exit, label %mulb
|
2013-05-07 00:17:29 +08:00
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mulb:
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|
%mul = mul i64 %src1, %src1
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br label %exit
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exit:
|
2016-04-08 00:11:44 +08:00
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|
|
%tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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|
%res = add i64 %tmp, 1
|
2013-05-07 00:17:29 +08:00
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|
|
ret i64 %res
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|
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}
|
2013-05-30 17:45:42 +08:00
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|
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; Repeat f1 with an unaligned address.
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|
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define i64 @f5(i64 %src1) {
|
2013-07-14 14:24:09 +08:00
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|
; CHECK-LABEL: f5:
|
2020-08-18 02:42:57 +08:00
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|
|
; CHECK: lgrl [[REG:%r[0-5]]], h@GOT
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; CHECK: llgh [[VAL:%r[0-5]]], 0([[REG]])
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|
; CHECK: clgrjl %r2, [[VAL]],
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; CHECK: br %r14
|
2013-05-30 17:45:42 +08:00
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|
|
entry:
|
2018-07-20 20:12:10 +08:00
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|
|
%val = load i16, i16 *@h, align 1
|
2013-05-30 17:45:42 +08:00
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|
|
%src2 = zext i16 %val to i64
|
2017-01-12 03:55:19 +08:00
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|
|
%cond = icmp ult i64 %src1, %src2
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|
br i1 %cond, label %exit, label %mulb
|
2013-05-30 17:45:42 +08:00
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|
|
mulb:
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|
|
%mul = mul i64 %src1, %src1
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|
|
br label %exit
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|
exit:
|
2016-04-08 00:11:44 +08:00
|
|
|
%tmp = phi i64 [ %src1, %entry ], [ %mul, %mulb ]
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|
|
|
%res = add i64 %tmp, 1
|
2013-05-30 17:45:42 +08:00
|
|
|
ret i64 %res
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|
|
|
}
|
2013-08-23 19:27:19 +08:00
|
|
|
|
|
|
|
; Check the comparison can be reversed if that allows CLGHRL to be used.
|
|
|
|
define i64 @f6(i64 %src2) {
|
|
|
|
; CHECK-LABEL: f6:
|
2020-08-18 02:42:57 +08:00
|
|
|
; CHECK: clghrl %r2, g
|
|
|
|
; CHECK-NEXT: jh {{\.L.*}}
|
|
|
|
; CHECK: br %r14
|
2013-08-23 19:27:19 +08:00
|
|
|
entry:
|
2018-07-20 20:12:10 +08:00
|
|
|
%val = load i16, i16 *@g
|
2013-08-23 19:27:19 +08:00
|
|
|
%src1 = zext i16 %val to i64
|
2017-01-12 03:55:19 +08:00
|
|
|
%cond = icmp ult i64 %src1, %src2
|
|
|
|
br i1 %cond, label %exit, label %mulb
|
2013-08-23 19:27:19 +08:00
|
|
|
mulb:
|
|
|
|
%mul = mul i64 %src2, %src2
|
|
|
|
br label %exit
|
|
|
|
exit:
|
2016-04-08 00:11:44 +08:00
|
|
|
%tmp = phi i64 [ %src2, %entry ], [ %mul, %mulb ]
|
|
|
|
%res = add i64 %tmp, 1
|
2013-08-23 19:27:19 +08:00
|
|
|
ret i64 %res
|
|
|
|
}
|