maxjhandsome
/
llvm-project
forked from OSchip/llvm-project
1
0
Fork 0
Code Issues Pull Requests Packages Releases Wiki Activity
llvm-project/llvm/test/CodeGen/SystemZ/fp-mul-12.ll

Ignoring revisions in .git-blame-ignore-revs. Click here to bypass and see the normal blame view.

73 lines
2.5 KiB
LLVM
Raw Normal View History

[SystemZ] Add support for IBM z14 processor (3/3) This adds support for the new 128-bit vector float instructions of z14. Note that these instructions actually only operate on the f128 type, since only each 128-bit vector register can hold only one 128-bit float value. However, this is still preferable to the legacy 128-bit float instructions, since those operate on pairs of floating-point registers (so we can hold at most 8 values in registers), while the new instructions use single vector registers (so we hold up to 32 value in registers). Adding support includes: - Enabling the instructions for the assembler/disassembler. - CodeGen for the instructions. This includes allocating the f128 type now to the VR128BitRegClass instead of FP128BitRegClass. - Scheduler description support for the instructions. Note that for a small number of operations, we have no new vector instructions (like integer <-> 128-bit float conversions), and so we use the legacy instruction and then reformat the operand (i.e. copy between a pair of floating-point registers and a vector register). llvm-svn: 308196
2017-07-18 01:44:20 +08:00
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
declare fp128 @llvm.fma.f128(fp128 %f1, fp128 %f2, fp128 %f3)
define void @f1(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f1:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfmaxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %f3)
store fp128 %res, fp128 *%dst
ret void
}
define void @f2(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f2:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfmsxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%neg = fsub fp128 0xL00000000000000008000000000000000, %f3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %neg)
store fp128 %res, fp128 *%dst
ret void
}
define void @f3(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f3:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfnmaxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %f3)
%negres = fsub fp128 0xL00000000000000008000000000000000, %res
store fp128 %negres, fp128 *%dst
ret void
}
define void @f4(fp128 *%ptr1, fp128 *%ptr2, fp128 *%ptr3, fp128 *%dst) {
; CHECK-LABEL: f4:
; CHECK-DAG: vl [[REG1:%v[0-9]+]], 0(%r2)
; CHECK-DAG: vl [[REG2:%v[0-9]+]], 0(%r3)
; CHECK-DAG: vl [[REG3:%v[0-9]+]], 0(%r4)
; CHECK: wfnmsxb [[RES:%v[0-9]+]], [[REG1]], [[REG2]], [[REG3]]
; CHECK: vst [[RES]], 0(%r5)
; CHECK: br %r14
%f1 = load fp128, fp128 *%ptr1
%f2 = load fp128, fp128 *%ptr2
%f3 = load fp128, fp128 *%ptr3
%neg = fsub fp128 0xL00000000000000008000000000000000, %f3
%res = call fp128 @llvm.fma.f128 (fp128 %f1, fp128 %f2, fp128 %neg)
%negres = fsub fp128 0xL00000000000000008000000000000000, %res
store fp128 %negres, fp128 *%dst
ret void
}