forked from OSchip/llvm-project
216 lines
5.8 KiB
LLVM
216 lines
5.8 KiB
LLVM
|
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
|
||
|
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu -O2 \
|
||
|
|
; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
|
||
|
|
; RUN: --check-prefixes=CHECK,CHECK-LE
|
||
|
|
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu -O2 \
|
||
|
|
; RUN: -ppc-asm-full-reg-names -mcpu=pwr10 < %s | FileCheck %s \
|
||
|
|
; RUN: --check-prefixes=CHECK,CHECK-BE
|
||
|
|
|
||
|
|
; This file does not contain many test cases involving comparisons and logical
|
||
|
|
; comparisons (cmplwi, cmpldi). This is because alternative code is generated
|
||
|
|
; when there is a compare (logical or not), followed by a sign or zero extend.
|
||
|
|
; This codegen will be re-evaluated at a later time on whether or not it should
|
||
|
|
; be emitted on P10.
|
||
|
|
|
||
|
|
@globalVal = common local_unnamed_addr global i8 0, align 1
|
||
|
|
@globalVal2 = common local_unnamed_addr global i32 0, align 4
|
||
|
|
@globalVal3 = common local_unnamed_addr global i64 0, align 8
|
||
|
|
@globalVal4 = common local_unnamed_addr global i16 0, align 2
|
||
|
|
|
||
|
|
define signext i32 @setbcr1(i8 %a) {
|
||
|
|
; CHECK-LABEL: setbcr1:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: clrlwi r3, r3, 24
|
||
|
|
; CHECK-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i8 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i32
|
||
|
|
ret i32 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define signext i32 @setbcr2(i32 %a) {
|
||
|
|
; CHECK-LABEL: setbcr2:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i32 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i32
|
||
|
|
ret i32 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define signext i32 @setbcr3(i64 %a) {
|
||
|
|
; CHECK-LABEL: setbcr3:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: cmpdi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i64 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i32
|
||
|
|
ret i32 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define signext i32 @setbcr4(i16 %a) {
|
||
|
|
; CHECK-LABEL: setbcr4:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: clrlwi r3, r3, 16
|
||
|
|
; CHECK-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i16 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i32
|
||
|
|
ret i32 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define signext i64 @setbcr5(i8 %a) {
|
||
|
|
; CHECK-LABEL: setbcr5:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: clrlwi r3, r3, 24
|
||
|
|
; CHECK-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i8 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i64
|
||
|
|
ret i64 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define signext i64 @setbcr6(i32 %a) {
|
||
|
|
; CHECK-LABEL: setbcr6:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i32 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i64
|
||
|
|
ret i64 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define signext i64 @setbcr7(i64 %a) {
|
||
|
|
; CHECK-LABEL: setbcr7:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: cmpdi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i64 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i64
|
||
|
|
ret i64 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define signext i64 @setbcr8(i16 %a) {
|
||
|
|
; CHECK-LABEL: setbcr8:
|
||
|
|
; CHECK: # %bb.0: # %entry
|
||
|
|
; CHECK-NEXT: clrlwi r3, r3, 16
|
||
|
|
; CHECK-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i16 %a, 1
|
||
|
|
%conv = zext i1 %cmp to i64
|
||
|
|
ret i64 %conv
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @setbcr9(i8 %a) {
|
||
|
|
; CHECK-LE-LABEL: setbcr9:
|
||
|
|
; CHECK-LE: # %bb.0: # %entry
|
||
|
|
; CHECK-LE-NEXT: clrlwi r3, r3, 24
|
||
|
|
; CHECK-LE-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-LE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-LE-NEXT: pstb r3, globalVal@PCREL(0), 1
|
||
|
|
; CHECK-LE-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-LABEL: setbcr9:
|
||
|
|
; CHECK-BE: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NEXT: addis r4, r2, .LC0@toc@ha
|
||
|
|
; CHECK-BE-NEXT: clrlwi r3, r3, 24
|
||
|
|
; CHECK-BE-NEXT: ld r4, .LC0@toc@l(r4)
|
||
|
|
; CHECK-BE-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-BE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-BE-NEXT: stb r3, 0(r4)
|
||
|
|
; CHECK-BE-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i8 %a, 1
|
||
|
|
%conv1 = zext i1 %cmp to i8
|
||
|
|
store i8 %conv1, i8* @globalVal, align 1
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @setbcr10(i32 %a) {
|
||
|
|
; CHECK-LE-LABEL: setbcr10:
|
||
|
|
; CHECK-LE: # %bb.0: # %entry
|
||
|
|
; CHECK-LE-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-LE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-LE-NEXT: pstw r3, globalVal2@PCREL(0), 1
|
||
|
|
; CHECK-LE-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-LABEL: setbcr10:
|
||
|
|
; CHECK-BE: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NEXT: addis r4, r2, .LC1@toc@ha
|
||
|
|
; CHECK-BE-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-BE-NEXT: ld r4, .LC1@toc@l(r4)
|
||
|
|
; CHECK-BE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-BE-NEXT: stw r3, 0(r4)
|
||
|
|
; CHECK-BE-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i32 %a, 1
|
||
|
|
%conv1 = zext i1 %cmp to i32
|
||
|
|
store i32 %conv1, i32* @globalVal2, align 4
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @setbcr11(i64 %a) {
|
||
|
|
; CHECK-LE-LABEL: setbcr11:
|
||
|
|
; CHECK-LE: # %bb.0: # %entry
|
||
|
|
; CHECK-LE-NEXT: cmpdi r3, 1
|
||
|
|
; CHECK-LE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-LE-NEXT: pstd r3, globalVal3@PCREL(0), 1
|
||
|
|
; CHECK-LE-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-LABEL: setbcr11:
|
||
|
|
; CHECK-BE: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NEXT: addis r4, r2, .LC2@toc@ha
|
||
|
|
; CHECK-BE-NEXT: cmpdi r3, 1
|
||
|
|
; CHECK-BE-NEXT: ld r4, .LC2@toc@l(r4)
|
||
|
|
; CHECK-BE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-BE-NEXT: std r3, 0(r4)
|
||
|
|
; CHECK-BE-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i64 %a, 1
|
||
|
|
%conv1 = zext i1 %cmp to i64
|
||
|
|
store i64 %conv1, i64* @globalVal3, align 8
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|
||
|
|
define void @setbcr12(i16 %a) {
|
||
|
|
; CHECK-LE-LABEL: setbcr12:
|
||
|
|
; CHECK-LE: # %bb.0: # %entry
|
||
|
|
; CHECK-LE-NEXT: clrlwi r3, r3, 16
|
||
|
|
; CHECK-LE-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-LE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-LE-NEXT: psth r3, globalVal4@PCREL(0), 1
|
||
|
|
; CHECK-LE-NEXT: blr
|
||
|
|
;
|
||
|
|
; CHECK-BE-LABEL: setbcr12:
|
||
|
|
; CHECK-BE: # %bb.0: # %entry
|
||
|
|
; CHECK-BE-NEXT: addis r4, r2, .LC3@toc@ha
|
||
|
|
; CHECK-BE-NEXT: clrlwi r3, r3, 16
|
||
|
|
; CHECK-BE-NEXT: ld r4, .LC3@toc@l(r4)
|
||
|
|
; CHECK-BE-NEXT: cmpwi r3, 1
|
||
|
|
; CHECK-BE-NEXT: setbcr r3, eq
|
||
|
|
; CHECK-BE-NEXT: sth r3, 0(r4)
|
||
|
|
; CHECK-BE-NEXT: blr
|
||
|
|
entry:
|
||
|
|
%cmp = icmp ne i16 %a, 1
|
||
|
|
%conv1 = zext i1 %cmp to i16
|
||
|
|
store i16 %conv1, i16* @globalVal4, align 2
|
||
|
|
ret void
|
||
|
|
}
|
||
|
|
|