forked from OSchip/llvm-project
22 lines
819 B
LLVM
22 lines
819 B
LLVM
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; RUN: llc -march=hexagon < %s | FileCheck %s
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;
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; Check that we generate new value stores in V60.
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; CHECK: v{{[0-9]+}} = valign(v{{[0-9]+}},v{{[0-9]+}},r{{[0-9]+}})
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; CHECK: vmem(r{{[0-9]+}}+#{{[0-9]+}}) = v{{[0-9]+}}.new
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define void @f0(i16* nocapture readonly %a0, i32 %a1, i16* nocapture %a2) #0 {
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b0:
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%v0 = bitcast i16* %a0 to <16 x i32>*
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%v1 = bitcast i16* %a2 to <16 x i32>*
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%v2 = load <16 x i32>, <16 x i32>* %v0, align 64
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%v3 = tail call <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32> %v2, <16 x i32> undef, i32 %a1)
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store <16 x i32> %v3, <16 x i32>* %v1, align 64
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ret void
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.valignb(<16 x i32>, <16 x i32>, i32) #0
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attributes #0 = { nounwind readnone "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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