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llvm-project/llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

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[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=tahiti -o - %s | FileCheck -check-prefix=GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=fiji -o - %s | FileCheck -check-prefix=GFX8 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 -o - %s | FileCheck -check-prefix=GFX9 %s
; RUN: llc -global-isel -mtriple=amdgcn-amd-amdpal -mcpu=gfx1010 -o - %s | FileCheck -check-prefix=GFX10 %s
define i7 @v_ssubsat_i7(i7 %lhs, i7 %rhs) {
; GFX6-LABEL: v_ssubsat_i7:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 25, v0
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 25, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 25, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 9, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 9, v1
; GFX8-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v3, 0x8000, v3
; GFX8-NEXT: v_max_i16_e32 v1, v2, v1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v3
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 9, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 9, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 9, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_lshlrev_b16 v0, 9, v0
; GFX10-NEXT: v_lshlrev_b16 v1, 9, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_ashrrev_i16 v0, 9, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
define amdgpu_ps i7 @s_ssubsat_i7(i7 inreg %lhs, i7 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i7:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 25
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 25
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s3, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 25
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_i7:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, -1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s3, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, 0x7fff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s5
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, 0xffff8000
; GFX8-NEXT: s_max_i32 s1, s4, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s0, s0, s2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i7:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 9, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i7:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 9, 0x100000
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_ashrrev_i16 v0, 9, v0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i7 @llvm.ssub.sat.i7(i7 %lhs, i7 %rhs)
ret i7 %result
}
define i8 @v_ssubsat_i8(i8 %lhs, i8 %rhs) {
; GFX6-LABEL: v_ssubsat_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
; GFX8-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v3, 0x8000, v3
; GFX8-NEXT: v_max_i16_e32 v1, v2, v1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v3
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX8-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_lshlrev_b16 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b16 v1, 8, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
define amdgpu_ps i8 @s_ssubsat_i8(i8 inreg %lhs, i8 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s3, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX8-NEXT: s_lshl_b32 s0, s0, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, -1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s3, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, 0x7fff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s5
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, 0xffff8000
; GFX8-NEXT: s_max_i32 s1, s4, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s0, s0, s2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_ashrrev_i16_e32 v0, 8, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_bfe_u32 s2, 8, 0x100000
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_ashrrev_i16 v0, 8, v0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i8 @llvm.ssub.sat.i8(i8 %lhs, i8 %rhs)
ret i8 %result
}
define i16 @v_ssubsat_v2i8(i16 %lhs.arg, i16 %rhs.arg) {
; GFX6-LABEL: v_ssubsat_v2i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 8, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
; GFX6-NEXT: v_max_i32_e32 v1, v4, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1
; GFX6-NEXT: v_mov_b32_e32 v2, 0xff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_and_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v0, v0, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 8
; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v4, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s5, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v4, s4, v4
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v5, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v5, s5, v5
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i16_e32 v1, v4, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i16_e32 v1, v1, v5
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v1, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v1, s4, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v4, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v4, s5, v4
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i16_e32 v1, v1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i16_e32 v1, v1, v4
; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_mov_b32_e32 v2, 0xff
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_and_b32_sdwa v0, sext(v0), v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v2 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_lshrrev_b32_sdwa v3, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX9-NEXT: v_mov_b32_e32 v4, 0xffff
; GFX9-NEXT: v_and_or_b32 v0, v0, v4, v2
; GFX9-NEXT: v_and_or_b32 v1, v1, v4, v3
; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_movk_i32 s4, 0xff
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: s_mov_b32 s4, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_mov_b32_e32 v2, 0xffff
; GFX10-NEXT: v_lshrrev_b32_sdwa v3, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v4, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_movk_i32 s4, 0xff
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_and_or_b32 v0, v0, v2, v3
; GFX10-NEXT: v_and_or_b32 v1, v1, v2, v4
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s4 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result
}
define amdgpu_ps i16 @s_ssubsat_v2i8(i16 inreg %lhs.arg, i16 inreg %rhs.arg) {
; GFX6-LABEL: s_ssubsat_v2i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_brev_b32 s4, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s0, -1
; GFX6-NEXT: s_lshr_b32 s3, s1, 8
; GFX6-NEXT: s_lshl_b32 s1, s1, 24
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s7, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s7, s7, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s6, s1
; GFX6-NEXT: s_min_i32 s1, s1, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_lshl_b32 s2, s3, 24
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s3, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s3, s2
; GFX6-NEXT: s_min_i32 s2, s2, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_ashr_i32 s1, s1, 24
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_movk_i32 s2, 0xff
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v2i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s4, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8
; GFX8-NEXT: s_lshl_b32 s0, s0, s4
; GFX8-NEXT: s_sext_i32_i16 s7, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s5, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s9, s7, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s3, s1, 8
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s9, s9, s5
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s6, 0x8000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s7, s7, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s7, s7, s6
; GFX8-NEXT: s_max_i32 s1, s9, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s7, s7
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s1, s1, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_lshl_b32 s1, s2, s4
; GFX8-NEXT: s_lshl_b32 s2, s3, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s7, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s7, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s2, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s6
; GFX8-NEXT: s_max_i32 s2, s5, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s2, s2, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s2
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sext_i32_i16 s0, s0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_ashr_i32 s1, s1, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_movk_i32 s2, 0xff
; GFX8-NEXT: s_ashr_i32 s0, s0, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_and_b32 s1, s1, s2
; GFX8-NEXT: s_and_b32 s0, s0, s2
; GFX8-NEXT: s_lshl_b32 s1, s1, s4
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v2i8:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: s_lshr_b32 s2, s0, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: s_lshr_b32 s3, s1, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX9-NEXT: s_mov_b32 s2, 0x80008
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_lshr_b32 s3, s0, 16
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: s_lshl_b32 s0, s0, s2
; GFX9-NEXT: s_lshl_b32 s3, s3, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX9-NEXT: s_lshr_b32 s3, s1, 16
; GFX9-NEXT: s_lshl_b32 s1, s1, s2
; GFX9-NEXT: s_lshl_b32 s2, s3, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s2
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s1
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: s_movk_i32 s0, 0xff
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX9-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i8:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: s_lshr_b32 s2, s0, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: s_lshr_b32 s3, s1, 8
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s3
; GFX10-NEXT: s_mov_b32 s2, 0x80008
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: s_lshr_b32 s3, s0, 16
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: s_lshr_b32 s4, s1, 16
; GFX10-NEXT: s_lshl_b32 s0, s0, s2
; GFX10-NEXT: s_lshl_b32 s3, s3, 8
; GFX10-NEXT: s_lshl_b32 s1, s1, s2
; GFX10-NEXT: s_lshl_b32 s2, s4, 8
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s2
; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
; GFX10-NEXT: s_movk_i32 s0, 0xff
; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_and_b32_sdwa v1, v0, s0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
; GFX10-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:DWORD
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i16 %lhs.arg to <2 x i8>
%rhs = bitcast i16 %rhs.arg to <2 x i8>
%result = call <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8> %lhs, <2 x i8> %rhs)
%cast.result = bitcast <2 x i8> %result to i16
ret i16 %cast.result
}
define i32 @v_ssubsat_v4i8(i32 %lhs.arg, i32 %rhs.arg) {
; GFX6-LABEL: v_ssubsat_v4i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshrrev_b32_e32 v2, 8, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v4, 24, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 24, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshrrev_b32_e32 v5, 8, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX6-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v1, v8, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v10
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_max_i32_e32 v2, v5, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 24, v3
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
; GFX6-NEXT: v_max_i32_e32 v3, v5, v3
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 24, v4
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 24, v1
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 24, v7
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
; GFX6-NEXT: s_movk_i32 s4, 0xff
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 24, v0
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v11
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 24, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 24, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 24, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v4i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v2, 8
; GFX8-NEXT: v_lshrrev_b32_sdwa v3, v2, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 24, v0
; GFX8-NEXT: v_lshlrev_b16_e32 v0, 8, v0
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v8, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_sdwa v2, v2, v1 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v1
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v1, 8, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s5, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v8, s4, v8
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v10, -1, v0
; GFX8-NEXT: v_subrev_u16_e32 v10, s5, v10
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i16_e32 v1, v8, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v1, v1, v10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v1, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v1, s4, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v8, -1, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v8, s5, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_max_i16_e32 v1, v1, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v2, 8, v4
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_mov_b32_e32 v9, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v1, v1, v8
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v4, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_e32 v1, v3, v1
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v6
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v4, v4, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v6, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v6, s5, v6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i16_e32 v3, v4, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i16_e32 v3, v3, v6
; GFX8-NEXT: v_sub_u16_e32 v2, v2, v3
; GFX8-NEXT: v_lshlrev_b16_e32 v3, 8, v5
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v5, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshlrev_b16_e32 v4, 8, v7
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v5, v5, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v6, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v6, 0x8000, v6
; GFX8-NEXT: v_max_i16_e32 v4, v5, v4
; GFX8-NEXT: v_min_i16_e32 v4, v4, v6
; GFX8-NEXT: v_sub_u16_e32 v3, v3, v4
; GFX8-NEXT: v_mov_b32_e32 v4, 0xff
; GFX8-NEXT: v_and_b32_sdwa v1, sext(v1), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_and_b32_sdwa v0, sext(v0), v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, sext(v2), v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: v_and_b32_sdwa v1, sext(v3), v4 dst_sel:BYTE_3 dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v4i8:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_lshrrev_b32_e32 v4, 24, v0
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_mov_b32_e32 v8, 0xffff
; GFX9-NEXT: v_lshrrev_b32_e32 v3, 16, v0
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_lshrrev_b32_sdwa v5, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_and_or_b32 v0, v0, v8, v2
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v4
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_and_or_b32 v2, v3, v8, v2
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_and_or_b32 v1, v1, v8, v5
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_lshlrev_b32_e32 v3, 16, v7
; GFX9-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_and_or_b32 v3, v6, v8, v3
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_pk_sub_i16 v1, v2, v3 clamp
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX9-NEXT: v_mov_b32_e32 v2, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: s_movk_i32 s4, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_and_or_b32 v0, v0, s4, v2
; GFX9-NEXT: v_and_b32_e32 v2, s4, v1
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_mov_b32_e32 v3, 24
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, v3, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v4i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_lshrrev_b32_e32 v4, 24, v0
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: v_lshrrev_b32_e32 v5, 24, v1
; GFX10-NEXT: s_mov_b32 s4, 8
Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" This reverts commit 9075009d1fd5f2bf9aa6c2f362d2993691a316b3. Failed amdgpu runtime buildbot # 3514
2021-12-23 00:39:28 +08:00
; GFX10-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX10-NEXT: v_lshrrev_b32_sdwa v2, s4, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_lshrrev_b32_sdwa v6, s4, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX10-NEXT: v_mov_b32_e32 v7, 0xffff
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_lshrrev_b32_e32 v8, 16, v1
; GFX10-NEXT: v_lshlrev_b32_e32 v4, 16, v4
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: v_lshlrev_b32_e32 v5, 16, v5
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: s_movk_i32 s4, 0xff
Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" This reverts commit 9075009d1fd5f2bf9aa6c2f362d2993691a316b3. Failed amdgpu runtime buildbot # 3514
2021-12-23 00:39:28 +08:00
; GFX10-NEXT: v_and_or_b32 v0, v0, v7, v2
; GFX10-NEXT: v_and_or_b32 v1, v1, v7, v6
; GFX10-NEXT: v_and_or_b32 v2, v3, v7, v4
; GFX10-NEXT: v_and_or_b32 v3, v8, v7, v5
; GFX10-NEXT: v_mov_b32_e32 v4, 24
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_pk_lshlrev_b16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_lshlrev_b16 v1, 8, v1 op_sel_hi:[0,1]
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range Currently the return address ABI registers s[30:31], which fall in the call clobbered register range, are added as a live-in on the function entry to preserve its value when we have calls so that it gets saved and restored around the calls. But the DWARF unwind information (CFI) needs to track where the return address resides in a frame and the above approach makes it difficult to track the return address when the CFI information is emitted during the frame lowering, due to the involvment of understanding the control flow. This patch moves the return address ABI registers s[30:31] into callee saved registers range and stops adding live-in for return address registers, so that the CFI machinery will know where the return address resides when CSR save/restore happen during the frame lowering. And doing the above poses an issue that now the return instruction uses undefined register `sgpr30_sgpr31`. This is resolved by hiding the return address register use by the return instruction through the `SI_RETURN` pseudo instruction, which doesn't take any input operands, until the `SI_RETURN` pseudo gets lowered to the `S_SETPC_B64_return` during the `expandPostRAPseudo()`. As an added benefit, this patch simplifies overall return instruction handling. Note: The AMDGPU CFI changes are there only in the downstream code and another version of this patch will be posted for review for the downstream code. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D114652
2021-12-22 21:02:52 +08:00
; GFX10-NEXT: v_pk_lshlrev_b16 v2, 8, v2 op_sel_hi:[0,1]
Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" This reverts commit 9075009d1fd5f2bf9aa6c2f362d2993691a316b3. Failed amdgpu runtime buildbot # 3514
2021-12-23 00:39:28 +08:00
; GFX10-NEXT: v_pk_lshlrev_b16 v3, 8, v3 op_sel_hi:[0,1]
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range" This reverts commit 9075009d1fd5f2bf9aa6c2f362d2993691a316b3. Failed amdgpu runtime buildbot # 3514
2021-12-23 00:39:28 +08:00
; GFX10-NEXT: v_pk_sub_i16 v1, v2, v3 clamp
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: v_mov_b32_e32 v2, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_and_b32_e32 v3, s4, v1
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_and_or_b32 v0, v0, s4, v2
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result
}
define amdgpu_ps i32 @s_ssubsat_v4i8(i32 inreg %lhs.arg, i32 inreg %rhs.arg) {
; GFX6-LABEL: s_ssubsat_v4i8:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshr_b32 s2, s0, 8
; GFX6-NEXT: s_lshr_b32 s3, s0, 16
; GFX6-NEXT: s_lshr_b32 s4, s0, 24
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_lshl_b32 s0, s0, 24
; GFX6-NEXT: s_brev_b32 s8, -2
; GFX6-NEXT: s_max_i32 s10, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshr_b32 s5, s1, 8
; GFX6-NEXT: s_lshr_b32 s6, s1, 16
; GFX6-NEXT: s_lshr_b32 s7, s1, 24
; GFX6-NEXT: s_lshl_b32 s1, s1, 24
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s9, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s11, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s11, s11, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s10, s1
; GFX6-NEXT: s_min_i32 s1, s1, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_lshl_b32 s1, s2, 24
; GFX6-NEXT: s_lshl_b32 s2, s5, 24
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s5, s2
; GFX6-NEXT: s_min_i32 s2, s2, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_lshl_b32 s2, s3, 24
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s3, s6, 24
; GFX6-NEXT: s_sub_i32 s5, s5, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s6, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s3, s5, s3
; GFX6-NEXT: s_min_i32 s3, s3, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: s_lshl_b32 s3, s4, 24
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s4, s7, 24
; GFX6-NEXT: s_sub_i32 s5, s5, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s6, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s5, s4
; GFX6-NEXT: s_min_i32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 24
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_movk_i32 s4, 0xff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s0, s0, 24
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s1, s1, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s2, s2, 24
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_ashr_i32 s3, s3, 24
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s3, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 24
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v4i8:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_bfe_u32 s8, 8, 0x100000
; GFX8-NEXT: s_lshr_b32 s2, s0, 8
; GFX8-NEXT: s_lshr_b32 s3, s0, 16
; GFX8-NEXT: s_lshr_b32 s4, s0, 24
; GFX8-NEXT: s_lshl_b32 s0, s0, s8
; GFX8-NEXT: s_sext_i32_i16 s11, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s12, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s9, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s13, s11, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s5, s1, 8
; GFX8-NEXT: s_lshr_b32 s6, s1, 16
; GFX8-NEXT: s_lshr_b32 s7, s1, 24
; GFX8-NEXT: s_lshl_b32 s1, s1, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s13, s13, s9
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s10, 0x8000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s11, s11, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s13, s13
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s11, s11, s10
; GFX8-NEXT: s_max_i32 s1, s13, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s11, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s1, s1, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_lshl_b32 s1, s2, s8
; GFX8-NEXT: s_lshl_b32 s2, s5, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s11, s5, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s11, s11, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s5, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s11, s11
; GFX8-NEXT: s_sext_i32_i16 s2, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_max_i32 s2, s11, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s5, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s2, s2, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s2
; GFX8-NEXT: s_lshl_b32 s2, s3, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshl_b32 s3, s6, s8
; GFX8-NEXT: s_max_i32 s6, s5, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s5, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_max_i32 s3, s6, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s5, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s3
; GFX8-NEXT: s_lshl_b32 s3, s4, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s6, s5, s12
; GFX8-NEXT: s_lshl_b32 s4, s7, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s5, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s10
; GFX8-NEXT: s_max_i32 s4, s6, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s5, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_sext_i32_i16 s0, s0
; GFX8-NEXT: s_ashr_i32 s1, s1, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s4, 0xff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_ashr_i32 s0, s0, s8
; GFX8-NEXT: s_sext_i32_i16 s2, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_and_b32 s1, s1, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_ashr_i32 s2, s2, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_and_b32 s0, s0, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 8
; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s2, s4
; GFX8-NEXT: s_ashr_i32 s3, s3, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_lshl_b32 s1, s1, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: s_and_b32 s1, s3, s4
; GFX8-NEXT: s_lshl_b32 s1, s1, 24
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v4i8:
; GFX9: ; %bb.0:
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: s_lshr_b32 s3, s0, 8
GlobalISel: Revisit users of other merge opcodes in artifact combiner The artifact combiner searches for the uses of G_MERGE_VALUES for unmerge/trunc that need further combining. This also needs to handle the vector merge opcodes the same way. This fixes leaving behind some pairs I expected to be removed, that were if the legalizer is run a second time.
2020-08-16 22:04:12 +08:00
; GFX9-NEXT: s_lshr_b32 s4, s0, 16
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: s_lshr_b32 s6, s0, 24
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s3
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s4, s6
; GFX9-NEXT: s_mov_b32 s4, 0x80008
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_lshr_b32 s6, s0, 16
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: s_lshr_b32 s7, s1, 8
; GFX9-NEXT: s_lshl_b32 s0, s0, s4
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
; GFX9-NEXT: s_lshr_b32 s8, s1, 16
; GFX9-NEXT: s_lshr_b32 s9, s1, 24
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_pack_ll_b32_b16 s0, s0, s6
; GFX9-NEXT: s_lshr_b32 s6, s3, 16
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s7
; GFX9-NEXT: s_lshl_b32 s3, s3, s4
; GFX9-NEXT: s_lshl_b32 s6, s6, 8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_lshr_b32 s7, s1, 16
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: s_pack_ll_b32_b16 s3, s3, s6
; GFX9-NEXT: s_pack_ll_b32_b16 s6, s8, s9
; GFX9-NEXT: s_lshl_b32 s1, s1, s4
; GFX9-NEXT: s_lshl_b32 s7, s7, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s1, s1, s7
; GFX9-NEXT: s_lshr_b32 s7, s6, 16
; GFX9-NEXT: s_lshl_b32 s4, s6, s4
; GFX9-NEXT: s_lshl_b32 s6, s7, 8
; GFX9-NEXT: s_pack_ll_b32_b16 s4, s4, s6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s1
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: s_mov_b32 s2, 8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_pk_sub_i16 v1, s3, v1 clamp
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX9-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: s_movk_i32 s0, 0xff
; GFX9-NEXT: v_lshlrev_b32_sdwa v2, s2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_mov_b32 s5, 24
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_and_or_b32 v0, v0, s0, v2
; GFX9-NEXT: v_and_b32_e32 v2, s0, v1
; GFX9-NEXT: v_lshlrev_b32_e32 v2, 16, v2
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX9-NEXT: v_lshlrev_b32_sdwa v1, s5, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX9-NEXT: v_or3_b32 v0, v0, v2, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v4i8:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshr_b32 s2, s0, 8
; GFX10-NEXT: s_lshr_b32 s3, s0, 16
; GFX10-NEXT: s_lshr_b32 s4, s0, 24
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s2
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_pack_ll_b32_b16 s2, s3, s4
; GFX10-NEXT: s_mov_b32 s3, 0x80008
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: s_lshr_b32 s4, s0, 16
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_lshr_b32 s5, s1, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: s_lshr_b32 s6, s1, 16
; GFX10-NEXT: s_lshr_b32 s7, s1, 24
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_lshl_b32 s0, s0, s3
; GFX10-NEXT: s_lshl_b32 s4, s4, 8
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_pack_ll_b32_b16 s0, s0, s4
; GFX10-NEXT: s_pack_ll_b32_b16 s4, s6, s7
; GFX10-NEXT: s_lshr_b32 s8, s2, 16
GlobalISel: Revisit users of other merge opcodes in artifact combiner The artifact combiner searches for the uses of G_MERGE_VALUES for unmerge/trunc that need further combining. This also needs to handle the vector merge opcodes the same way. This fixes leaving behind some pairs I expected to be removed, that were if the legalizer is run a second time.
2020-08-16 22:04:12 +08:00
; GFX10-NEXT: s_lshr_b32 s5, s1, 16
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_lshr_b32 s6, s4, 16
; GFX10-NEXT: s_lshl_b32 s2, s2, s3
GlobalISel: Revisit users of other merge opcodes in artifact combiner The artifact combiner searches for the uses of G_MERGE_VALUES for unmerge/trunc that need further combining. This also needs to handle the vector merge opcodes the same way. This fixes leaving behind some pairs I expected to be removed, that were if the legalizer is run a second time.
2020-08-16 22:04:12 +08:00
; GFX10-NEXT: s_lshl_b32 s8, s8, 8
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_lshl_b32 s1, s1, s3
GlobalISel: Revisit users of other merge opcodes in artifact combiner The artifact combiner searches for the uses of G_MERGE_VALUES for unmerge/trunc that need further combining. This also needs to handle the vector merge opcodes the same way. This fixes leaving behind some pairs I expected to be removed, that were if the legalizer is run a second time.
2020-08-16 22:04:12 +08:00
; GFX10-NEXT: s_lshl_b32 s5, s5, 8
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_lshl_b32 s3, s4, s3
; GFX10-NEXT: s_lshl_b32 s4, s6, 8
; GFX10-NEXT: s_pack_ll_b32_b16 s2, s2, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: s_pack_ll_b32_b16 s1, s1, s5
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: s_pack_ll_b32_b16 s3, s3, s4
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: v_pk_sub_i16 v1, s2, s3 clamp
; GFX10-NEXT: s_mov_b32 s0, 8
; GFX10-NEXT: s_movk_i32 s1, 0xff
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_pk_ashrrev_i16 v0, 8, v0 op_sel_hi:[0,1]
; GFX10-NEXT: v_pk_ashrrev_i16 v1, 8, v1 op_sel_hi:[0,1]
[AMDGPU][GlobalISel] Legalize and select G_SBFX and G_UBFX Adds legalizer, register bank select, and instruction select support for G_SBFX and G_UBFX. These opcodes generate scalar or vector ALU bitfield extract instructions for AMDGPU. The instructions allow both constant or register values for the offset and width operands. The 32-bit scalar version is expanded to a sequence that combines the offset and width into a single register. There are no 64-bit vgpr bitfield extract instructions, so the operations are expanded to a sequence of instructions that implement the operation. If the width is a constant, then the 32-bit bitfield extract instructions are used. Moved the AArch64 specific code for creating G_SBFX to CombinerHelper.cpp so that it can be used by other targets. Only bitfield extracts with constant offset and width values are handled currently. Differential Revision: https://reviews.llvm.org/D100149
2021-04-30 21:57:44 +08:00
; GFX10-NEXT: v_lshlrev_b32_sdwa v2, s0, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_and_b32_e32 v3, s1, v1
; GFX10-NEXT: s_mov_b32 s0, 24
; GFX10-NEXT: v_lshlrev_b32_sdwa v1, s0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_2
; GFX10-NEXT: v_and_or_b32 v0, v0, s1, v2
AMDGPU/GlobalISel: Try to promote to use packed saturating add/sub This produces worse results right now for i8 vectors, but that should be addressed when we actually try to optimize packed vectors.
2020-07-16 01:49:03 +08:00
; GFX10-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX10-NEXT: v_or3_b32 v0, v0, v2, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%lhs = bitcast i32 %lhs.arg to <4 x i8>
%rhs = bitcast i32 %rhs.arg to <4 x i8>
%result = call <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8> %lhs, <4 x i8> %rhs)
%cast.result = bitcast <4 x i8> %result to i32
ret i32 %cast.result
}
define i24 @v_ssubsat_i24(i24 %lhs, i24 %rhs) {
; GFX6-LABEL: v_ssubsat_i24:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 8, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_i24:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v0, v1
; GFX8-NEXT: v_bfe_i32 v3, v2, 0, 24
; GFX8-NEXT: v_bfe_i32 v0, v0, 0, 24
; GFX8-NEXT: v_cmp_lt_i32_e64 s[4:5], v3, v0
; GFX8-NEXT: v_bfe_i32 v0, v1, 0, 24
GlobalISel: Combine out redundant sext_inreg The scalar tests don't work yet, since computeNumSignBits apparently doesn't handle sextload yet, and sext folds into the load first.
2020-08-28 22:43:17 +08:00
; GFX8-NEXT: v_cmp_lt_i32_e64 s[6:7], 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 23, v3
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0xff800000, v0
; GFX8-NEXT: s_xor_b64 vcc, s[6:7], s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v0
; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v1
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
define amdgpu_ps i24 @s_ssubsat_i24(i24 inreg %lhs, i24 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i24:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 8
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s3, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 8
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_i24:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_i32 s2, s0, s1
; GFX8-NEXT: s_bfe_i32 s3, s2, 0x180000
; GFX8-NEXT: s_bfe_i32 s0, s0, 0x180000
; GFX8-NEXT: s_cmp_lt_i32 s3, s0
; GFX8-NEXT: s_cselect_b32 s0, 1, 0
; GFX8-NEXT: s_bfe_i32 s1, s1, 0x180000
GlobalISel: Combine out redundant sext_inreg The scalar tests don't work yet, since computeNumSignBits apparently doesn't handle sextload yet, and sext folds into the load first.
2020-08-28 22:43:17 +08:00
; GFX8-NEXT: s_cmp_gt_i32 s1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_xor_b32 s0, s1, s0
; GFX8-NEXT: s_ashr_i32 s1, s3, 23
; GFX8-NEXT: s_add_i32 s1, s1, 0xff800000
; GFX8-NEXT: s_and_b32 s0, s0, 1
; GFX8-NEXT: s_cmp_lg_u32 s0, 0
; GFX8-NEXT: s_cselect_b32 s0, s1, s2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i24:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_lshl_b32 s1, s1, 8
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: s_lshl_b32 s0, s0, 8
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i24:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_lshl_b32 s0, s0, 8
; GFX10-NEXT: s_lshl_b32 s1, s1, 8
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 8, v0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i24 @llvm.ssub.sat.i24(i24 %lhs, i24 %rhs)
ret i24 %result
}
define i32 @v_ssubsat_i32(i32 %lhs, i32 %rhs) {
; GFX6-LABEL: v_ssubsat_i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_max_i32_e32 v2, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 0x7fffffff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i32_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, 0x80000000, v3
; GFX8-NEXT: v_max_i32_e32 v1, v2, v1
; GFX8-NEXT: v_min_i32_e32 v1, v1, v3
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
define amdgpu_ps i32 @s_ssubsat_i32(i32 inreg %lhs, i32 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i32:
; GFX6: ; %bb.0:
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s3, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_i32:
; GFX8: ; %bb.0:
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s3, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, 0x80000000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s1, s2, s1
; GFX8-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i32:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i32:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s1 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
ret i32 %result
}
define amdgpu_ps float @ssubsat_i32_sv(i32 inreg %lhs, i32 %rhs) {
; GFX6-LABEL: ssubsat_i32_sv:
; GFX6: ; %bb.0:
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, 0x80000000
; GFX6-NEXT: v_max_i32_e32 v0, s1, v0
; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i32_sv:
; GFX8: ; %bb.0:
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s1, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, 0x80000000
; GFX8-NEXT: v_max_i32_e32 v0, s1, v0
; GFX8-NEXT: v_min_i32_e32 v0, s2, v0
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i32_sv:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i32_sv:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, v0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
}
define amdgpu_ps float @ssubsat_i32_vs(i32 %lhs, i32 inreg %rhs) {
; GFX6-LABEL: ssubsat_i32_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_max_i32_e32 v1, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, 0x7fffffff, v1
; GFX6-NEXT: v_min_i32_e32 v2, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x80000000, v2
; GFX6-NEXT: v_max_i32_e32 v1, s0, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i32_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_max_i32_e32 v1, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v1, vcc, 0x7fffffff, v1
; GFX8-NEXT: v_min_i32_e32 v2, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, 0x80000000, v2
; GFX8-NEXT: v_max_i32_e32 v1, s0, v1
; GFX8-NEXT: v_min_i32_e32 v1, v1, v2
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i32_vs:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, s0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i32_vs:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, s0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i32 @llvm.ssub.sat.i32(i32 %lhs, i32 %rhs)
%cast = bitcast i32 %result to float
ret float %cast
}
define <2 x i32> @v_ssubsat_v2i32(<2 x i32> %lhs, <2 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s4, v2
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT: v_max_i32_e32 v2, v2, v3
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v4, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v5, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s5, v5
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i32_e32 v2, v4, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v2, v2, v5
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v2
; GFX8-NEXT: v_max_i32_e32 v2, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s4, v2
; GFX8-NEXT: v_min_i32_e32 v4, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s5, v4
; GFX8-NEXT: v_max_i32_e32 v2, v2, v3
; GFX8-NEXT: v_min_i32_e32 v2, v2, v4
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, v2 clamp
; GFX9-NEXT: v_sub_i32 v1, v1, v3 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v2 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, v1, v3 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
define amdgpu_ps <2 x i32> @s_ssubsat_v2i32(<2 x i32> inreg %lhs, <2 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_brev_b32 s4, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s7, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s7, s7, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s6, s2
; GFX6-NEXT: s_min_i32 s2, s2, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s2, s3
; GFX6-NEXT: s_min_i32 s2, s2, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v2i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_brev_b32 s4, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s6, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s7, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s7, s7, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s2, s6, s2
; GFX8-NEXT: s_min_i32 s2, s2, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s2, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s2, s2, s3
; GFX8-NEXT: s_min_i32 s2, s2, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v2i32:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i32:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s2 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, s1, s3 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32> %lhs, <2 x i32> %rhs)
ret <2 x i32> %result
}
define <3 x i32> @v_ssubsat_v3i32(<3 x i32> %lhs, <3 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v6, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s4, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v7, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, s5, v7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v3, v6, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, v3, v7
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_min_i32_e32 v6, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v3, v3, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, v3, v6
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v2
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
; GFX6-NEXT: v_min_i32_e32 v4, -1, v2
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT: v_max_i32_e32 v3, v3, v5
; GFX6-NEXT: v_min_i32_e32 v3, v3, v4
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v6, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s4, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v7, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v7, vcc, s5, v7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i32_e32 v3, v6, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v3, v3, v7
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v3
; GFX8-NEXT: v_max_i32_e32 v3, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s4, v3
; GFX8-NEXT: v_min_i32_e32 v6, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s5, v6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i32_e32 v3, v3, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v3, v3, v6
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v3
; GFX8-NEXT: v_max_i32_e32 v3, -1, v2
; GFX8-NEXT: v_subrev_u32_e32 v3, vcc, s4, v3
; GFX8-NEXT: v_min_i32_e32 v4, -1, v2
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s5, v4
; GFX8-NEXT: v_max_i32_e32 v3, v3, v5
; GFX8-NEXT: v_min_i32_e32 v3, v3, v4
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v3i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, v3 clamp
; GFX9-NEXT: v_sub_i32 v1, v1, v4 clamp
; GFX9-NEXT: v_sub_i32 v2, v2, v5 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v3i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v3 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, v1, v4 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, v2, v5 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
define amdgpu_ps <3 x i32> @s_ssubsat_v3i32(<3 x i32> inreg %lhs, <3 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v3i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_brev_b32 s6, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s7, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s8, s8, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s9, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s9, s9, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s3, s8, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s3, s3, s9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s3, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s8, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s8, s8, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s3, s3, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s3, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s3, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s7
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s3, s3, s5
; GFX6-NEXT: s_min_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v3i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_brev_b32 s6, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s8, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s7, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s9, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s9, s9, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s3, s8, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s3, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s8, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s3, s3, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s3, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s7
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s3, s3, s5
; GFX8-NEXT: s_min_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v3i32:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v3i32:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s3 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, s1, s4 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, s2, s5 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32> %lhs, <3 x i32> %rhs)
ret <3 x i32> %result
}
define <4 x i32> @v_ssubsat_v4i32(<4 x i32> %lhs, <4 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v9, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v9, vcc, s5, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v4, v4, v9
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v4, v4, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v2
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v2
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
; GFX6-NEXT: v_max_i32_e32 v4, v4, v6
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
; GFX6-NEXT: v_max_i32_e32 v4, -1, v3
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, 0x7fffffff, v4
; GFX6-NEXT: v_min_i32_e32 v5, -1, v3
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, 0x80000000, v5
; GFX6-NEXT: v_max_i32_e32 v4, v4, v7
; GFX6-NEXT: v_min_i32_e32 v4, v4, v5
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v8, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, s4, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v9, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v9, vcc, s5, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i32_e32 v4, v8, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v4, v4, v9
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
; GFX8-NEXT: v_min_i32_e32 v8, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v8, vcc, s5, v8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i32_e32 v4, v4, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v4, v4, v8
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v2
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s4, v4
; GFX8-NEXT: v_min_i32_e32 v5, -1, v2
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s5, v5
; GFX8-NEXT: v_max_i32_e32 v4, v4, v6
; GFX8-NEXT: v_min_i32_e32 v4, v4, v5
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v4
; GFX8-NEXT: v_max_i32_e32 v4, -1, v3
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, 0x7fffffff, v4
; GFX8-NEXT: v_min_i32_e32 v5, -1, v3
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, 0x80000000, v5
; GFX8-NEXT: v_max_i32_e32 v4, v4, v7
; GFX8-NEXT: v_min_i32_e32 v4, v4, v5
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v4i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, v4 clamp
; GFX9-NEXT: v_sub_i32 v1, v1, v5 clamp
; GFX9-NEXT: v_sub_i32 v2, v2, v6 clamp
; GFX9-NEXT: v_sub_i32 v3, v3, v7 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v4i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v4 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, v1, v5 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, v2, v6 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, v3, v7 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
define amdgpu_ps <4 x i32> @s_ssubsat_v4i32(<4 x i32> inreg %lhs, <4 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v4i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_brev_b32 s8, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s10, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s9, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s11, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s11, s11, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s4, s10, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s4, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s10, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s4, s4, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s4, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s5, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s4, s6
; GFX6-NEXT: s_min_i32 s4, s4, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s5, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s4, s7
; GFX6-NEXT: s_min_i32 s4, s4, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v4i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_brev_b32 s8, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s10, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s9, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s10, s10, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s11, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s11, s11, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s4, s10, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s4, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s4, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s10, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s10, s10, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s4, s4, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s4, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s4, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s4, s4, s6
; GFX8-NEXT: s_min_i32 s4, s4, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s4, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s4, s4, s7
; GFX8-NEXT: s_min_i32 s4, s4, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s4
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v4i32:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v4i32:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s4 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, s1, s5 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, s2, s6 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, s3, s7 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %lhs, <4 x i32> %rhs)
ret <4 x i32> %result
}
define <5 x i32> @v_ssubsat_v5i32(<5 x i32> %lhs, <5 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v10, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s4, v10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v12, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, s5, v12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v5, v10, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v5, v5, v12
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v10, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v5, v5, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v5, v5, v10
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
; GFX6-NEXT: v_max_i32_e32 v5, v5, v7
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
; GFX6-NEXT: v_bfrev_b32_e32 v11, -2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v13, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v13
; GFX6-NEXT: v_max_i32_e32 v5, v5, v8
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v4
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v11
; GFX6-NEXT: v_min_i32_e32 v6, -1, v4
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v13
; GFX6-NEXT: v_max_i32_e32 v5, v5, v9
; GFX6-NEXT: v_min_i32_e32 v5, v5, v6
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v5
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_brev_b32 s4, -2
; GFX8-NEXT: v_max_i32_e32 v10, -1, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, s4, v10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v12, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v12, vcc, s5, v12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i32_e32 v5, v10, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v5, v5, v12
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v5
; GFX8-NEXT: v_min_i32_e32 v10, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v10, vcc, s5, v10
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i32_e32 v5, v5, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v5, v5, v10
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v2
; GFX8-NEXT: v_subrev_u32_e32 v5, vcc, s4, v5
; GFX8-NEXT: v_min_i32_e32 v6, -1, v2
; GFX8-NEXT: v_subrev_u32_e32 v6, vcc, s5, v6
; GFX8-NEXT: v_max_i32_e32 v5, v5, v7
; GFX8-NEXT: v_min_i32_e32 v5, v5, v6
; GFX8-NEXT: v_bfrev_b32_e32 v11, -2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_max_i32_e32 v5, -1, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_bfrev_b32_e32 v13, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v6, -1, v3
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v6, v13
; GFX8-NEXT: v_max_i32_e32 v5, v5, v8
; GFX8-NEXT: v_min_i32_e32 v5, v5, v6
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v5
; GFX8-NEXT: v_max_i32_e32 v5, -1, v4
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v11
; GFX8-NEXT: v_min_i32_e32 v6, -1, v4
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v6, v13
; GFX8-NEXT: v_max_i32_e32 v5, v5, v9
; GFX8-NEXT: v_min_i32_e32 v5, v5, v6
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v5
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v5i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, v5 clamp
; GFX9-NEXT: v_sub_i32 v1, v1, v6 clamp
; GFX9-NEXT: v_sub_i32 v2, v2, v7 clamp
; GFX9-NEXT: v_sub_i32 v3, v3, v8 clamp
; GFX9-NEXT: v_sub_i32 v4, v4, v9 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v5i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v5 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, v1, v6 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, v2, v7 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, v3, v8 clamp
; GFX10-NEXT: v_sub_nc_i32 v4, v4, v9 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
define amdgpu_ps <5 x i32> @s_ssubsat_v5i32(<5 x i32> inreg %lhs, <5 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v5i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_brev_b32 s10, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s12, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s11, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s12, s12, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s13, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s13, s13, s11
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s5, s12, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s5, s5, s13
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s12, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s12, s12, s11
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s5, s5, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s5, s5, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s6, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s5, s7
; GFX6-NEXT: s_min_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s6, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s5, s8
; GFX6-NEXT: s_min_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s6, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s5, s9
; GFX6-NEXT: s_min_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s5
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v5i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_brev_b32 s10, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s12, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s11, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s12, s12, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s13, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s13, s13, s11
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s5, s12, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s5, s13
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s12, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s12, s12, s11
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s5, s5, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s5, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s6, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s5, s7
; GFX8-NEXT: s_min_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s6, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s5, s8
; GFX8-NEXT: s_min_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s6, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s5, s5, s9
; GFX8-NEXT: s_min_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s5
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v5i32:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s7
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_mov_b32_e32 v4, s9
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp
; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v5i32:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s5 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, s1, s6 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, s2, s7 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, s3, s8 clamp
; GFX10-NEXT: v_sub_nc_i32 v4, s4, s9 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32> %lhs, <5 x i32> %rhs)
ret <5 x i32> %result
}
define <16 x i32> @v_ssubsat_v16i32(<16 x i32> %lhs, <16 x i32> %rhs) {
; GFX6-LABEL: v_ssubsat_v16i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: s_brev_b32 s4, -2
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX6-NEXT: v_max_i32_e32 v31, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v31, vcc, s4, v31
; GFX6-NEXT: v_max_i32_e32 v16, v31, v16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX6-NEXT: v_min_i32_e32 v31, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v31, vcc, s5, v31
; GFX6-NEXT: v_min_i32_e32 v16, v16, v31
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v16
; GFX6-NEXT: v_max_i32_e32 v16, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, s4, v16
; GFX6-NEXT: v_max_i32_e32 v16, v16, v17
; GFX6-NEXT: v_min_i32_e32 v17, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v17, vcc, s5, v17
; GFX6-NEXT: v_min_i32_e32 v16, v16, v17
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v16
; GFX6-NEXT: v_max_i32_e32 v16, -1, v2
; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, s4, v16
; GFX6-NEXT: v_min_i32_e32 v17, -1, v2
; GFX6-NEXT: v_max_i32_e32 v16, v16, v18
; GFX6-NEXT: v_subrev_i32_e32 v17, vcc, s5, v17
; GFX6-NEXT: v_min_i32_e32 v16, v16, v17
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v16
; GFX6-NEXT: v_bfrev_b32_e32 v16, -2
; GFX6-NEXT: v_max_i32_e32 v17, -1, v3
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_max_i32_e32 v17, v17, v19
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v18, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v19, -1, v3
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v4
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_max_i32_e32 v17, v17, v20
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX6-NEXT: buffer_load_dword v20, off, s[0:3], s32
; GFX6-NEXT: v_min_i32_e32 v19, -1, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v5
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v5
; GFX6-NEXT: v_max_i32_e32 v17, v17, v21
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v6
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v6
; GFX6-NEXT: v_max_i32_e32 v17, v17, v22
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v7
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v7
; GFX6-NEXT: v_max_i32_e32 v17, v17, v23
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v8
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v8
; GFX6-NEXT: v_max_i32_e32 v17, v17, v24
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v9
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v9
; GFX6-NEXT: v_max_i32_e32 v17, v17, v25
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v10
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v10
; GFX6-NEXT: v_max_i32_e32 v17, v17, v26
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v11
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v11
; GFX6-NEXT: v_max_i32_e32 v17, v17, v27
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v11, vcc, v11, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v12
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v12
; GFX6-NEXT: v_max_i32_e32 v17, v17, v28
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v12, vcc, v12, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v13
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v13
; GFX6-NEXT: v_max_i32_e32 v17, v17, v29
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v13, vcc, v13, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v14
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v19, -1, v14
; GFX6-NEXT: v_max_i32_e32 v17, v17, v30
; GFX6-NEXT: v_sub_i32_e32 v19, vcc, v19, v18
; GFX6-NEXT: v_min_i32_e32 v17, v17, v19
; GFX6-NEXT: v_sub_i32_e32 v14, vcc, v14, v17
; GFX6-NEXT: v_max_i32_e32 v17, -1, v15
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, v17, v16
; GFX6-NEXT: v_min_i32_e32 v17, -1, v15
; GFX6-NEXT: v_sub_i32_e32 v17, vcc, v17, v18
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX6-NEXT: s_waitcnt vmcnt(0)
; GFX6-NEXT: v_max_i32_e32 v16, v16, v20
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v16, v16, v17
; GFX6-NEXT: v_sub_i32_e32 v15, vcc, v15, v16
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v16i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_brev_b32 s4, -2
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX8-NEXT: v_max_i32_e32 v31, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v31, vcc, s4, v31
; GFX8-NEXT: v_max_i32_e32 v16, v31, v16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s5, 1
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX8-NEXT: v_min_i32_e32 v31, -1, v0
; GFX8-NEXT: v_subrev_u32_e32 v31, vcc, s5, v31
; GFX8-NEXT: v_min_i32_e32 v16, v16, v31
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u32_e32 v0, vcc, v0, v16
; GFX8-NEXT: v_max_i32_e32 v16, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, s4, v16
; GFX8-NEXT: v_max_i32_e32 v16, v16, v17
; GFX8-NEXT: v_min_i32_e32 v17, -1, v1
; GFX8-NEXT: v_subrev_u32_e32 v17, vcc, s5, v17
; GFX8-NEXT: v_min_i32_e32 v16, v16, v17
; GFX8-NEXT: v_sub_u32_e32 v1, vcc, v1, v16
; GFX8-NEXT: v_max_i32_e32 v16, -1, v2
; GFX8-NEXT: v_subrev_u32_e32 v16, vcc, s4, v16
; GFX8-NEXT: v_min_i32_e32 v17, -1, v2
; GFX8-NEXT: v_max_i32_e32 v16, v16, v18
; GFX8-NEXT: v_subrev_u32_e32 v17, vcc, s5, v17
; GFX8-NEXT: v_min_i32_e32 v16, v16, v17
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, v2, v16
; GFX8-NEXT: v_bfrev_b32_e32 v16, -2
; GFX8-NEXT: v_max_i32_e32 v17, -1, v3
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_max_i32_e32 v17, v17, v19
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_bfrev_b32_e32 v18, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v19, -1, v3
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v3, vcc, v3, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v4
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_max_i32_e32 v17, v17, v20
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX8-NEXT: buffer_load_dword v20, off, s[0:3], s32
; GFX8-NEXT: v_min_i32_e32 v19, -1, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v4, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v5
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v5
; GFX8-NEXT: v_max_i32_e32 v17, v17, v21
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v5, vcc, v5, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v6
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v6
; GFX8-NEXT: v_max_i32_e32 v17, v17, v22
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v6, vcc, v6, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v7
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v7
; GFX8-NEXT: v_max_i32_e32 v17, v17, v23
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v7, vcc, v7, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v8
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v8
; GFX8-NEXT: v_max_i32_e32 v17, v17, v24
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v8, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v9
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v9
; GFX8-NEXT: v_max_i32_e32 v17, v17, v25
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v9, vcc, v9, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v10
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v10
; GFX8-NEXT: v_max_i32_e32 v17, v17, v26
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v10, vcc, v10, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v11
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v11
; GFX8-NEXT: v_max_i32_e32 v17, v17, v27
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v11, vcc, v11, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v12
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v12
; GFX8-NEXT: v_max_i32_e32 v17, v17, v28
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v12, vcc, v12, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v13
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v13
; GFX8-NEXT: v_max_i32_e32 v17, v17, v29
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v13, vcc, v13, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v14
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v19, -1, v14
; GFX8-NEXT: v_max_i32_e32 v17, v17, v30
; GFX8-NEXT: v_sub_u32_e32 v19, vcc, v19, v18
; GFX8-NEXT: v_min_i32_e32 v17, v17, v19
; GFX8-NEXT: v_sub_u32_e32 v14, vcc, v14, v17
; GFX8-NEXT: v_max_i32_e32 v17, -1, v15
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, v17, v16
; GFX8-NEXT: v_min_i32_e32 v17, -1, v15
; GFX8-NEXT: v_sub_u32_e32 v17, vcc, v17, v18
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_max_i32_e32 v16, v16, v20
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i32_e32 v16, v16, v17
; GFX8-NEXT: v_sub_u32_e32 v15, vcc, v15, v16
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v16i32:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v0, v0, v16 clamp
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX9-NEXT: buffer_load_dword v16, off, s[0:3], s32
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i32 v1, v1, v17 clamp
; GFX9-NEXT: v_sub_i32 v2, v2, v18 clamp
; GFX9-NEXT: v_sub_i32 v3, v3, v19 clamp
; GFX9-NEXT: v_sub_i32 v4, v4, v20 clamp
; GFX9-NEXT: v_sub_i32 v5, v5, v21 clamp
; GFX9-NEXT: v_sub_i32 v6, v6, v22 clamp
; GFX9-NEXT: v_sub_i32 v7, v7, v23 clamp
; GFX9-NEXT: v_sub_i32 v8, v8, v24 clamp
; GFX9-NEXT: v_sub_i32 v9, v9, v25 clamp
; GFX9-NEXT: v_sub_i32 v10, v10, v26 clamp
; GFX9-NEXT: v_sub_i32 v11, v11, v27 clamp
; GFX9-NEXT: v_sub_i32 v12, v12, v28 clamp
; GFX9-NEXT: v_sub_i32 v13, v13, v29 clamp
; GFX9-NEXT: v_sub_i32 v14, v14, v30 clamp
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX9-NEXT: s_waitcnt vmcnt(0)
; GFX9-NEXT: v_sub_i32 v15, v15, v16 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v16i32:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX10-NEXT: buffer_load_dword v31, off, s[0:3], s32
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, v0, v16 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, v1, v17 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, v2, v18 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, v3, v19 clamp
; GFX10-NEXT: v_sub_nc_i32 v4, v4, v20 clamp
; GFX10-NEXT: v_sub_nc_i32 v5, v5, v21 clamp
; GFX10-NEXT: v_sub_nc_i32 v6, v6, v22 clamp
; GFX10-NEXT: v_sub_nc_i32 v7, v7, v23 clamp
; GFX10-NEXT: v_sub_nc_i32 v8, v8, v24 clamp
; GFX10-NEXT: v_sub_nc_i32 v9, v9, v25 clamp
; GFX10-NEXT: v_sub_nc_i32 v10, v10, v26 clamp
; GFX10-NEXT: v_sub_nc_i32 v11, v11, v27 clamp
; GFX10-NEXT: v_sub_nc_i32 v12, v12, v28 clamp
; GFX10-NEXT: v_sub_nc_i32 v13, v13, v29 clamp
; GFX10-NEXT: v_sub_nc_i32 v14, v14, v30 clamp
AMDGPU: Enable fixed function ABI by default Code using indirect calls is broken without this, and there isn't really much value in supporting the old attempt to vary the argument placement based on uses. This resulted in more argument shuffling code anyway. Also have the option stop implying all inputs need to be passed. This will no rely on the amdgpu-no-* attributes to avoid passing unnecessary values.
2021-08-15 07:10:46 +08:00
; GFX10-NEXT: s_waitcnt vmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v15, v15, v31 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
define amdgpu_ps <16 x i32> @s_ssubsat_v16i32(<16 x i32> inreg %lhs, <16 x i32> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v16i32:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_brev_b32 s32, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s34, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s33, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s34, s34, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s35, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s35, s35, s33
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s16, s34, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s16, s16, s35
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s34, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s34, s34, s33
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s16, s16, s34
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s18
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s19
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s20
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s5, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s5, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s21
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s6, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s6, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s22
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s7, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s7, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s23
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s7, s7, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s8, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s8, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s24
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s8, s8, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s9, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s9, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s25
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s10, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s10, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s26
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s11, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s11, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s27
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s11, s11, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s12, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s12, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s28
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s12, s12, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s13, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s13, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s29
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s13, s13, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s14, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s14, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s30
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s14, s14, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s15, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s17, s15, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s16, s16, s31
; GFX6-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s15, s15, s16
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v16i32:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_brev_b32 s32, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s34, s0, -1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_brev_b32 s33, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s34, s34, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s35, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s35, s35, s33
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s16, s34, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s16, s16, s35
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s34, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s34, s34, s33
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s16, s16, s34
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s18
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s19
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s20
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s5, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s5, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s21
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s6, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s6, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s22
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s7, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s7, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s23
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s7, s7, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s8, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s8, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s24
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s9, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s9, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s25
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s10, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s10, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s26
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s10, s10, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s11, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s11, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s27
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s11, s11, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s12, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s12, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s28
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s12, s12, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s13, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s13, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s29
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s13, s13, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s14, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s14, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s30
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s14, s14, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s15, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s32
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s17, s15, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s17, s17, s33
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s16, s16, s31
; GFX8-NEXT: s_min_i32 s16, s16, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s15, s15, s16
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v16i32:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s16
; GFX9-NEXT: v_mov_b32_e32 v1, s17
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
; GFX9-NEXT: v_mov_b32_e32 v4, s20
; GFX9-NEXT: v_mov_b32_e32 v5, s21
; GFX9-NEXT: v_mov_b32_e32 v6, s22
; GFX9-NEXT: v_mov_b32_e32 v7, s23
; GFX9-NEXT: v_mov_b32_e32 v8, s24
; GFX9-NEXT: v_mov_b32_e32 v9, s25
; GFX9-NEXT: v_mov_b32_e32 v10, s26
; GFX9-NEXT: v_mov_b32_e32 v11, s27
; GFX9-NEXT: v_mov_b32_e32 v12, s28
; GFX9-NEXT: v_mov_b32_e32 v13, s29
; GFX9-NEXT: v_mov_b32_e32 v14, s30
; GFX9-NEXT: v_mov_b32_e32 v15, s31
; GFX9-NEXT: v_sub_i32 v0, s0, v0 clamp
; GFX9-NEXT: v_sub_i32 v1, s1, v1 clamp
; GFX9-NEXT: v_sub_i32 v2, s2, v2 clamp
; GFX9-NEXT: v_sub_i32 v3, s3, v3 clamp
; GFX9-NEXT: v_sub_i32 v4, s4, v4 clamp
; GFX9-NEXT: v_sub_i32 v5, s5, v5 clamp
; GFX9-NEXT: v_sub_i32 v6, s6, v6 clamp
; GFX9-NEXT: v_sub_i32 v7, s7, v7 clamp
; GFX9-NEXT: v_sub_i32 v8, s8, v8 clamp
; GFX9-NEXT: v_sub_i32 v9, s9, v9 clamp
; GFX9-NEXT: v_sub_i32 v10, s10, v10 clamp
; GFX9-NEXT: v_sub_i32 v11, s11, v11 clamp
; GFX9-NEXT: v_sub_i32 v12, s12, v12 clamp
; GFX9-NEXT: v_sub_i32 v13, s13, v13 clamp
; GFX9-NEXT: v_sub_i32 v14, s14, v14 clamp
; GFX9-NEXT: v_sub_i32 v15, s15, v15 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: v_readfirstlane_b32 s4, v4
; GFX9-NEXT: v_readfirstlane_b32 s5, v5
; GFX9-NEXT: v_readfirstlane_b32 s6, v6
; GFX9-NEXT: v_readfirstlane_b32 s7, v7
; GFX9-NEXT: v_readfirstlane_b32 s8, v8
; GFX9-NEXT: v_readfirstlane_b32 s9, v9
; GFX9-NEXT: v_readfirstlane_b32 s10, v10
; GFX9-NEXT: v_readfirstlane_b32 s11, v11
; GFX9-NEXT: v_readfirstlane_b32 s12, v12
; GFX9-NEXT: v_readfirstlane_b32 s13, v13
; GFX9-NEXT: v_readfirstlane_b32 s14, v14
; GFX9-NEXT: v_readfirstlane_b32 s15, v15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v16i32:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i32 v0, s0, s16 clamp
; GFX10-NEXT: v_sub_nc_i32 v1, s1, s17 clamp
; GFX10-NEXT: v_sub_nc_i32 v2, s2, s18 clamp
; GFX10-NEXT: v_sub_nc_i32 v3, s3, s19 clamp
; GFX10-NEXT: v_sub_nc_i32 v4, s4, s20 clamp
; GFX10-NEXT: v_sub_nc_i32 v5, s5, s21 clamp
; GFX10-NEXT: v_sub_nc_i32 v6, s6, s22 clamp
; GFX10-NEXT: v_sub_nc_i32 v7, s7, s23 clamp
; GFX10-NEXT: v_sub_nc_i32 v8, s8, s24 clamp
; GFX10-NEXT: v_sub_nc_i32 v9, s9, s25 clamp
; GFX10-NEXT: v_sub_nc_i32 v10, s10, s26 clamp
; GFX10-NEXT: v_sub_nc_i32 v11, s11, s27 clamp
; GFX10-NEXT: v_sub_nc_i32 v12, s12, s28 clamp
; GFX10-NEXT: v_sub_nc_i32 v13, s13, s29 clamp
; GFX10-NEXT: v_sub_nc_i32 v14, s14, s30 clamp
; GFX10-NEXT: v_sub_nc_i32 v15, s15, s31 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: v_readfirstlane_b32 s8, v8
; GFX10-NEXT: v_readfirstlane_b32 s9, v9
; GFX10-NEXT: v_readfirstlane_b32 s10, v10
; GFX10-NEXT: v_readfirstlane_b32 s11, v11
; GFX10-NEXT: v_readfirstlane_b32 s12, v12
; GFX10-NEXT: v_readfirstlane_b32 s13, v13
; GFX10-NEXT: v_readfirstlane_b32 s14, v14
; GFX10-NEXT: v_readfirstlane_b32 s15, v15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32> %lhs, <16 x i32> %rhs)
ret <16 x i32> %result
}
define i16 @v_ssubsat_i16(i16 %lhs, i16 %rhs) {
; GFX6-LABEL: v_ssubsat_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x7fffffff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, 0x80000000, v3
; GFX6-NEXT: v_max_i32_e32 v1, v2, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v3
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v2, 0x7fff, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v3, 0x8000, v3
; GFX8-NEXT: v_max_i16_e32 v1, v2, v1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v3
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i16 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
define amdgpu_ps i16 @s_ssubsat_i16(i16 inreg %lhs, i16 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s2, s2, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s3, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, 0x80000000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s2, s1
; GFX6-NEXT: s_min_i32 s1, s1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s1
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s2, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s3, -1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s4, s2, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, 0x7fff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s2, s2, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s3, s4
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, 0xffff8000
; GFX8-NEXT: s_max_i32 s1, s3, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s2, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s1, s1, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i16:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i16:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, s0, s1 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
ret i16 %result
}
define amdgpu_ps half @ssubsat_i16_sv(i16 inreg %lhs, i16 %rhs) {
; GFX6-LABEL: ssubsat_i16_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, 0x7fffffff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, 0x80000000
; GFX6-NEXT: v_max_i32_e32 v0, s1, v0
; GFX6-NEXT: v_min_i32_e32 v0, s2, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i16_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s1, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s2, -1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s3, s1, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s1, s1, s2
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, 0xffff8000
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_max_i16_e32 v0, s3, v0
; GFX8-NEXT: v_min_i16_e32 v0, s1, v0
; GFX8-NEXT: v_sub_u16_e32 v0, s0, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i16_sv:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i16 v0, s0, v0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i16_sv:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, s0, v0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
}
define amdgpu_ps half @ssubsat_i16_vs(i16 %lhs, i16 inreg %rhs) {
; GFX6-LABEL: ssubsat_i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: v_max_i32_e32 v1, -1, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: v_subrev_i32_e32 v1, vcc, 0x7fffffff, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v2, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, 0x80000000, v2
; GFX6-NEXT: v_max_i32_e32 v1, s0, v1
; GFX6-NEXT: v_min_i32_e32 v1, v1, v2
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i16_vs:
; GFX8: ; %bb.0:
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v1, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v1, 0x7fff, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v2, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v2, 0x8000, v2
; GFX8-NEXT: v_max_i16_e32 v1, s0, v1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v2
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i16_vs:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_sub_i16 v0, v0, s0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i16_vs:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_sub_nc_i16 v0, v0, s0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i16 @llvm.ssub.sat.i16(i16 %lhs, i16 %rhs)
%cast = bitcast i16 %result to half
ret half %cast
}
define <2 x i16> @v_ssubsat_v2i16(<2 x i16> %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v4, -1, v0
GlobalISel: Use DAG call lowering infrastructure in a more compatible way Unfortunately the current call lowering code is built on top of the legacy MVT/DAG based code. However, GlobalISel was not using it the same way. In short, the DAG passes legalized types to the assignment function, and GlobalISel was passing the original raw type if it was simple. I do believe the DAG lowering is conceptually broken since it requires picking a type up front before knowing how/where the value will be passed. This ends up being a problem for AArch64, which wants to pass i1/i8/i16 values as a different size if passed on the stack or in registers. The argument type decision is split across 3 different places which is hard to follow. SelectionDAG builder uses getRegisterTypeForCallingConv to pick a legal type, tablegen gives the illusion of controlling the type, and the target may have additional hacks in the C++ part of the call lowering. AArch64 hacks around this by not using the standard AnalyzeFormalArguments and special casing i1/i8/i16 by looking at the underlying type of the original IR argument. I believe people have generally assumed the calling convention code is processing the original types, and I've discovered a number of dead paths in several targets. x86 actually relies on the opposite behavior from AArch64, and relies on x86_32 and x86_64 sharing calling convention code where the 64-bit cases implicitly do not work on x86_32 due to using the pre-legalized types. AMDGPU targets without legal i16/f16 have always used a broken ABI that promotes to i32/f32. GlobalISel accidentally fixed this to be the ABI we should have, but this fixes it so we're using the worse ABI that is compatible with the DAG. Ideally we would fix the DAG to match the old GlobalISel behavior, but I don't wish to fight that battle. A new native GlobalISel call lowering framework should let the target process the incoming types directly. CCValAssigns select a "ValVT" and "LocVT" but the meanings of these aren't entirely clear. Different targets don't use them consistently, even within their own call lowering code. My current belief is the intent was "ValVT" is supposed to be the legalized value type to use in the end, and and LocVT was supposed to be the ABI passed type (which is also legalized). With the default CCState::Analyze functions always passing the same type for these arguments, these only differ when the TableGen part of the lowering decide to promote the type from one legal type to another. AArch64's i1/i8/i16 hack ends up inverting the meanings of these values, so I had to add an additional hack to let the target interpret how large the argument memory is. Since targets don't consistently interpret ValVT and LocVT, this doesn't produce quite equivalent code to the initial DAG lowerings. I've opted to consistently interpret LocVT as the in-memory size for stack passed values, and ValVT as the register type to assign from that memory. We therefore produce extending loads directly out of the IRTranslator, whereas the DAG would emit regular loads of smaller values. This will also produce loads/stores that are wider than the argument value if the allocated stack slot is larger (and there will be undef padding bytes). If we had the optimizations to reduce load/stores based on truncated values, this wouldn't produce a different end result. Since ValVT/LocVT are more consistently interpreted, we now will emit more G_BITCASTS as requested by the CCAssignFn. For example AArch64 was directly assigning types to some physical vector registers which according to the tablegen spec should have been casted to a vector with a different element type. This also moves the responsibility for inserting G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the generic code, which is closer to how SelectionDAGBuilder works. I had to xfail an x86 test since I don't see a quick way to fix it right now (I filed bug 50035 for this). It's broken independently of this change, and only triggers since now we end up with more ands which hit the improperly handled selection pattern. I also observed that FP arguments that need promotion (e.g. f16 passed as f32) are broken, and use regular G_TRUNC and G_ANYEXT. TLDR; the current call lowering infrastructure is bad and nobody has ever understood how it chooses types.
2021-04-14 01:45:35 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s4, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v5, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s5, v5
GlobalISel: Use DAG call lowering infrastructure in a more compatible way Unfortunately the current call lowering code is built on top of the legacy MVT/DAG based code. However, GlobalISel was not using it the same way. In short, the DAG passes legalized types to the assignment function, and GlobalISel was passing the original raw type if it was simple. I do believe the DAG lowering is conceptually broken since it requires picking a type up front before knowing how/where the value will be passed. This ends up being a problem for AArch64, which wants to pass i1/i8/i16 values as a different size if passed on the stack or in registers. The argument type decision is split across 3 different places which is hard to follow. SelectionDAG builder uses getRegisterTypeForCallingConv to pick a legal type, tablegen gives the illusion of controlling the type, and the target may have additional hacks in the C++ part of the call lowering. AArch64 hacks around this by not using the standard AnalyzeFormalArguments and special casing i1/i8/i16 by looking at the underlying type of the original IR argument. I believe people have generally assumed the calling convention code is processing the original types, and I've discovered a number of dead paths in several targets. x86 actually relies on the opposite behavior from AArch64, and relies on x86_32 and x86_64 sharing calling convention code where the 64-bit cases implicitly do not work on x86_32 due to using the pre-legalized types. AMDGPU targets without legal i16/f16 have always used a broken ABI that promotes to i32/f32. GlobalISel accidentally fixed this to be the ABI we should have, but this fixes it so we're using the worse ABI that is compatible with the DAG. Ideally we would fix the DAG to match the old GlobalISel behavior, but I don't wish to fight that battle. A new native GlobalISel call lowering framework should let the target process the incoming types directly. CCValAssigns select a "ValVT" and "LocVT" but the meanings of these aren't entirely clear. Different targets don't use them consistently, even within their own call lowering code. My current belief is the intent was "ValVT" is supposed to be the legalized value type to use in the end, and and LocVT was supposed to be the ABI passed type (which is also legalized). With the default CCState::Analyze functions always passing the same type for these arguments, these only differ when the TableGen part of the lowering decide to promote the type from one legal type to another. AArch64's i1/i8/i16 hack ends up inverting the meanings of these values, so I had to add an additional hack to let the target interpret how large the argument memory is. Since targets don't consistently interpret ValVT and LocVT, this doesn't produce quite equivalent code to the initial DAG lowerings. I've opted to consistently interpret LocVT as the in-memory size for stack passed values, and ValVT as the register type to assign from that memory. We therefore produce extending loads directly out of the IRTranslator, whereas the DAG would emit regular loads of smaller values. This will also produce loads/stores that are wider than the argument value if the allocated stack slot is larger (and there will be undef padding bytes). If we had the optimizations to reduce load/stores based on truncated values, this wouldn't produce a different end result. Since ValVT/LocVT are more consistently interpreted, we now will emit more G_BITCASTS as requested by the CCAssignFn. For example AArch64 was directly assigning types to some physical vector registers which according to the tablegen spec should have been casted to a vector with a different element type. This also moves the responsibility for inserting G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the generic code, which is closer to how SelectionDAGBuilder works. I had to xfail an x86 test since I don't see a quick way to fix it right now (I filed bug 50035 for this). It's broken independently of this change, and only triggers since now we end up with more ands which hit the improperly handled selection pattern. I also observed that FP arguments that need promotion (e.g. f16 passed as f32) are broken, and use regular G_TRUNC and G_ANYEXT. TLDR; the current call lowering infrastructure is bad and nobody has ever understood how it chooses types.
2021-04-14 01:45:35 +08:00
; GFX6-NEXT: v_max_i32_e32 v2, v4, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v5
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v3
; GFX6-NEXT: v_max_i32_e32 v3, -1, v1
GlobalISel: Use DAG call lowering infrastructure in a more compatible way Unfortunately the current call lowering code is built on top of the legacy MVT/DAG based code. However, GlobalISel was not using it the same way. In short, the DAG passes legalized types to the assignment function, and GlobalISel was passing the original raw type if it was simple. I do believe the DAG lowering is conceptually broken since it requires picking a type up front before knowing how/where the value will be passed. This ends up being a problem for AArch64, which wants to pass i1/i8/i16 values as a different size if passed on the stack or in registers. The argument type decision is split across 3 different places which is hard to follow. SelectionDAG builder uses getRegisterTypeForCallingConv to pick a legal type, tablegen gives the illusion of controlling the type, and the target may have additional hacks in the C++ part of the call lowering. AArch64 hacks around this by not using the standard AnalyzeFormalArguments and special casing i1/i8/i16 by looking at the underlying type of the original IR argument. I believe people have generally assumed the calling convention code is processing the original types, and I've discovered a number of dead paths in several targets. x86 actually relies on the opposite behavior from AArch64, and relies on x86_32 and x86_64 sharing calling convention code where the 64-bit cases implicitly do not work on x86_32 due to using the pre-legalized types. AMDGPU targets without legal i16/f16 have always used a broken ABI that promotes to i32/f32. GlobalISel accidentally fixed this to be the ABI we should have, but this fixes it so we're using the worse ABI that is compatible with the DAG. Ideally we would fix the DAG to match the old GlobalISel behavior, but I don't wish to fight that battle. A new native GlobalISel call lowering framework should let the target process the incoming types directly. CCValAssigns select a "ValVT" and "LocVT" but the meanings of these aren't entirely clear. Different targets don't use them consistently, even within their own call lowering code. My current belief is the intent was "ValVT" is supposed to be the legalized value type to use in the end, and and LocVT was supposed to be the ABI passed type (which is also legalized). With the default CCState::Analyze functions always passing the same type for these arguments, these only differ when the TableGen part of the lowering decide to promote the type from one legal type to another. AArch64's i1/i8/i16 hack ends up inverting the meanings of these values, so I had to add an additional hack to let the target interpret how large the argument memory is. Since targets don't consistently interpret ValVT and LocVT, this doesn't produce quite equivalent code to the initial DAG lowerings. I've opted to consistently interpret LocVT as the in-memory size for stack passed values, and ValVT as the register type to assign from that memory. We therefore produce extending loads directly out of the IRTranslator, whereas the DAG would emit regular loads of smaller values. This will also produce loads/stores that are wider than the argument value if the allocated stack slot is larger (and there will be undef padding bytes). If we had the optimizations to reduce load/stores based on truncated values, this wouldn't produce a different end result. Since ValVT/LocVT are more consistently interpreted, we now will emit more G_BITCASTS as requested by the CCAssignFn. For example AArch64 was directly assigning types to some physical vector registers which according to the tablegen spec should have been casted to a vector with a different element type. This also moves the responsibility for inserting G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the generic code, which is closer to how SelectionDAGBuilder works. I had to xfail an x86 test since I don't see a quick way to fix it right now (I filed bug 50035 for this). It's broken independently of this change, and only triggers since now we end up with more ands which hit the improperly handled selection pattern. I also observed that FP arguments that need promotion (e.g. f16 passed as f32) are broken, and use regular G_TRUNC and G_ANYEXT. TLDR; the current call lowering infrastructure is bad and nobody has ever understood how it chooses types.
2021-04-14 01:45:35 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s4, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v4, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s5, v4
; GFX6-NEXT: v_max_i32_e32 v2, v3, v2
; GFX6-NEXT: v_min_i32_e32 v2, v2, v4
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
GlobalISel: Merge and cleanup more AMDGPU call lowering code This merges more AMDGPU ABI lowering code into the generic call lowering. Start cleaning up by factoring away more of the pack/unpack logic into the buildCopy{To|From}Parts functions. These could use more improvement, and the SelectionDAG versions are significantly more complex, and we'll eventually have to emulate all of those cases too. This is mostly NFC, but does result in some minor instruction reordering. It also removes some of the limitations with mismatched sizes the old code had. However, similarly to the merge on the input, this is forcing gfx6/gfx7 to use the gfx8+ ABI (which is what we actually want, but SelectionDAG is stuck using the weird emergent ABI). This also changes the load/store size for stack passed EVTs for AArch64, which makes it consistent with the DAG behavior.
2021-02-10 01:09:20 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
GlobalISel: Use DAG call lowering infrastructure in a more compatible way Unfortunately the current call lowering code is built on top of the legacy MVT/DAG based code. However, GlobalISel was not using it the same way. In short, the DAG passes legalized types to the assignment function, and GlobalISel was passing the original raw type if it was simple. I do believe the DAG lowering is conceptually broken since it requires picking a type up front before knowing how/where the value will be passed. This ends up being a problem for AArch64, which wants to pass i1/i8/i16 values as a different size if passed on the stack or in registers. The argument type decision is split across 3 different places which is hard to follow. SelectionDAG builder uses getRegisterTypeForCallingConv to pick a legal type, tablegen gives the illusion of controlling the type, and the target may have additional hacks in the C++ part of the call lowering. AArch64 hacks around this by not using the standard AnalyzeFormalArguments and special casing i1/i8/i16 by looking at the underlying type of the original IR argument. I believe people have generally assumed the calling convention code is processing the original types, and I've discovered a number of dead paths in several targets. x86 actually relies on the opposite behavior from AArch64, and relies on x86_32 and x86_64 sharing calling convention code where the 64-bit cases implicitly do not work on x86_32 due to using the pre-legalized types. AMDGPU targets without legal i16/f16 have always used a broken ABI that promotes to i32/f32. GlobalISel accidentally fixed this to be the ABI we should have, but this fixes it so we're using the worse ABI that is compatible with the DAG. Ideally we would fix the DAG to match the old GlobalISel behavior, but I don't wish to fight that battle. A new native GlobalISel call lowering framework should let the target process the incoming types directly. CCValAssigns select a "ValVT" and "LocVT" but the meanings of these aren't entirely clear. Different targets don't use them consistently, even within their own call lowering code. My current belief is the intent was "ValVT" is supposed to be the legalized value type to use in the end, and and LocVT was supposed to be the ABI passed type (which is also legalized). With the default CCState::Analyze functions always passing the same type for these arguments, these only differ when the TableGen part of the lowering decide to promote the type from one legal type to another. AArch64's i1/i8/i16 hack ends up inverting the meanings of these values, so I had to add an additional hack to let the target interpret how large the argument memory is. Since targets don't consistently interpret ValVT and LocVT, this doesn't produce quite equivalent code to the initial DAG lowerings. I've opted to consistently interpret LocVT as the in-memory size for stack passed values, and ValVT as the register type to assign from that memory. We therefore produce extending loads directly out of the IRTranslator, whereas the DAG would emit regular loads of smaller values. This will also produce loads/stores that are wider than the argument value if the allocated stack slot is larger (and there will be undef padding bytes). If we had the optimizations to reduce load/stores based on truncated values, this wouldn't produce a different end result. Since ValVT/LocVT are more consistently interpreted, we now will emit more G_BITCASTS as requested by the CCAssignFn. For example AArch64 was directly assigning types to some physical vector registers which according to the tablegen spec should have been casted to a vector with a different element type. This also moves the responsibility for inserting G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the generic code, which is closer to how SelectionDAGBuilder works. I had to xfail an x86 test since I don't see a quick way to fix it right now (I filed bug 50035 for this). It's broken independently of this change, and only triggers since now we end up with more ands which hit the improperly handled selection pattern. I also observed that FP arguments that need promotion (e.g. f16 passed as f32) are broken, and use regular G_TRUNC and G_ANYEXT. TLDR; the current call lowering infrastructure is bad and nobody has ever understood how it chooses types.
2021-04-14 01:45:35 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v3, -1, v0
; GFX8-NEXT: s_movk_i32 s5, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v3, s4, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v4, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v2, 16, v0
; GFX8-NEXT: v_subrev_u16_e32 v4, s5, v4
; GFX8-NEXT: v_max_i16_e32 v3, v3, v1
; GFX8-NEXT: v_min_i16_e32 v3, v3, v4
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v4, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v4, s4, v4
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v5, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v5, s5, v5
; GFX8-NEXT: v_max_i16_sdwa v1, v4, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_min_i16_e32 v1, v1, v5
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v3
; GFX8-NEXT: v_sub_u16_sdwa v1, v2, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v1 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
ret <2 x i16> %result
}
define amdgpu_ps i32 @s_ssubsat_v2i16(<2 x i16> inreg %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s4, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s0, -1
GlobalISel: Use DAG call lowering infrastructure in a more compatible way Unfortunately the current call lowering code is built on top of the legacy MVT/DAG based code. However, GlobalISel was not using it the same way. In short, the DAG passes legalized types to the assignment function, and GlobalISel was passing the original raw type if it was simple. I do believe the DAG lowering is conceptually broken since it requires picking a type up front before knowing how/where the value will be passed. This ends up being a problem for AArch64, which wants to pass i1/i8/i16 values as a different size if passed on the stack or in registers. The argument type decision is split across 3 different places which is hard to follow. SelectionDAG builder uses getRegisterTypeForCallingConv to pick a legal type, tablegen gives the illusion of controlling the type, and the target may have additional hacks in the C++ part of the call lowering. AArch64 hacks around this by not using the standard AnalyzeFormalArguments and special casing i1/i8/i16 by looking at the underlying type of the original IR argument. I believe people have generally assumed the calling convention code is processing the original types, and I've discovered a number of dead paths in several targets. x86 actually relies on the opposite behavior from AArch64, and relies on x86_32 and x86_64 sharing calling convention code where the 64-bit cases implicitly do not work on x86_32 due to using the pre-legalized types. AMDGPU targets without legal i16/f16 have always used a broken ABI that promotes to i32/f32. GlobalISel accidentally fixed this to be the ABI we should have, but this fixes it so we're using the worse ABI that is compatible with the DAG. Ideally we would fix the DAG to match the old GlobalISel behavior, but I don't wish to fight that battle. A new native GlobalISel call lowering framework should let the target process the incoming types directly. CCValAssigns select a "ValVT" and "LocVT" but the meanings of these aren't entirely clear. Different targets don't use them consistently, even within their own call lowering code. My current belief is the intent was "ValVT" is supposed to be the legalized value type to use in the end, and and LocVT was supposed to be the ABI passed type (which is also legalized). With the default CCState::Analyze functions always passing the same type for these arguments, these only differ when the TableGen part of the lowering decide to promote the type from one legal type to another. AArch64's i1/i8/i16 hack ends up inverting the meanings of these values, so I had to add an additional hack to let the target interpret how large the argument memory is. Since targets don't consistently interpret ValVT and LocVT, this doesn't produce quite equivalent code to the initial DAG lowerings. I've opted to consistently interpret LocVT as the in-memory size for stack passed values, and ValVT as the register type to assign from that memory. We therefore produce extending loads directly out of the IRTranslator, whereas the DAG would emit regular loads of smaller values. This will also produce loads/stores that are wider than the argument value if the allocated stack slot is larger (and there will be undef padding bytes). If we had the optimizations to reduce load/stores based on truncated values, this wouldn't produce a different end result. Since ValVT/LocVT are more consistently interpreted, we now will emit more G_BITCASTS as requested by the CCAssignFn. For example AArch64 was directly assigning types to some physical vector registers which according to the tablegen spec should have been casted to a vector with a different element type. This also moves the responsibility for inserting G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the generic code, which is closer to how SelectionDAGBuilder works. I had to xfail an x86 test since I don't see a quick way to fix it right now (I filed bug 50035 for this). It's broken independently of this change, and only triggers since now we end up with more ands which hit the improperly handled selection pattern. I also observed that FP arguments that need promotion (e.g. f16 passed as f32) are broken, and use regular G_TRUNC and G_ANYEXT. TLDR; the current call lowering infrastructure is bad and nobody has ever understood how it chooses types.
2021-04-14 01:45:35 +08:00
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s7, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s7, s7, s5
GlobalISel: Use DAG call lowering infrastructure in a more compatible way Unfortunately the current call lowering code is built on top of the legacy MVT/DAG based code. However, GlobalISel was not using it the same way. In short, the DAG passes legalized types to the assignment function, and GlobalISel was passing the original raw type if it was simple. I do believe the DAG lowering is conceptually broken since it requires picking a type up front before knowing how/where the value will be passed. This ends up being a problem for AArch64, which wants to pass i1/i8/i16 values as a different size if passed on the stack or in registers. The argument type decision is split across 3 different places which is hard to follow. SelectionDAG builder uses getRegisterTypeForCallingConv to pick a legal type, tablegen gives the illusion of controlling the type, and the target may have additional hacks in the C++ part of the call lowering. AArch64 hacks around this by not using the standard AnalyzeFormalArguments and special casing i1/i8/i16 by looking at the underlying type of the original IR argument. I believe people have generally assumed the calling convention code is processing the original types, and I've discovered a number of dead paths in several targets. x86 actually relies on the opposite behavior from AArch64, and relies on x86_32 and x86_64 sharing calling convention code where the 64-bit cases implicitly do not work on x86_32 due to using the pre-legalized types. AMDGPU targets without legal i16/f16 have always used a broken ABI that promotes to i32/f32. GlobalISel accidentally fixed this to be the ABI we should have, but this fixes it so we're using the worse ABI that is compatible with the DAG. Ideally we would fix the DAG to match the old GlobalISel behavior, but I don't wish to fight that battle. A new native GlobalISel call lowering framework should let the target process the incoming types directly. CCValAssigns select a "ValVT" and "LocVT" but the meanings of these aren't entirely clear. Different targets don't use them consistently, even within their own call lowering code. My current belief is the intent was "ValVT" is supposed to be the legalized value type to use in the end, and and LocVT was supposed to be the ABI passed type (which is also legalized). With the default CCState::Analyze functions always passing the same type for these arguments, these only differ when the TableGen part of the lowering decide to promote the type from one legal type to another. AArch64's i1/i8/i16 hack ends up inverting the meanings of these values, so I had to add an additional hack to let the target interpret how large the argument memory is. Since targets don't consistently interpret ValVT and LocVT, this doesn't produce quite equivalent code to the initial DAG lowerings. I've opted to consistently interpret LocVT as the in-memory size for stack passed values, and ValVT as the register type to assign from that memory. We therefore produce extending loads directly out of the IRTranslator, whereas the DAG would emit regular loads of smaller values. This will also produce loads/stores that are wider than the argument value if the allocated stack slot is larger (and there will be undef padding bytes). If we had the optimizations to reduce load/stores based on truncated values, this wouldn't produce a different end result. Since ValVT/LocVT are more consistently interpreted, we now will emit more G_BITCASTS as requested by the CCAssignFn. For example AArch64 was directly assigning types to some physical vector registers which according to the tablegen spec should have been casted to a vector with a different element type. This also moves the responsibility for inserting G_ASSERT_SEXT/G_ASSERT_ZEXT from the target ValueHandlers into the generic code, which is closer to how SelectionDAGBuilder works. I had to xfail an x86 test since I don't see a quick way to fix it right now (I filed bug 50035 for this). It's broken independently of this change, and only triggers since now we end up with more ands which hit the improperly handled selection pattern. I also observed that FP arguments that need promotion (e.g. f16 passed as f32) are broken, and use regular G_TRUNC and G_ANYEXT. TLDR; the current call lowering infrastructure is bad and nobody has ever understood how it chooses types.
2021-04-14 01:45:35 +08:00
; GFX6-NEXT: s_max_i32 s2, s6, s2
; GFX6-NEXT: s_min_i32 s2, s2, s7
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_sub_i32 s0, s0, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s2, s3, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s3, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s2, s3, s2
; GFX6-NEXT: s_min_i32 s2, s2, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s2
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_mov_b32 s2, 0xffff
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s0, s0, s2
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v2i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s6, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s7, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s8, s6, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s3, s1, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s5, 0x8000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s6, s6, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s5
; GFX8-NEXT: s_max_i32 s1, s8, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s1, s1
; GFX8-NEXT: s_sext_i32_i16 s6, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s2, s0, 16
; GFX8-NEXT: s_min_i32 s1, s1, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s1
; GFX8-NEXT: s_sext_i32_i16 s1, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s6, s1, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s6, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s1, s1, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s5
; GFX8-NEXT: s_max_i32 s3, s4, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s1, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s1, s3, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s2, s1
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s1, s1, 16
; GFX8-NEXT: s_or_b32 s0, s0, s1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v2i16:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s1
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i16:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to i32
ret i32 %cast
}
define amdgpu_ps float @ssubsat_v2i16_sv(<2 x i16> inreg %lhs, <2 x i16> %rhs) {
; GFX6-LABEL: ssubsat_v2i16_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s2, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s3, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s4, s4, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s5, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s3
; GFX6-NEXT: v_max_i32_e32 v0, s4, v0
; GFX6-NEXT: v_min_i32_e32 v0, s5, v0
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, s0, v0
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s1, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s2, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s2, s2, s3
; GFX6-NEXT: v_max_i32_e32 v1, s1, v1
; GFX6-NEXT: v_min_i32_e32 v1, s2, v1
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, s0, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_v2i16_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s4, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s5, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s2, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s6, s4, s5
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s3, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s4, s5
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s3
; GFX8-NEXT: v_max_i16_e32 v1, s6, v0
; GFX8-NEXT: v_min_i16_e32 v1, s4, v1
; GFX8-NEXT: s_sext_i32_i16 s4, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s6, s4, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s6, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s4, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: s_sub_i32 s3, s4, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_max_i16_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i16_e32 v0, s3, v0
; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_sub_u16_e32 v1, s0, v1
; GFX8-NEXT: v_sub_u16_sdwa v0, v2, v0 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v1, v0
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_v2i16_sv:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_v2i16_sv:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
}
define amdgpu_ps float @ssubsat_v2i16_vs(<2 x i16> %lhs, <2 x i16> inreg %rhs) {
; GFX6-LABEL: ssubsat_v2i16_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_brev_b32 s2, -2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v0
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s3, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v2
; GFX6-NEXT: v_max_i32_e32 v2, -1, v1
; GFX6-NEXT: s_lshl_b32 s0, s1, 16
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s2, v2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v3, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v3, vcc, s3, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_max_i32_e32 v2, s0, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v2, v2, v3
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: s_mov_b32 s0, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_and_b32_e32 v1, s0, v1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_v2i16_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_movk_i32 s2, 0x7fff
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v2, -1, v0
; GFX8-NEXT: s_movk_i32 s3, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v2, s2, v2
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v3, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v1, 16, v0
; GFX8-NEXT: v_subrev_u16_e32 v3, s3, v3
; GFX8-NEXT: v_max_i16_e32 v2, s0, v2
; GFX8-NEXT: v_min_i16_e32 v2, v2, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v3, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_lshr_b32 s1, s0, 16
; GFX8-NEXT: v_subrev_u16_e32 v3, s2, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v4, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v4, s3, v4
; GFX8-NEXT: v_max_i16_e32 v3, s1, v3
; GFX8-NEXT: v_min_i16_e32 v3, v3, v4
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u16_sdwa v1, v1, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_v2i16_vs:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_v2i16_vs:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, v0, s0 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16> %lhs, <2 x i16> %rhs)
%cast = bitcast <2 x i16> %result to float
ret float %cast
}
; FIXME: v3i16 insert/extract
; define <3 x i16> @v_ssubsat_v3i16(<3 x i16> %lhs, <3 x i16> %rhs) {
; %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
; ret <3 x i16> %result
; }
; define amdgpu_ps <3 x i16> @s_ssubsat_v3i16(<3 x i16> inreg %lhs, <3 x i16> inreg %rhs) {
; %result = call <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16> %lhs, <3 x i16> %rhs)
; ret <3 x i16> %result
; }
define <2 x float> @v_ssubsat_v4i16(<4 x i16> %lhs, <4 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v8, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s4, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v4, v8, v4
; GFX6-NEXT: v_min_i32_e32 v4, v4, v10
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v5
; GFX6-NEXT: v_max_i32_e32 v5, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v5, vcc, s4, v5
; GFX6-NEXT: v_min_i32_e32 v8, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_bfrev_b32_e32 v9, -2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v4, v4, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_max_i32_e32 v5, -1, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v6, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v6, vcc, s5, v6
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
; GFX6-NEXT: v_max_i32_e32 v5, -1, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v11, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v7
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v6, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v11
; GFX6-NEXT: v_max_i32_e32 v4, v5, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v4, v4, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_mov_b32 s4, 0xffff
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v4
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v6, -1, v0
; GFX8-NEXT: s_movk_i32 s5, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v6, s4, v6
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v7, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v4, 16, v0
; GFX8-NEXT: v_subrev_u16_e32 v7, s5, v7
; GFX8-NEXT: v_max_i16_e32 v6, v6, v2
; GFX8-NEXT: v_min_i16_e32 v6, v6, v7
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v7, -1, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v7, s4, v7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v8, -1, v4
; GFX8-NEXT: v_subrev_u16_e32 v8, s5, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_max_i16_sdwa v2, v7, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v7, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_min_i16_e32 v2, v2, v8
; GFX8-NEXT: v_subrev_u16_e32 v7, s4, v7
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v8, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v5, 16, v1
; GFX8-NEXT: v_subrev_u16_e32 v8, s5, v8
; GFX8-NEXT: v_max_i16_e32 v7, v7, v3
; GFX8-NEXT: v_min_i16_e32 v7, v7, v8
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v8, -1, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v8, s4, v8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v9, -1, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v9, s5, v9
; GFX8-NEXT: v_max_i16_sdwa v3, v8, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_min_i16_e32 v3, v3, v9
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v6
; GFX8-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
; GFX8-NEXT: v_sub_u16_e32 v1, v1, v7
; GFX8-NEXT: v_sub_u16_sdwa v2, v5, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v1, v1, v2
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v4i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v2 clamp
; GFX9-NEXT: v_pk_sub_i16 v1, v1, v3 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v4i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v2 clamp
; GFX10-NEXT: v_pk_sub_i16 v1, v1, v3 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x float>
ret <2 x float> %cast
}
define amdgpu_ps <2 x i32> @s_ssubsat_v4i16(<4 x i16> inreg %lhs, <4 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v4i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s8, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s10, s0, -1
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s9, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s11, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s11, s11, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s10, s4
; GFX6-NEXT: s_min_i32 s4, s4, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s4, s5, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s5, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s5, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s4, s10
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s5, s2, -1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s4, s6, 16
; GFX6-NEXT: s_sub_i32 s5, s5, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s6, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s5, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s4, s4, s6
; GFX6-NEXT: s_max_i32 s5, s3, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s4, s7, 16
; GFX6-NEXT: s_sub_i32 s5, s5, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s6, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s6, s6, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s4, s5, s4
; GFX6-NEXT: s_min_i32 s4, s4, s6
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_mov_b32 s4, 0xffff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s1, s1, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
; GFX6-NEXT: s_and_b32 s0, s0, s4
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s4
; GFX6-NEXT: s_and_b32 s2, s3, s4
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v4i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s10, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s11, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s8, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s12, s10, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s12, s12, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s6, s2, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s9, 0x8000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s10, s10, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_sext_i32_i16 s2, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s10, s10, s9
; GFX8-NEXT: s_max_i32 s2, s12, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s2, s2
; GFX8-NEXT: s_sext_i32_i16 s10, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s4, s0, 16
; GFX8-NEXT: s_min_i32 s2, s2, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s2
; GFX8-NEXT: s_sext_i32_i16 s2, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s10, s2, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s10, s10, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s2, s2, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s10, s10
; GFX8-NEXT: s_sext_i32_i16 s6, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s9
; GFX8-NEXT: s_max_i32 s6, s10, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s2, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s2, s6, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s4, s2
; GFX8-NEXT: s_sext_i32_i16 s4, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s6, s4, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s7, s3, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s4, s4, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s3, s6, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s4, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s5, s1, 16
; GFX8-NEXT: s_min_i32 s3, s3, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s4, s3, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s7
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s9
; GFX8-NEXT: s_max_i32 s4, s4, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s4, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_sub_i32 s3, s5, s3
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s2, s2, 16
; GFX8-NEXT: s_or_b32 s0, s0, s2
; GFX8-NEXT: s_bfe_u32 s2, s3, 0x100000
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s2, s2, 16
; GFX8-NEXT: s_or_b32 s1, s1, s2
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v4i16:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v4i16:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, s0, s2 clamp
; GFX10-NEXT: v_pk_sub_i16 v1, s1, s3 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16> %lhs, <4 x i16> %rhs)
%cast = bitcast <4 x i16> %result to <2 x i32>
ret <2 x i32> %cast
}
; FIXME
; define <5 x i16> @v_ssubsat_v5i16(<5 x i16> %lhs, <5 x i16> %rhs) {
; %result = call <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)
; ret <5 x i16> %result
; }
; define amdgpu_ps <5 x i16> @s_ssubsat_v5i16(<5 x i16> inreg %lhs, <5 x i16> inreg %rhs) {
; %result = call <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16> %lhs, <5 x i16> %rhs)
; ret <5 x i16> %result
; }
define <3 x float> @v_ssubsat_v6i16(<6 x i16> %lhs, <6 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v6i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v12, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, s4, v12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v14, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v14, vcc, s5, v14
; GFX6-NEXT: v_max_i32_e32 v6, v12, v6
; GFX6-NEXT: v_min_i32_e32 v6, v6, v14
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v7
; GFX6-NEXT: v_max_i32_e32 v7, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v7, vcc, s4, v7
; GFX6-NEXT: v_min_i32_e32 v12, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v12, vcc, s5, v12
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_bfrev_b32_e32 v13, -2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v6, v6, v12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_max_i32_e32 v7, -1, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v8
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v8, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v8, vcc, s5, v8
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
; GFX6-NEXT: v_max_i32_e32 v7, -1, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v15, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v9
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v8, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v15
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
; GFX6-NEXT: v_max_i32_e32 v7, -1, v4
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v10
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v8, -1, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v15
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
; GFX6-NEXT: v_max_i32_e32 v7, -1, v5
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v11
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v8, -1, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v8, v15
; GFX6-NEXT: v_max_i32_e32 v6, v7, v6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_mov_b32 s4, 0xffff
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_min_i32_e32 v6, v6, v8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v6i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v9, -1, v0
; GFX8-NEXT: s_movk_i32 s5, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v9, s4, v9
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v11, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v6, 16, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v11, s5, v11
; GFX8-NEXT: v_max_i16_e32 v9, v9, v3
; GFX8-NEXT: v_min_i16_e32 v9, v9, v11
; GFX8-NEXT: v_max_i16_e32 v11, -1, v6
; GFX8-NEXT: v_subrev_u16_e32 v11, s4, v11
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v13, -1, v6
; GFX8-NEXT: v_subrev_u16_e32 v13, s5, v13
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_sdwa v3, v11, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_max_i16_e32 v11, -1, v1
; GFX8-NEXT: v_min_i16_e32 v3, v3, v13
; GFX8-NEXT: v_subrev_u16_e32 v11, s4, v11
; GFX8-NEXT: v_min_i16_e32 v13, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v7, 16, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v13, s5, v13
; GFX8-NEXT: v_max_i16_e32 v11, v11, v4
; GFX8-NEXT: v_min_i16_e32 v11, v11, v13
; GFX8-NEXT: v_max_i16_e32 v13, -1, v7
; GFX8-NEXT: v_subrev_u16_e32 v13, s4, v13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v14, -1, v7
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_mov_b32_e32 v10, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v14, s5, v14
; GFX8-NEXT: v_max_i16_sdwa v4, v13, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v13, -1, v2
; GFX8-NEXT: v_mov_b32_e32 v12, 0xffff8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v4, v4, v14
; GFX8-NEXT: v_sub_u16_e32 v13, v13, v10
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v14, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v2
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v14, v14, v12
; GFX8-NEXT: v_max_i16_e32 v13, v13, v5
; GFX8-NEXT: v_min_i16_e32 v13, v13, v14
; GFX8-NEXT: v_max_i16_e32 v14, -1, v8
; GFX8-NEXT: v_sub_u16_e32 v10, v14, v10
; GFX8-NEXT: v_min_i16_e32 v14, -1, v8
; GFX8-NEXT: v_sub_u16_e32 v12, v14, v12
; GFX8-NEXT: v_max_i16_sdwa v5, v10, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_sdwa v3, v6, v3 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v5, v5, v12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_or_b32_e32 v0, v0, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v1, v1, v11
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_sdwa v3, v7, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v2, v2, v13
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_sdwa v3, v8, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v2, v2, v3
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v6i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v3 clamp
; GFX9-NEXT: v_pk_sub_i16 v1, v1, v4 clamp
; GFX9-NEXT: v_pk_sub_i16 v2, v2, v5 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v6i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v3 clamp
; GFX10-NEXT: v_pk_sub_i16 v1, v1, v4 clamp
; GFX10-NEXT: v_pk_sub_i16 v2, v2, v5 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x float>
ret <3 x float> %cast
}
define amdgpu_ps <3 x i32> @s_ssubsat_v6i16(<6 x i16> inreg %lhs, <6 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v6i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s12, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s14, s0, -1
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s13, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s14, s14, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s15, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s15, s15, s13
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s14, s6
; GFX6-NEXT: s_min_i32 s6, s6, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s6, s7, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s7, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s7, s7, s12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s14, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s14, s14, s13
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s7, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s6, s6, s14
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s7, s2, -1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s6, s8, 16
; GFX6-NEXT: s_sub_i32 s7, s7, s12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s8, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s8, s8, s13
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s7, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_max_i32 s7, s3, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s6, s9, 16
; GFX6-NEXT: s_sub_i32 s7, s7, s12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s8, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s8, s8, s13
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s7, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_max_i32 s7, s4, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s6, s10, 16
; GFX6-NEXT: s_sub_i32 s7, s7, s12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s8, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s8, s8, s13
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s7, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_max_i32 s7, s5, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s6, s11, 16
; GFX6-NEXT: s_sub_i32 s7, s7, s12
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s8, s5, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s8, s8, s13
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s6, s7, s6
; GFX6-NEXT: s_min_i32 s6, s6, s8
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_mov_b32 s6, 0xffff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s1, s1, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s0, s0, s6
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s6
; GFX6-NEXT: s_and_b32 s2, s3, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_and_b32 s3, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s6
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v6i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s14, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s15, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s12, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s16, s14, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s16, s16, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s9, s3, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s13, 0x8000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s14, s14, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s16, s16
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s14, s14, s13
; GFX8-NEXT: s_max_i32 s3, s16, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s3, s3
; GFX8-NEXT: s_sext_i32_i16 s14, s14
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s6, s0, 16
; GFX8-NEXT: s_min_i32 s3, s3, s14
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s3
; GFX8-NEXT: s_sext_i32_i16 s3, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s14, s3, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s14, s14, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s3, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s14, s14
; GFX8-NEXT: s_sext_i32_i16 s9, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s13
; GFX8-NEXT: s_max_i32 s9, s14, s9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s3, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s3, s9, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s6, s3
; GFX8-NEXT: s_sext_i32_i16 s6, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s9, s6, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s9, s9, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s10, s4, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s6, s6, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s4, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s4, s9, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s6, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s7, s1, 16
; GFX8-NEXT: s_min_i32 s4, s4, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s7
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s6, s4, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s4, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s9, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s13
; GFX8-NEXT: s_max_i32 s6, s6, s9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s4, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s6, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s4, s7, s4
; GFX8-NEXT: s_max_i32 s7, s6, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s7, s7, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s11, s5, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s6, s6, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_sext_i32_i16 s5, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s5, s7, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s6, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s8, s2, 16
; GFX8-NEXT: s_min_i32 s5, s5, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s5
; GFX8-NEXT: s_sext_i32_i16 s5, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s6, s5, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s5, s15
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s7, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s13
; GFX8-NEXT: s_max_i32 s6, s6, s7
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s3, s3, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s6, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_or_b32 s0, s0, s3
; GFX8-NEXT: s_bfe_u32 s3, s4, 0x100000
; GFX8-NEXT: s_sub_i32 s5, s8, s5
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s3, s3, 16
; GFX8-NEXT: s_or_b32 s1, s1, s3
; GFX8-NEXT: s_bfe_u32 s3, s5, 0x100000
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_lshl_b32 s3, s3, 16
; GFX8-NEXT: s_or_b32 s2, s2, s3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v6i16:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp
; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v6i16:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, s0, s3 clamp
; GFX10-NEXT: v_pk_sub_i16 v1, s1, s4 clamp
; GFX10-NEXT: v_pk_sub_i16 v2, s2, s5 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16> %lhs, <6 x i16> %rhs)
%cast = bitcast <6 x i16> %result to <3 x i32>
ret <3 x i32> %cast
}
define <4 x float> @v_ssubsat_v8i16(<8 x i16> %lhs, <8 x i16> %rhs) {
; GFX6-LABEL: v_ssubsat_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_lshlrev_b32_e32 v0, 16, v0
; GFX6-NEXT: s_brev_b32 s4, -2
; GFX6-NEXT: v_max_i32_e32 v16, -1, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v8
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s5, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, s4, v16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_min_i32_e32 v18, -1, v0
; GFX6-NEXT: v_subrev_i32_e32 v18, vcc, s5, v18
; GFX6-NEXT: v_max_i32_e32 v8, v16, v8
; GFX6-NEXT: v_min_i32_e32 v8, v8, v18
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
; GFX6-NEXT: v_sub_i32_e32 v0, vcc, v0, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v9
; GFX6-NEXT: v_max_i32_e32 v9, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v9, vcc, s4, v9
; GFX6-NEXT: v_min_i32_e32 v16, -1, v1
; GFX6-NEXT: v_subrev_i32_e32 v16, vcc, s5, v16
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_bfrev_b32_e32 v17, -2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v8, v8, v16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_max_i32_e32 v9, -1, v2
; GFX6-NEXT: v_sub_i32_e32 v1, vcc, v1, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v10
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_subrev_i32_e32 v10, vcc, s5, v10
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v19, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v11
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v4
; GFX6-NEXT: v_sub_i32_e32 v3, vcc, v3, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v12
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v5, 16, v5
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v5
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v4, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v13
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v6, 16, v6
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v6
; GFX6-NEXT: v_sub_i32_e32 v5, vcc, v5, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v14
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
; GFX6-NEXT: v_lshlrev_b32_e32 v7, 16, v7
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
; GFX6-NEXT: v_max_i32_e32 v9, -1, v7
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 16, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_sub_i32_e32 v6, vcc, v6, v8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v8, 16, v15
; GFX6-NEXT: v_sub_i32_e32 v9, vcc, v9, v17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v10, -1, v7
; GFX6-NEXT: s_mov_b32 s4, 0xffff
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 16, v0
; GFX6-NEXT: v_sub_i32_e32 v10, vcc, v10, v19
; GFX6-NEXT: v_max_i32_e32 v8, v9, v8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_and_b32_e32 v1, s4, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 16, v2
; GFX6-NEXT: v_ashrrev_i32_e32 v3, 16, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_min_i32_e32 v8, v8, v10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_and_b32_e32 v0, s4, v0
; GFX6-NEXT: v_lshlrev_b32_e32 v1, 16, v1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 16, v5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v7, vcc, v7, v8
; GFX6-NEXT: v_or_b32_e32 v0, v0, v1
; GFX6-NEXT: v_and_b32_e32 v1, s4, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v3
; GFX6-NEXT: v_ashrrev_i32_e32 v4, 16, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v7, 16, v7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_lshlrev_b32_e32 v2, 16, v2
; GFX6-NEXT: v_and_b32_e32 v3, s4, v5
; GFX6-NEXT: v_ashrrev_i32_e32 v6, 16, v6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_or_b32_e32 v1, v1, v2
; GFX6-NEXT: v_and_b32_e32 v2, s4, v4
; GFX6-NEXT: v_lshlrev_b32_e32 v3, 16, v3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_and_b32_e32 v4, s4, v7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_or_b32_e32 v2, v2, v3
; GFX6-NEXT: v_and_b32_e32 v3, s4, v6
; GFX6-NEXT: v_lshlrev_b32_e32 v4, 16, v4
; GFX6-NEXT: v_or_b32_e32 v3, v3, v4
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: s_movk_i32 s4, 0x7fff
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v12, -1, v0
; GFX8-NEXT: s_movk_i32 s5, 0x8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v12, s4, v12
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v14, -1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v8, 16, v0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v14, s5, v14
; GFX8-NEXT: v_max_i16_e32 v12, v12, v4
; GFX8-NEXT: v_min_i16_e32 v12, v12, v14
; GFX8-NEXT: v_max_i16_e32 v14, -1, v8
; GFX8-NEXT: v_subrev_u16_e32 v14, s4, v14
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v16, -1, v8
; GFX8-NEXT: v_subrev_u16_e32 v16, s5, v16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_sdwa v4, v14, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_max_i16_e32 v14, -1, v1
; GFX8-NEXT: v_min_i16_e32 v4, v4, v16
; GFX8-NEXT: v_subrev_u16_e32 v14, s4, v14
; GFX8-NEXT: v_min_i16_e32 v16, -1, v1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v9, 16, v1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v16, s5, v16
; GFX8-NEXT: v_max_i16_e32 v14, v14, v5
; GFX8-NEXT: v_min_i16_e32 v14, v14, v16
; GFX8-NEXT: v_max_i16_e32 v16, -1, v9
; GFX8-NEXT: v_subrev_u16_e32 v16, s4, v16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v17, -1, v9
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_mov_b32_e32 v13, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_subrev_u16_e32 v17, s5, v17
; GFX8-NEXT: v_max_i16_sdwa v5, v16, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_e32 v16, -1, v2
; GFX8-NEXT: v_mov_b32_e32 v15, 0xffff8000
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v5, v5, v17
; GFX8-NEXT: v_sub_u16_e32 v16, v16, v13
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v17, -1, v2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v10, 16, v2
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v17, v17, v15
; GFX8-NEXT: v_max_i16_e32 v16, v16, v6
; GFX8-NEXT: v_min_i16_e32 v16, v16, v17
; GFX8-NEXT: v_max_i16_e32 v17, -1, v10
; GFX8-NEXT: v_sub_u16_e32 v17, v17, v13
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_min_i16_e32 v18, -1, v10
; GFX8-NEXT: v_sub_u16_e32 v18, v18, v15
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_max_i16_sdwa v6, v17, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
; GFX8-NEXT: v_max_i16_e32 v17, -1, v3
; GFX8-NEXT: v_min_i16_e32 v6, v6, v18
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_sub_u16_e32 v17, v17, v13
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v18, -1, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_lshrrev_b32_e32 v11, 16, v3
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v18, v18, v15
; GFX8-NEXT: v_max_i16_e32 v17, v17, v7
; GFX8-NEXT: v_min_i16_e32 v17, v17, v18
; GFX8-NEXT: v_max_i16_e32 v18, -1, v11
; GFX8-NEXT: v_sub_u16_e32 v13, v18, v13
; GFX8-NEXT: v_min_i16_e32 v18, -1, v11
; GFX8-NEXT: v_sub_u16_e32 v0, v0, v12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_sdwa v4, v8, v4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v15, v18, v15
; GFX8-NEXT: v_max_i16_sdwa v7, v13, v7 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v1, v1, v14
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_sdwa v4, v9, v5 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_min_i16_e32 v7, v7, v15
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_or_b32_e32 v1, v1, v4
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v2, v2, v16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_sdwa v4, v10, v6 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v2, v2, v4
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: v_sub_u16_e32 v3, v3, v17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u16_sdwa v4, v11, v7 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
; GFX8-NEXT: v_or_b32_e32 v3, v3, v4
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v8i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_pk_sub_i16 v0, v0, v4 clamp
; GFX9-NEXT: v_pk_sub_i16 v1, v1, v5 clamp
; GFX9-NEXT: v_pk_sub_i16 v2, v2, v6 clamp
; GFX9-NEXT: v_pk_sub_i16 v3, v3, v7 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v8i16:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, v0, v4 clamp
; GFX10-NEXT: v_pk_sub_i16 v1, v1, v5 clamp
; GFX10-NEXT: v_pk_sub_i16 v2, v2, v6 clamp
; GFX10-NEXT: v_pk_sub_i16 v3, v3, v7 clamp
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x float>
ret <4 x float> %cast
}
define amdgpu_ps <4 x i32> @s_ssubsat_v8i16(<8 x i16> inreg %lhs, <8 x i16> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v8i16:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_lshl_b32 s0, s0, 16
; GFX6-NEXT: s_brev_b32 s16, -2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s18, s0, -1
; GFX6-NEXT: s_lshl_b32 s8, s8, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX6-NEXT: s_brev_b32 s17, 1
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s18, s18, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s19, s0, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s19, s19, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s18, s8
; GFX6-NEXT: s_min_i32 s8, s8, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_sub_i32 s0, s0, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s8, s9, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s9, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s18, s1, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s18, s18, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s9, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s8, s8, s18
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_max_i32 s9, s2, -1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_sub_i32 s1, s1, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s8, s10, 16
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s2, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s9, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s3, -1
; GFX6-NEXT: s_sub_i32 s2, s2, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s8, s11, 16
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s3, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s9, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s4, -1
; GFX6-NEXT: s_sub_i32 s3, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s8, s12, 16
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s4, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s9, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s5, s5, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s5, -1
; GFX6-NEXT: s_sub_i32 s4, s4, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s8, s13, 16
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s5, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s9, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s6, s6, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s6, -1
; GFX6-NEXT: s_sub_i32 s5, s5, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s8, s14, 16
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s6, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s9, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s7, s7, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_max_i32 s9, s7, -1
; GFX6-NEXT: s_sub_i32 s6, s6, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_lshl_b32 s8, s15, 16
; GFX6-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_min_i32 s10, s7, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_i32 s10, s10, s17
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_max_i32 s8, s9, s8
; GFX6-NEXT: s_min_i32 s8, s8, s10
; GFX6-NEXT: s_ashr_i32 s1, s1, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_sub_i32 s7, s7, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_mov_b32 s8, 0xffff
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s0, s0, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s1, s1, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s2, s2, 16
; GFX6-NEXT: s_ashr_i32 s3, s3, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_and_b32 s0, s0, s8
; GFX6-NEXT: s_lshl_b32 s1, s1, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_ashr_i32 s5, s5, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_or_b32 s0, s0, s1
; GFX6-NEXT: s_and_b32 s1, s2, s8
; GFX6-NEXT: s_and_b32 s2, s3, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX6-NEXT: s_ashr_i32 s4, s4, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_ashr_i32 s7, s7, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_lshl_b32 s2, s2, 16
; GFX6-NEXT: s_and_b32 s3, s5, s8
; GFX6-NEXT: s_ashr_i32 s6, s6, 16
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_or_b32 s1, s1, s2
; GFX6-NEXT: s_and_b32 s2, s4, s8
; GFX6-NEXT: s_lshl_b32 s3, s3, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_and_b32 s4, s7, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_or_b32 s2, s2, s3
; GFX6-NEXT: s_and_b32 s3, s6, s8
; GFX6-NEXT: s_lshl_b32 s4, s4, 16
; GFX6-NEXT: s_or_b32 s3, s3, s4
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v8i16:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sext_i32_i16 s18, s0
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_sext_i32_i16 s19, -1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_movk_i32 s16, 0x7fff
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s20, s18, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s20, s20, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s12, s4, 16
AMDGPU/GlobalISel: Sign extend integer constants This matches the DAG behavior and fixes immediate folding
2020-07-26 02:37:29 +08:00
; GFX8-NEXT: s_movk_i32 s17, 0x8000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s18, s18, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s20, s20
; GFX8-NEXT: s_sext_i32_i16 s4, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s18, s18, s17
; GFX8-NEXT: s_max_i32 s4, s20, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s4, s4
; GFX8-NEXT: s_sext_i32_i16 s18, s18
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s8, s0, 16
; GFX8-NEXT: s_min_i32 s4, s4, s18
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s0, s0, s4
; GFX8-NEXT: s_sext_i32_i16 s4, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s18, s4, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s18, s18, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s4, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s18, s18
; GFX8-NEXT: s_sext_i32_i16 s12, s12
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s4, s4, s17
; GFX8-NEXT: s_max_i32 s12, s18, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_sext_i32_i16 s4, s4
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s4, s12, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s4, s8, s4
; GFX8-NEXT: s_sext_i32_i16 s8, s1
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s12, s8, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s12, s12, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s13, s5, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s8, s8, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s12, s12
; GFX8-NEXT: s_sext_i32_i16 s5, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s5, s12, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s5, s5
; GFX8-NEXT: s_sext_i32_i16 s8, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s9, s1, 16
; GFX8-NEXT: s_min_i32 s5, s5, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s1, s1, s5
; GFX8-NEXT: s_sext_i32_i16 s5, s9
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s8, s5, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s5, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s12, s13
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s5, s5, s17
; GFX8-NEXT: s_max_i32 s8, s8, s12
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s5, s5
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s5, s8, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s2
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s5, s9, s5
; GFX8-NEXT: s_max_i32 s9, s8, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s14, s6, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s8, s8, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s6, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s6, s9, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s6, s6
; GFX8-NEXT: s_sext_i32_i16 s8, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s10, s2, 16
; GFX8-NEXT: s_min_i32 s6, s6, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s2, s2, s6
; GFX8-NEXT: s_sext_i32_i16 s6, s10
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s8, s6, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s6, s6, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s9, s14
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s6, s6, s17
; GFX8-NEXT: s_max_i32 s8, s8, s9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s6, s6
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s6, s8, s6
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s3
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s9, s8, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s9, s9, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s15, s7, 16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_min_i32 s8, s8, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s9, s9
; GFX8-NEXT: s_sext_i32_i16 s7, s7
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s17
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_max_i32 s7, s9, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s7, s7
; GFX8-NEXT: s_sext_i32_i16 s8, s8
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_lshr_b32 s11, s3, 16
; GFX8-NEXT: s_min_i32 s7, s7, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s3, s3, s7
; GFX8-NEXT: s_sext_i32_i16 s7, s11
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_max_i32 s8, s7, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_i32 s8, s8, s16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_bfe_u32 s4, s4, 0x100000
; GFX8-NEXT: s_min_i32 s7, s7, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s9, s15
; GFX8-NEXT: s_bfe_u32 s0, s0, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s7, s7, s17
; GFX8-NEXT: s_max_i32 s8, s8, s9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_or_b32 s0, s0, s4
; GFX8-NEXT: s_bfe_u32 s4, s5, 0x100000
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_sub_i32 s6, s10, s6
; GFX8-NEXT: s_sext_i32_i16 s8, s8
; GFX8-NEXT: s_sext_i32_i16 s7, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_bfe_u32 s1, s1, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
[AMDGPU][GlobalISel] Use scalar min/max instructions SALU min/max s32 instructions exist so use them. This means that regbankselect can handle min/max much like add/sub/mul/shifts. Differential Revision: https://reviews.llvm.org/D96047
2021-02-05 00:08:39 +08:00
; GFX8-NEXT: s_min_i32 s7, s8, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_or_b32 s1, s1, s4
; GFX8-NEXT: s_bfe_u32 s4, s6, 0x100000
; GFX8-NEXT: s_sub_i32 s7, s11, s7
; GFX8-NEXT: s_bfe_u32 s2, s2, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
; GFX8-NEXT: s_or_b32 s2, s2, s4
; GFX8-NEXT: s_bfe_u32 s4, s7, 0x100000
; GFX8-NEXT: s_bfe_u32 s3, s3, 0x100000
; GFX8-NEXT: s_lshl_b32 s4, s4, 16
; GFX8-NEXT: s_or_b32 s3, s3, s4
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v8i16:
; GFX9: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s5
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
; GFX9-NEXT: v_pk_sub_i16 v0, s0, v0 clamp
; GFX9-NEXT: v_pk_sub_i16 v1, s1, v1 clamp
; GFX9-NEXT: v_pk_sub_i16 v2, s2, v2 clamp
; GFX9-NEXT: v_pk_sub_i16 v3, s3, v3 clamp
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v8i16:
; GFX10: ; %bb.0:
AMDGPU/GlobalISel: Use clamp modifier for [us]addsat/[us]subsat We also have never handled this for SelectionDAG, which needs additional work.
2020-07-13 02:16:36 +08:00
; GFX10-NEXT: v_pk_sub_i16 v0, s0, s4 clamp
; GFX10-NEXT: v_pk_sub_i16 v1, s1, s5 clamp
; GFX10-NEXT: v_pk_sub_i16 v2, s2, s6 clamp
; GFX10-NEXT: v_pk_sub_i16 v3, s3, s7 clamp
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16> %lhs, <8 x i16> %rhs)
%cast = bitcast <8 x i16> %result to <4 x i32>
ret <4 x i32> %cast
}
; FIXME: i48 broken because i48 add broken
; define i48 @v_ssubsat_i48(i48 %lhs, i48 %rhs) {
; %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)
; ret i48 %result
; }
; define amdgpu_ps i48 @s_ssubsat_i48(i48 inreg %lhs, i48 inreg %rhs) {
; %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)
; ret i48 %result
; }
; define amdgpu_ps <2 x float> @ssubsat_i48_sv(i48 inreg %lhs, i48 %rhs) {
; %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)
; %ext.result = zext i48 %result to i64
; %cast = bitcast i64 %ext.result to <2 x float>
; ret <2 x float> %cast
; }
; define amdgpu_ps <2 x float> @ssubsat_i48_vs(i48 %lhs, i48 inreg %rhs) {
; %result = call i48 @llvm.ssub.sat.i48(i48 %lhs, i48 %rhs)
; %ext.result = zext i48 %result to i64
; %cast = bitcast i64 %ext.result to <2 x float>
; ret <2 x float> %cast
; }
define i64 @v_ssubsat_i64(i64 %lhs, i64 %rhs) {
; GFX6-LABEL: v_ssubsat_i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v0, v2
; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
; GFX6-NEXT: v_add_i32_e64 v2, s[6:7], 0, v0
; GFX6-NEXT: v_addc_u32_e64 v1, s[6:7], v0, v1, s[6:7]
; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v0, v2
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v3, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: v_add_u32_e64 v2, s[6:7], 0, v0
; GFX8-NEXT: v_addc_u32_e64 v1, s[6:7], v0, v1, s[6:7]
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v0, v2
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v3, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[2:3]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v5
; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
; GFX9-NEXT: v_add_co_u32_e64 v2, s[6:7], 0, v0
; GFX9-NEXT: v_addc_co_u32_e64 v1, s[6:7], v0, v1, s[6:7]
; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, v2
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, v1, v3, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_ashrrev_i32_e32 v6, 31, v5
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[4:5], v[0:1]
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_add_co_u32 v0, s5, v6, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s5, 0x80000000, v6, s5
; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s4
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v5, v1, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
define amdgpu_ps i64 @s_ssubsat_i64(i64 inreg %lhs, i64 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s4, s0, s2
; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: s_and_b32 s5, s5, 1
; GFX6-NEXT: s_cmp_lg_u32 s5, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_subb_u32 s5, s1, s3
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
; GFX6-NEXT: s_ashr_i32 s2, s5, 31
; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX6-NEXT: s_add_u32 s0, s2, 0
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
; GFX6-NEXT: s_and_b32 s1, s1, 1
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
; GFX6-NEXT: s_addc_u32 s1, s2, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v0, s4
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s4, s0, s2
; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: s_and_b32 s5, s5, 1
; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_subb_u32 s5, s1, s3
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
; GFX8-NEXT: s_ashr_i32 s2, s5, 31
; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX8-NEXT: s_add_u32 s0, s2, 0
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_addc_u32 s1, s2, 0x80000000
; GFX8-NEXT: v_mov_b32_e32 v0, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s4, s0, s2
; GFX9-NEXT: s_cselect_b32 s5, 1, 0
; GFX9-NEXT: s_and_b32 s5, s5, 1
; GFX9-NEXT: s_cmp_lg_u32 s5, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_subb_u32 s5, s1, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[4:5], v[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
; GFX9-NEXT: s_ashr_i32 s2, s5, 31
; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX9-NEXT: s_add_u32 s0, s2, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_addc_u32 s1, s2, 0x80000000
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v2, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s4, s0, s2
; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: v_mov_b32_e32 v0, s4
; GFX10-NEXT: s_and_b32 s5, s5, 1
; GFX10-NEXT: s_cmp_lg_u32 s5, 0
; GFX10-NEXT: s_subb_u32 s5, s1, s3
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[4:5], s[0:1]
; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[2:3], 0
; GFX10-NEXT: s_ashr_i32 s2, s5, 31
; GFX10-NEXT: v_mov_b32_e32 v1, s5
; GFX10-NEXT: s_xor_b32 s3, s1, s0
; GFX10-NEXT: s_add_u32 s0, s2, 0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s3
; GFX10-NEXT: s_and_b32 s1, s1, 1
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
; GFX10-NEXT: s_addc_u32 s1, s2, 0x80000000
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s3
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
ret i64 %result
}
define amdgpu_ps <2 x float> @ssubsat_i64_sv(i64 inreg %lhs, i64 %rhs) {
; GFX6-LABEL: ssubsat_i64_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_sub_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v3, v1, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[2:3]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[0:1], 0, v[0:1]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
; GFX6-NEXT: v_add_i32_e64 v4, s[2:3], 0, v0
; GFX6-NEXT: v_addc_u32_e64 v1, s[2:3], v0, v1, s[2:3]
; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i64_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_sub_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v3, v1, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[2:3]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[0:1], 0, v[0:1]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: v_add_u32_e64 v4, s[2:3], 0, v0
; GFX8-NEXT: v_addc_u32_e64 v1, s[2:3], v0, v1, s[2:3]
; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i64_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_sub_co_u32_e32 v2, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v1, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[0:1], v[2:3]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[0:1], 0, v[0:1]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
; GFX9-NEXT: v_add_co_u32_e64 v4, s[2:3], 0, v0
; GFX9-NEXT: v_addc_co_u32_e64 v1, s[2:3], v0, v1, s[2:3]
; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i64_sv:
; GFX10: ; %bb.0:
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_sub_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[0:1]
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[0:1], v[2:3]
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_add_co_u32 v0, s1, v4, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s1, 0x80000000, v4, s1
; GFX10-NEXT: s_xor_b32 vcc_lo, vcc_lo, s0
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
}
define amdgpu_ps <2 x float> @ssubsat_i64_vs(i64 %lhs, i64 inreg %rhs) {
; GFX6-LABEL: ssubsat_i64_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: v_subrev_i32_e32 v2, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], s[0:1], 0
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX6-NEXT: v_bfrev_b32_e32 v1, 1
; GFX6-NEXT: v_add_i32_e64 v4, s[0:1], 0, v0
; GFX6-NEXT: v_addc_u32_e64 v1, s[0:1], v0, v1, s[0:1]
; GFX6-NEXT: s_xor_b64 vcc, s[2:3], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i64_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: v_subrev_u32_e32 v2, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v3, vcc, v1, v3, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], s[0:1], 0
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX8-NEXT: v_bfrev_b32_e32 v1, 1
; GFX8-NEXT: v_add_u32_e64 v4, s[0:1], 0, v0
; GFX8-NEXT: v_addc_u32_e64 v1, s[0:1], v0, v1, s[0:1]
; GFX8-NEXT: s_xor_b64 vcc, s[2:3], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i64_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v2, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v3, vcc, v1, v3, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[2:3], v[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[0:1], 0
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v3
; GFX9-NEXT: v_bfrev_b32_e32 v1, 1
; GFX9-NEXT: v_add_co_u32_e64 v4, s[0:1], 0, v0
; GFX9-NEXT: v_addc_co_u32_e64 v1, s[0:1], v0, v1, s[0:1]
; GFX9-NEXT: s_xor_b64 vcc, s[2:3], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v0, v2, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i64_vs:
; GFX10: ; %bb.0:
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_sub_co_u32 v2, vcc_lo, v0, s0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v3, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[0:1], 0
; GFX10-NEXT: v_ashrrev_i32_e32 v4, 31, v3
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[2:3], v[0:1]
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_add_co_u32 v0, s0, v4, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_add_co_ci_u32_e64 v1, s0, 0x80000000, v4, s0
; GFX10-NEXT: s_xor_b32 vcc_lo, s1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT: ; return to shader part epilog
%result = call i64 @llvm.ssub.sat.i64(i64 %lhs, i64 %rhs)
%cast = bitcast i64 %result to <2 x float>
ret <2 x float> %cast
}
define <2 x i64> @v_ssubsat_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v0, v4
; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v10, 1
; GFX6-NEXT: v_add_i32_e64 v1, s[6:7], 0, v0
; GFX6-NEXT: v_addc_u32_e64 v4, s[6:7], v0, v10, s[6:7]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v2, v6
; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX6-NEXT: v_add_i32_e64 v3, s[6:7], 0, v2
; GFX6-NEXT: v_addc_u32_e64 v6, s[6:7], v2, v10, s[6:7]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v2i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v0, v4
; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX8-NEXT: v_bfrev_b32_e32 v10, 1
; GFX8-NEXT: v_add_u32_e64 v1, s[6:7], 0, v0
; GFX8-NEXT: v_addc_u32_e64 v4, s[6:7], v0, v10, s[6:7]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v2, v6
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX8-NEXT: v_add_u32_e64 v3, s[6:7], 0, v2
; GFX8-NEXT: v_addc_u32_e64 v6, s[6:7], v2, v10, s[6:7]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v0, v4
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v1, v5, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX9-NEXT: v_bfrev_b32_e32 v10, 1
; GFX9-NEXT: v_add_co_u32_e64 v1, s[6:7], 0, v0
; GFX9-NEXT: v_addc_co_u32_e64 v4, s[6:7], v0, v10, s[6:7]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v2, v6
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v7, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX9-NEXT: v_add_co_u32_e64 v3, s[6:7], 0, v2
; GFX9-NEXT: v_addc_co_u32_e64 v6, s[6:7], v2, v10, s[6:7]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v0, v4
; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v1, v5, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v10, vcc_lo, v2, v6
; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v3, v7, vcc_lo
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v9
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[0:1]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[4:5]
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v11
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e64 s6, 0, v[6:7]
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_add_co_u32 v1, s5, v12, 0
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[10:11], v[2:3]
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_add_co_u32 v2, s7, v0, 0
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine Add a combiner helper that replaces G_UNMERGE of big constants into direct use of smaller constants. Differential Revision: https://reviews.llvm.org/D87166
2020-09-05 05:27:42 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v11, v3, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i64:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s8, s0, s4
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_and_b32 s9, s9, 1
; GFX6-NEXT: s_cmp_lg_u32 s9, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_subb_u32 s9, s1, s5
; GFX6-NEXT: v_mov_b32_e32 v1, s1
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_ashr_i32 s4, s9, 31
; GFX6-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX6-NEXT: s_add_u32 s0, s4, 0
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
; GFX6-NEXT: s_and_b32 s1, s1, 1
; GFX6-NEXT: s_brev_b32 s5, 1
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
; GFX6-NEXT: s_addc_u32 s1, s4, s5
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: s_sub_u32 s0, s2, s6
; GFX6-NEXT: v_mov_b32_e32 v2, s1
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_and_b32 s1, s1, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_mov_b32_e32 v0, s2
; GFX6-NEXT: v_mov_b32_e32 v3, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_subb_u32 s1, s3, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 0
; GFX6-NEXT: s_ashr_i32 s4, s1, 31
; GFX6-NEXT: s_xor_b64 vcc, s[2:3], vcc
; GFX6-NEXT: v_mov_b32_e32 v0, s0
; GFX6-NEXT: s_add_u32 s0, s4, 0
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
; GFX6-NEXT: s_addc_u32 s3, s4, s5
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v3, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_mov_b32_e32 v5, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX6-NEXT: v_readfirstlane_b32 s0, v4
; GFX6-NEXT: v_readfirstlane_b32 s1, v2
; GFX6-NEXT: v_readfirstlane_b32 s2, v0
; GFX6-NEXT: v_readfirstlane_b32 s3, v1
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v2i64:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s8, s0, s4
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: s_and_b32 s9, s9, 1
; GFX8-NEXT: s_cmp_lg_u32 s9, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_subb_u32 s9, s1, s5
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_ashr_i32 s4, s9, 31
; GFX8-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX8-NEXT: s_add_u32 s0, s4, 0
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_brev_b32 s5, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_addc_u32 s1, s4, s5
; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: s_sub_u32 s0, s2, s6
; GFX8-NEXT: v_mov_b32_e32 v2, s1
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: v_mov_b32_e32 v0, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_and_b32 s1, s1, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v0, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_subb_u32 s1, s3, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 0
; GFX8-NEXT: s_ashr_i32 s4, s1, 31
; GFX8-NEXT: s_xor_b64 vcc, s[2:3], vcc
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: s_add_u32 s0, s4, 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
; GFX8-NEXT: s_addc_u32 s3, s4, s5
; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_mov_b32_e32 v3, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_mov_b32_e32 v5, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v4
; GFX8-NEXT: v_readfirstlane_b32 s1, v2
; GFX8-NEXT: v_readfirstlane_b32 s2, v0
; GFX8-NEXT: v_readfirstlane_b32 s3, v1
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v2i64:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s8, s0, s4
; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: s_and_b32 s9, s9, 1
; GFX9-NEXT: s_cmp_lg_u32 s9, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_subb_u32 s9, s1, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s1
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[8:9], v[0:1]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[4:5], 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_ashr_i32 s4, s9, 31
; GFX9-NEXT: s_xor_b64 vcc, s[0:1], vcc
; GFX9-NEXT: s_add_u32 s0, s4, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_brev_b32 s5, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_addc_u32 s1, s4, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: s_sub_u32 s0, s2, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s1
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: v_mov_b32_e32 v0, s8
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_and_b32 s1, s1, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v4, v0, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_subb_u32 s1, s3, s7
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[0:1], v[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[2:3], s[6:7], 0
; GFX9-NEXT: s_ashr_i32 s4, s1, 31
; GFX9-NEXT: s_xor_b64 vcc, s[2:3], vcc
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: s_add_u32 s0, s4, 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_addc_u32 s3, s4, s5
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v3, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_mov_b32_e32 v5, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v4
; GFX9-NEXT: v_readfirstlane_b32 s1, v2
; GFX9-NEXT: v_readfirstlane_b32 s2, v0
; GFX9-NEXT: v_readfirstlane_b32 s3, v1
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i64:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s8, s0, s4
; GFX10-NEXT: s_cselect_b32 s9, 1, 0
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, s[4:5], 0
; GFX10-NEXT: s_and_b32 s9, s9, 1
; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: s_cmp_lg_u32 s9, 0
; GFX10-NEXT: s_brev_b32 s10, 1
; GFX10-NEXT: s_subb_u32 s9, s1, s5
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[8:9], s[0:1]
; GFX10-NEXT: s_ashr_i32 s1, s9, 31
; GFX10-NEXT: v_mov_b32_e32 v1, s9
; GFX10-NEXT: s_xor_b32 s8, s4, s0
; GFX10-NEXT: s_add_u32 s0, s1, 0
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s0, s8
; GFX10-NEXT: s_and_b32 s4, s4, 1
; GFX10-NEXT: s_cmp_lg_u32 s4, 0
; GFX10-NEXT: s_addc_u32 s1, s1, s10
; GFX10-NEXT: s_sub_u32 s4, s2, s6
; GFX10-NEXT: s_cselect_b32 s5, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s1, s8
; GFX10-NEXT: s_and_b32 s5, s5, 1
; GFX10-NEXT: v_mov_b32_e32 v2, s4
; GFX10-NEXT: s_cmp_lg_u32 s5, 0
; GFX10-NEXT: s_subb_u32 s5, s3, s7
; GFX10-NEXT: v_cmp_lt_i64_e64 s2, s[4:5], s[2:3]
; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[6:7], 0
; GFX10-NEXT: s_ashr_i32 s1, s5, 31
; GFX10-NEXT: v_mov_b32_e32 v3, s5
; GFX10-NEXT: s_xor_b32 s2, s3, s2
; GFX10-NEXT: s_add_u32 s0, s1, 0
; GFX10-NEXT: s_cselect_b32 s3, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2
; GFX10-NEXT: s_and_b32 s3, s3, 1
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: s_cmp_lg_u32 s3, 0
; GFX10-NEXT: s_addc_u32 s1, s1, s10
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result
}
define amdgpu_ps i128 @s_ssubsat_i128(i128 inreg %lhs, i128 inreg %rhs) {
; GFX6-LABEL: s_ssubsat_i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s8, s0, s4
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
; GFX6-NEXT: s_and_b32 s9, s9, 1
; GFX6-NEXT: s_cmp_lg_u32 s9, 0
; GFX6-NEXT: s_subb_u32 s9, s1, s5
; GFX6-NEXT: s_cselect_b32 s10, 1, 0
; GFX6-NEXT: s_and_b32 s10, s10, 1
; GFX6-NEXT: s_cmp_lg_u32 s10, 0
; GFX6-NEXT: s_subb_u32 s10, s2, s6
; GFX6-NEXT: s_cselect_b32 s11, 1, 0
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: s_and_b32 s11, s11, 1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: s_cmp_lg_u32 s11, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_subb_u32 s11, s3, s7
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[10:11], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_ashr_i32 s3, s11, 31
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_add_u32 s0, s3, 0
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
; GFX6-NEXT: s_and_b32 s1, s1, 1
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
; GFX6-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[6:7], 0
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: s_addc_u32 s2, s3, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_cselect_b32 s4, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: s_and_b32 s4, s4, 1
; GFX6-NEXT: s_cmp_lg_u32 s4, 0
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: s_addc_u32 s3, s3, 0x80000000
; GFX6-NEXT: v_mov_b32_e32 v1, s0
; GFX6-NEXT: v_mov_b32_e32 v2, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_mov_b32_e32 v3, s8
; GFX6-NEXT: v_mov_b32_e32 v4, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_mov_b32_e32 v2, s2
; GFX6-NEXT: v_mov_b32_e32 v3, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_mov_b32_e32 v4, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_mov_b32_e32 v5, s11
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX6-NEXT: v_readfirstlane_b32 s0, v0
; GFX6-NEXT: v_readfirstlane_b32 s1, v1
; GFX6-NEXT: v_readfirstlane_b32 s2, v2
; GFX6-NEXT: v_readfirstlane_b32 s3, v3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s8, s0, s4
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: s_and_b32 s9, s9, 1
; GFX8-NEXT: s_cmp_lg_u32 s9, 0
; GFX8-NEXT: s_subb_u32 s9, s1, s5
; GFX8-NEXT: s_cselect_b32 s10, 1, 0
; GFX8-NEXT: s_and_b32 s10, s10, 1
; GFX8-NEXT: s_cmp_lg_u32 s10, 0
; GFX8-NEXT: s_subb_u32 s10, s2, s6
; GFX8-NEXT: s_cselect_b32 s11, 1, 0
; GFX8-NEXT: s_and_b32 s11, s11, 1
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: s_cmp_lg_u32 s11, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_subb_u32 s11, s3, s7
; GFX8-NEXT: v_mov_b32_e32 v0, s2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
; GFX8-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: s_ashr_i32 s3, s11, 31
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: s_add_u32 s0, s3, 0
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
; GFX8-NEXT: s_addc_u32 s2, s3, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_cselect_b32 s4, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: s_and_b32 s4, s4, 1
; GFX8-NEXT: s_cmp_lg_u32 s4, 0
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: s_addc_u32 s3, s3, 0x80000000
; GFX8-NEXT: v_mov_b32_e32 v1, s0
; GFX8-NEXT: v_mov_b32_e32 v2, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v3, s8
; GFX8-NEXT: v_mov_b32_e32 v4, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_mov_b32_e32 v2, s2
; GFX8-NEXT: v_mov_b32_e32 v3, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_mov_b32_e32 v4, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v5, s11
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v0
; GFX8-NEXT: v_readfirstlane_b32 s1, v1
; GFX8-NEXT: v_readfirstlane_b32 s2, v2
; GFX8-NEXT: v_readfirstlane_b32 s3, v3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s8, s0, s4
; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: s_and_b32 s9, s9, 1
; GFX9-NEXT: s_cmp_lg_u32 s9, 0
; GFX9-NEXT: s_subb_u32 s9, s1, s5
; GFX9-NEXT: s_cselect_b32 s10, 1, 0
; GFX9-NEXT: s_and_b32 s10, s10, 1
; GFX9-NEXT: s_cmp_lg_u32 s10, 0
; GFX9-NEXT: s_subb_u32 s10, s2, s6
; GFX9-NEXT: s_cselect_b32 s11, 1, 0
; GFX9-NEXT: s_and_b32 s11, s11, 1
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: s_cmp_lg_u32 s11, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: s_subb_u32 s11, s3, s7
; GFX9-NEXT: v_mov_b32_e32 v0, s2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[8:9], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[10:11], v[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[4:5], 0
; GFX9-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[6:7], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: s_ashr_i32 s3, s11, 31
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: s_add_u32 s0, s3, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_addc_u32 s2, s3, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: s_and_b32 s4, s4, 1
; GFX9-NEXT: s_cmp_lg_u32 s4, 0
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: s_addc_u32 s3, s3, 0x80000000
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: v_mov_b32_e32 v2, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v3, s8
; GFX9-NEXT: v_mov_b32_e32 v4, s9
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v4, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_mov_b32_e32 v4, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v5, s11
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v0
; GFX9-NEXT: v_readfirstlane_b32 s1, v1
; GFX9-NEXT: v_readfirstlane_b32 s2, v2
; GFX9-NEXT: v_readfirstlane_b32 s3, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_sub_u32 s8, s0, s4
; GFX10-NEXT: s_cselect_b32 s9, 1, 0
; GFX10-NEXT: s_and_b32 s9, s9, 1
; GFX10-NEXT: s_cmp_lg_u32 s9, 0
; GFX10-NEXT: s_subb_u32 s9, s1, s5
; GFX10-NEXT: s_cselect_b32 s10, 1, 0
; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[8:9], s[0:1]
; GFX10-NEXT: s_and_b32 s10, s10, 1
; GFX10-NEXT: s_cmp_lg_u32 s10, 0
; GFX10-NEXT: s_subb_u32 s10, s2, s6
; GFX10-NEXT: s_cselect_b32 s11, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: s_and_b32 s11, s11, 1
; GFX10-NEXT: v_mov_b32_e32 v3, s10
; GFX10-NEXT: s_cmp_lg_u32 s11, 0
; GFX10-NEXT: s_subb_u32 s11, s3, s7
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], s[2:3]
; GFX10-NEXT: v_cmp_lt_i64_e64 s1, s[10:11], s[2:3]
; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: v_mov_b32_e32 v4, s11
; GFX10-NEXT: s_and_b32 s0, 1, s0
; GFX10-NEXT: s_cmp_eq_u64 s[6:7], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[4:5], 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_ashr_i32 s3, s11, 31
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[6:7], 0
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_and_b32 s0, 1, s1
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
; GFX10-NEXT: s_add_u32 s0, s3, 0
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_and_b32 s1, s1, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_mov_b32_e32 v2, s9
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432
2021-03-04 21:40:31 +08:00
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_and_b32 s2, s2, 1
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432
2021-03-04 21:40:31 +08:00
; GFX10-NEXT: v_mov_b32_e32 v1, s8
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_addc_u32 s2, s3, 0
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_and_b32 s4, s4, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s4, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_addc_u32 s3, s3, 0x80000000
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v2, v3, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v3, v4, s3, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
; GFX10-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
ret i128 %result
}
define amdgpu_ps <4 x float> @ssubsat_i128_sv(i128 inreg %lhs, i128 %rhs) {
; GFX6-LABEL: ssubsat_i128_sv:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v5, s1
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v5, v1, vcc
; GFX6-NEXT: v_mov_b32_e32 v6, s2
; GFX6-NEXT: v_mov_b32_e32 v7, s3
; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc
; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc
; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
; GFX6-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_xor_b32_e32 v0, v0, v8
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i128_sv:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v5, v1, vcc
; GFX8-NEXT: v_mov_b32_e32 v6, s2
; GFX8-NEXT: v_mov_b32_e32 v7, s3
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v6, v2, vcc
; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v7, v3, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: v_xor_b32_e32 v0, v0, v8
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i128_sv:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v1, vcc
; GFX9-NEXT: v_mov_b32_e32 v6, s2
; GFX9-NEXT: v_mov_b32_e32 v7, s3
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v6, v2, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v3, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, s[0:1], v[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, s[2:3], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[0:1]
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_xor_b32_e32 v0, v0, v8
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v8, vcc
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i128_sv:
; GFX10: ; %bb.0:
[AMDGPU][MC][GFX10][GFX90A] Corrected _e32/_e64 suffices Fixed bugs https://bugs.llvm.org//show_bug.cgi?id=49643, https://bugs.llvm.org//show_bug.cgi?id=49644, https://bugs.llvm.org//show_bug.cgi?id=49645. Differential Revision: https://reviews.llvm.org/D99413
2021-04-01 19:21:00 +08:00
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, s0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_sub_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_gt_u64_e32 vcc_lo, s[0:1], v[4:5]
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_gt_i64_e32 vcc_lo, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[0:1]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[2:3]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[2:3], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[2:3]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX10-NEXT: v_xor_b32_e32 v0, v0, v8
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
}
define amdgpu_ps <4 x float> @ssubsat_i128_vs(i128 %lhs, i128 inreg %rhs) {
; GFX6-LABEL: ssubsat_i128_vs:
; GFX6: ; %bb.0:
; GFX6-NEXT: v_mov_b32_e32 v5, s1
; GFX6-NEXT: v_subrev_i32_e32 v4, vcc, s0, v0
; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v1, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v6, s2
; GFX6-NEXT: v_mov_b32_e32 v7, s3
; GFX6-NEXT: v_subb_u32_e32 v6, vcc, v2, v6, vcc
; GFX6-NEXT: v_subb_u32_e32 v7, vcc, v3, v7, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]
; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 0
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v8, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[2:3], 0
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: ssubsat_i128_vs:
; GFX8: ; %bb.0:
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_subrev_u32_e32 v4, vcc, s0, v0
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v1, v5, vcc
; GFX8-NEXT: v_mov_b32_e32 v6, s2
; GFX8-NEXT: v_mov_b32_e32 v7, s3
; GFX8-NEXT: v_subb_u32_e32 v6, vcc, v2, v6, vcc
; GFX8-NEXT: v_subb_u32_e32 v7, vcc, v3, v7, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]
; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 0
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_bfrev_b32_e32 v8, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s4
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, v1, v8, vcc
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: ssubsat_i128_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: v_mov_b32_e32 v5, s1
; GFX9-NEXT: v_subrev_co_u32_e32 v4, vcc, s0, v0
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v1, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v6, s2
; GFX9-NEXT: v_mov_b32_e32 v7, s3
; GFX9-NEXT: v_subb_co_u32_e32 v6, vcc, v2, v6, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v7, vcc, v3, v7, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[4:5], v[0:1]
; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[0:1], 0
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[6:7], v[2:3]
; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[2:3], 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_bfrev_b32_e32 v8, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s4
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, v1, v8, vcc
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v2, v6, v9, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v3, v7, v8, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: ssubsat_i128_vs:
; GFX10: ; %bb.0:
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_sub_co_u32 v4, vcc_lo, v0, s0
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v5, vcc_lo, s1, v1, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v6, vcc_lo, s2, v2, vcc_lo
; GFX10-NEXT: v_subrev_co_ci_u32_e32 v7, vcc_lo, s3, v3, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[4:5], v[0:1]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_cmp_gt_u64_e64 s0, s[0:1], 0
; GFX10-NEXT: s_cmp_eq_u64 s[2:3], 0
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[6:7], v[2:3]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, s0
; GFX10-NEXT: v_cmp_gt_i64_e64 s0, s[2:3], 0
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[6:7], v[2:3]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, s0
; GFX10-NEXT: s_and_b32 s0, 1, s4
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v7
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v8, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s0, 0, v0
; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, 0x80000000, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v4, v2, s0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v5, v3, s0
; GFX10-NEXT: v_cndmask_b32_e64 v2, v6, v8, s0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v7, v9, s0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: ; return to shader part epilog
%result = call i128 @llvm.ssub.sat.i128(i128 %lhs, i128 %rhs)
%cast = bitcast i128 %result to <4 x float>
ret <4 x float> %cast
}
define <2 x i128> @v_ssubsat_v2i128(<2 x i128> %lhs, <2 x i128> %rhs) {
; GFX6-LABEL: v_ssubsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v16, vcc, v0, v8
; GFX6-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc
; GFX6-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
; GFX6-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_bfrev_b32_e32 v20, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX6-NEXT: v_ashrrev_i32_e32 v1, 31, v19
; GFX6-NEXT: v_add_i32_e32 v2, vcc, 0, v1
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX6-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v1, v20, vcc
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v9, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12
; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX6-NEXT: v_ashrrev_i32_e32 v5, 31, v11
; GFX6-NEXT: v_add_i32_e32 v6, vcc, 0, v5
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
; GFX6-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
; GFX6-NEXT: v_addc_u32_e32 v13, vcc, v5, v20, vcc
; GFX6-NEXT: v_and_b32_e32 v4, 1, v4
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_ssubsat_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v16, vcc, v0, v8
; GFX8-NEXT: v_subb_u32_e32 v17, vcc, v1, v9, vcc
; GFX8-NEXT: v_subb_u32_e32 v18, vcc, v2, v10, vcc
; GFX8-NEXT: v_subb_u32_e32 v19, vcc, v3, v11, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_bfrev_b32_e32 v20, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX8-NEXT: v_ashrrev_i32_e32 v1, 31, v19
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 0, v1
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
; GFX8-NEXT: v_addc_u32_e32 v8, vcc, 0, v1, vcc
; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v1, v20, vcc
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v9, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12
; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX8-NEXT: v_ashrrev_i32_e32 v5, 31, v11
; GFX8-NEXT: v_add_u32_e32 v6, vcc, 0, v5
; GFX8-NEXT: v_addc_u32_e32 v7, vcc, 0, v5, vcc
; GFX8-NEXT: v_addc_u32_e32 v12, vcc, 0, v5, vcc
; GFX8-NEXT: v_addc_u32_e32 v13, vcc, v5, v20, vcc
; GFX8-NEXT: v_and_b32_e32 v4, 1, v4
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_ssubsat_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v16, vcc, v0, v8
; GFX9-NEXT: v_subb_co_u32_e32 v17, vcc, v1, v9, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v18, vcc, v2, v10, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v19, vcc, v3, v11, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[16:17], v[0:1]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_bfrev_b32_e32 v20, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[18:19], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[18:19], v[2:3]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[8:9]
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v19
; GFX9-NEXT: v_add_co_u32_e32 v2, vcc, 0, v1
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v8, vcc, 0, v1, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v1, v20, vcc
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v8, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v9, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX9-NEXT: v_ashrrev_i32_e32 v5, 31, v11
; GFX9-NEXT: v_add_co_u32_e32 v6, vcc, 0, v5
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, 0, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v12, vcc, 0, v5, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v13, vcc, v5, v20, vcc
; GFX9-NEXT: v_and_b32_e32 v4, 1, v4
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v7, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v12, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v13, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_ssubsat_v2i128:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_sub_co_u32 v16, vcc_lo, v0, v8
; GFX10-NEXT: v_sub_co_ci_u32_e32 v17, vcc_lo, v1, v9, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v18, vcc_lo, v2, v10, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v19, vcc_lo, v3, v11, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, v[16:17], v[0:1]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[18:19], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_u64_e32 vcc_lo, 0, v[8:9]
; GFX10-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc_lo
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, 0, v[10:11]
; GFX10-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc_lo
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, v[18:19], v[2:3]
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cmp_eq_u64_e32 vcc_lo, 0, v[10:11]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v8, vcc_lo
; GFX10-NEXT: v_sub_co_u32 v8, vcc_lo, v4, v12
; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v5, v13, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v10, vcc_lo, v6, v14, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e32 v11, vcc_lo, v7, v15, vcc_lo
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[4:5]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v19
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_eq_u64_e64 s5, v[10:11], v[6:7]
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, v[10:11], v[6:7]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_add_co_u32 v2, vcc_lo, v1, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v1, vcc_lo
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, 0, v[12:13]
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX10-NEXT: v_ashrrev_i32_e32 v7, 31, v11
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v12, 0, 1, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[14:15]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v13, 0, 1, s4
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v5, v4, s5
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_eq_u64_e64 s5, 0, v[14:15]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v1, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v6, vcc_lo, 0x80000000, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v1, v17, v3, s4
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v4, v13, v12, s5
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_xor_b32_e32 v4, v4, v0
; GFX10-NEXT: v_cndmask_b32_e64 v0, v16, v2, s4
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v2, v18, v5, s4
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_and_b32_e32 v3, 1, v4
; GFX10-NEXT: v_add_co_u32 v4, vcc_lo, v7, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v5, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v12, vcc_lo, 0, v7, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v3
; GFX10-NEXT: v_add_co_ci_u32_e32 v7, vcc_lo, 0x80000000, v7, vcc_lo
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v3, v19, v6, s4
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v4, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v12, s5
; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v7, s5
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
define amdgpu_ps <2 x i128> @s_ssubsat_v2i128(<2 x i128> inreg %lhs, <2 x i128> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i128:
; GFX6: ; %bb.0:
; GFX6-NEXT: s_sub_u32 s16, s0, s8
; GFX6-NEXT: s_cselect_b32 s17, 1, 0
; GFX6-NEXT: s_and_b32 s17, s17, 1
; GFX6-NEXT: s_cmp_lg_u32 s17, 0
; GFX6-NEXT: s_subb_u32 s17, s1, s9
; GFX6-NEXT: s_cselect_b32 s18, 1, 0
; GFX6-NEXT: s_and_b32 s18, s18, 1
; GFX6-NEXT: s_cmp_lg_u32 s18, 0
; GFX6-NEXT: s_subb_u32 s18, s2, s10
; GFX6-NEXT: s_cselect_b32 s19, 1, 0
; GFX6-NEXT: v_mov_b32_e32 v3, s1
; GFX6-NEXT: s_and_b32 s19, s19, 1
; GFX6-NEXT: v_mov_b32_e32 v2, s0
; GFX6-NEXT: s_cmp_lg_u32 s19, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_subb_u32 s19, s3, s11
; GFX6-NEXT: v_mov_b32_e32 v1, s3
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[18:19], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_ashr_i32 s3, s19, 31
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_add_u32 s0, s3, 0
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
; GFX6-NEXT: s_and_b32 s1, s1, 1
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
; GFX6-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
; GFX6-NEXT: s_addc_u32 s2, s3, 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[10:11], 0
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_and_b32 s9, s9, 1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_brev_b32 s8, 1
; GFX6-NEXT: s_cmp_lg_u32 s9, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_addc_u32 s3, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_sub_u32 s0, s4, s12
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_mov_b32_e32 v2, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_cselect_b32 s1, 1, 0
; GFX6-NEXT: s_and_b32 s1, s1, 1
; GFX6-NEXT: s_cmp_lg_u32 s1, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_subb_u32 s1, s5, s13
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX6-NEXT: v_mov_b32_e32 v0, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_cselect_b32 s2, 1, 0
; GFX6-NEXT: s_and_b32 s2, s2, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_mov_b32_e32 v3, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_mov_b32_e32 v4, s17
; GFX6-NEXT: s_cmp_lg_u32 s2, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s3
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_mov_b32_e32 v2, s18
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_mov_b32_e32 v3, s19
; GFX6-NEXT: s_subb_u32 s2, s6, s14
; GFX6-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_cselect_b32 s3, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_mov_b32_e32 v2, s4
; GFX6-NEXT: s_and_b32 s3, s3, 1
; GFX6-NEXT: v_mov_b32_e32 v3, s5
; GFX6-NEXT: s_cmp_lg_u32 s3, 0
; GFX6-NEXT: v_mov_b32_e32 v0, s6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: s_subb_u32 s3, s7, s15
; GFX6-NEXT: v_mov_b32_e32 v1, s7
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX6-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
; GFX6-NEXT: v_cndmask_b32_e64 v3, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, s[2:3], v[0:1]
; GFX6-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_ashr_i32 s7, s3, 31
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_add_u32 s4, s7, 0
; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: s_and_b32 s5, s5, 1
; GFX6-NEXT: s_cmp_lg_u32 s5, 0
; GFX6-NEXT: s_addc_u32 s5, s7, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: s_cselect_b32 s6, 1, 0
; GFX6-NEXT: s_and_b32 s6, s6, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cmp_eq_u64_e64 vcc, s[14:15], 0
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_cmp_lg_u32 s6, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: s_addc_u32 s6, s7, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: s_cselect_b32 s9, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_xor_b32_e32 v0, v1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_and_b32 s9, s9, 1
; GFX6-NEXT: s_cmp_lg_u32 s9, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_and_b32_e32 v0, 1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX6-NEXT: s_addc_u32 s7, s7, s8
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_mov_b32_e32 v1, s4
; GFX6-NEXT: v_mov_b32_e32 v2, s5
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_mov_b32_e32 v3, s0
; GFX6-NEXT: v_mov_b32_e32 v8, s1
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX6-NEXT: v_mov_b32_e32 v2, s6
; GFX6-NEXT: v_mov_b32_e32 v3, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX6-NEXT: v_mov_b32_e32 v8, s2
; GFX6-NEXT: v_mov_b32_e32 v9, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX6-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; GFX6-NEXT: v_readfirstlane_b32 s0, v5
; GFX6-NEXT: v_readfirstlane_b32 s1, v4
; GFX6-NEXT: v_readfirstlane_b32 s2, v6
; GFX6-NEXT: v_readfirstlane_b32 s3, v7
; GFX6-NEXT: v_readfirstlane_b32 s4, v0
; GFX6-NEXT: v_readfirstlane_b32 s5, v1
; GFX6-NEXT: v_readfirstlane_b32 s6, v2
; GFX6-NEXT: v_readfirstlane_b32 s7, v3
; GFX6-NEXT: ; return to shader part epilog
;
; GFX8-LABEL: s_ssubsat_v2i128:
; GFX8: ; %bb.0:
; GFX8-NEXT: s_sub_u32 s16, s0, s8
; GFX8-NEXT: s_cselect_b32 s17, 1, 0
; GFX8-NEXT: s_and_b32 s17, s17, 1
; GFX8-NEXT: s_cmp_lg_u32 s17, 0
; GFX8-NEXT: s_subb_u32 s17, s1, s9
; GFX8-NEXT: s_cselect_b32 s18, 1, 0
; GFX8-NEXT: s_and_b32 s18, s18, 1
; GFX8-NEXT: s_cmp_lg_u32 s18, 0
; GFX8-NEXT: s_subb_u32 s18, s2, s10
; GFX8-NEXT: s_cselect_b32 s19, 1, 0
; GFX8-NEXT: s_and_b32 s19, s19, 1
; GFX8-NEXT: v_mov_b32_e32 v3, s1
; GFX8-NEXT: s_cmp_lg_u32 s19, 0
; GFX8-NEXT: v_mov_b32_e32 v2, s0
; GFX8-NEXT: s_subb_u32 s19, s3, s11
; GFX8-NEXT: v_mov_b32_e32 v0, s2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v1, s3
; GFX8-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
; GFX8-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX8-NEXT: s_and_b32 s0, 1, s2
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: s_ashr_i32 s3, s19, 31
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX8-NEXT: s_add_u32 s0, s3, 0
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
; GFX8-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
; GFX8-NEXT: s_addc_u32 s2, s3, 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
; GFX8-NEXT: s_and_b32 s9, s9, 1
; GFX8-NEXT: s_brev_b32 s8, 1
; GFX8-NEXT: s_cmp_lg_u32 s9, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: s_addc_u32 s3, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_mov_b32_e32 v1, s0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_sub_u32 s0, s4, s12
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_mov_b32_e32 v2, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_cselect_b32 s1, 1, 0
; GFX8-NEXT: s_and_b32 s1, s1, 1
; GFX8-NEXT: s_cmp_lg_u32 s1, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_subb_u32 s1, s5, s13
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_cselect_b32 s2, 1, 0
; GFX8-NEXT: s_and_b32 s2, s2, 1
; GFX8-NEXT: s_cmp_lg_u32 s2, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_mov_b32_e32 v3, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_mov_b32_e32 v4, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: s_subb_u32 s2, s6, s14
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_mov_b32_e32 v1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v2, s18
; GFX8-NEXT: v_mov_b32_e32 v3, s19
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_cselect_b32 s3, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_and_b32 s3, s3, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v2, s4
; GFX8-NEXT: s_cmp_lg_u32 s3, 0
; GFX8-NEXT: v_mov_b32_e32 v3, s5
; GFX8-NEXT: s_subb_u32 s3, s7, s15
; GFX8-NEXT: v_mov_b32_e32 v0, s6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_mov_b32_e32 v1, s7
; GFX8-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX8-NEXT: s_and_b32 s4, 1, s6
; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
; GFX8-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX8-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX8-NEXT: s_and_b32 s4, 1, s6
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: s_ashr_i32 s7, s3, 31
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_add_u32 s4, s7, 0
; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: s_and_b32 s5, s5, 1
; GFX8-NEXT: s_cmp_lg_u32 s5, 0
; GFX8-NEXT: s_addc_u32 s5, s7, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: s_cselect_b32 s6, 1, 0
; GFX8-NEXT: s_and_b32 s6, s6, 1
; GFX8-NEXT: s_cmp_lg_u32 s6, 0
; GFX8-NEXT: s_addc_u32 s6, s7, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: s_cselect_b32 s9, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_xor_b32_e32 v0, v1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: s_and_b32 s9, s9, 1
; GFX8-NEXT: s_cmp_lg_u32 s9, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_and_b32_e32 v0, 1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX8-NEXT: s_addc_u32 s7, s7, s8
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_mov_b32_e32 v1, s4
; GFX8-NEXT: v_mov_b32_e32 v2, s5
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_mov_b32_e32 v3, s0
; GFX8-NEXT: v_mov_b32_e32 v8, s1
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX8-NEXT: v_mov_b32_e32 v2, s6
; GFX8-NEXT: v_mov_b32_e32 v3, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX8-NEXT: v_mov_b32_e32 v8, s2
; GFX8-NEXT: v_mov_b32_e32 v9, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX8-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; GFX8-NEXT: v_readfirstlane_b32 s0, v5
; GFX8-NEXT: v_readfirstlane_b32 s1, v4
; GFX8-NEXT: v_readfirstlane_b32 s2, v6
; GFX8-NEXT: v_readfirstlane_b32 s3, v7
; GFX8-NEXT: v_readfirstlane_b32 s4, v0
; GFX8-NEXT: v_readfirstlane_b32 s5, v1
; GFX8-NEXT: v_readfirstlane_b32 s6, v2
; GFX8-NEXT: v_readfirstlane_b32 s7, v3
; GFX8-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_ssubsat_v2i128:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_sub_u32 s16, s0, s8
; GFX9-NEXT: s_cselect_b32 s17, 1, 0
; GFX9-NEXT: s_and_b32 s17, s17, 1
; GFX9-NEXT: s_cmp_lg_u32 s17, 0
; GFX9-NEXT: s_subb_u32 s17, s1, s9
; GFX9-NEXT: s_cselect_b32 s18, 1, 0
; GFX9-NEXT: s_and_b32 s18, s18, 1
; GFX9-NEXT: s_cmp_lg_u32 s18, 0
; GFX9-NEXT: s_subb_u32 s18, s2, s10
; GFX9-NEXT: s_cselect_b32 s19, 1, 0
; GFX9-NEXT: s_and_b32 s19, s19, 1
; GFX9-NEXT: v_mov_b32_e32 v3, s1
; GFX9-NEXT: s_cmp_lg_u32 s19, 0
; GFX9-NEXT: v_mov_b32_e32 v2, s0
; GFX9-NEXT: s_subb_u32 s19, s3, s11
; GFX9-NEXT: v_mov_b32_e32 v0, s2
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[16:17], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s3
; GFX9-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[18:19], v[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: v_cmp_gt_u64_e64 s[0:1], s[8:9], 0
; GFX9-NEXT: s_cmp_eq_u64 s[10:11], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[0:1], s[10:11], 0
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[0:1]
; GFX9-NEXT: s_and_b32 s0, 1, s2
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: s_ashr_i32 s3, s19, 31
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s0
; GFX9-NEXT: s_add_u32 s0, s3, 0
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
; GFX9-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
; GFX9-NEXT: s_addc_u32 s2, s3, 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: s_cselect_b32 s9, 1, 0
; GFX9-NEXT: s_and_b32 s9, s9, 1
; GFX9-NEXT: s_brev_b32 s8, 1
; GFX9-NEXT: s_cmp_lg_u32 s9, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: s_addc_u32 s3, s3, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_sub_u32 s0, s4, s12
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_mov_b32_e32 v2, s1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_cselect_b32 s1, 1, 0
; GFX9-NEXT: s_and_b32 s1, s1, 1
; GFX9-NEXT: s_cmp_lg_u32 s1, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_subb_u32 s1, s5, s13
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; GFX9-NEXT: v_mov_b32_e32 v0, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_cselect_b32 s2, 1, 0
; GFX9-NEXT: s_and_b32 s2, s2, 1
; GFX9-NEXT: s_cmp_lg_u32 s2, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_mov_b32_e32 v3, s16
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_mov_b32_e32 v4, s17
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: s_subb_u32 s2, s6, s14
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v5, v3, v1, vcc
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v2, s18
; GFX9-NEXT: v_mov_b32_e32 v3, s19
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_cselect_b32 s3, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v6, v2, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v3, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_and_b32 s3, s3, 1
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: s_cmp_lg_u32 s3, 0
; GFX9-NEXT: v_mov_b32_e32 v3, s5
; GFX9-NEXT: s_subb_u32 s3, s7, s15
; GFX9-NEXT: v_mov_b32_e32 v0, s6
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, s[0:1], v[2:3]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s7
; GFX9-NEXT: s_cmp_eq_u64 s[2:3], s[6:7]
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, s[2:3], v[0:1]
; GFX9-NEXT: s_and_b32 s4, 1, s6
; GFX9-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: v_cmp_gt_u64_e64 s[4:5], s[12:13], 0
; GFX9-NEXT: s_cmp_eq_u64 s[14:15], 0
; GFX9-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], s[14:15], 0
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5]
; GFX9-NEXT: s_and_b32 s4, 1, s6
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: s_ashr_i32 s7, s3, 31
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_add_u32 s4, s7, 0
; GFX9-NEXT: s_cselect_b32 s5, 1, 0
; GFX9-NEXT: s_and_b32 s5, s5, 1
; GFX9-NEXT: s_cmp_lg_u32 s5, 0
; GFX9-NEXT: s_addc_u32 s5, s7, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: s_cselect_b32 s6, 1, 0
; GFX9-NEXT: s_and_b32 s6, s6, 1
; GFX9-NEXT: s_cmp_lg_u32 s6, 0
; GFX9-NEXT: s_addc_u32 s6, s7, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: s_cselect_b32 s9, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_xor_b32_e32 v0, v1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: s_and_b32 s9, s9, 1
; GFX9-NEXT: s_cmp_lg_u32 s9, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_and_b32_e32 v0, 1, v0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX9-NEXT: s_addc_u32 s7, s7, s8
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_mov_b32_e32 v1, s4
; GFX9-NEXT: v_mov_b32_e32 v2, s5
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_mov_b32_e32 v3, s0
; GFX9-NEXT: v_mov_b32_e32 v8, s1
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v8, v2, vcc
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX9-NEXT: v_mov_b32_e32 v2, s6
; GFX9-NEXT: v_mov_b32_e32 v3, s7
[AMDGPU] Switch PostRA sched to MachineSched Use GCNHazardRecognizer in postra sched. Updated tests for the new schedules. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D109536 Change-Id: Ia86ba2ae168f12fb34b4d8efdab491f84d936cde
2021-09-09 01:22:15 +08:00
; GFX9-NEXT: v_mov_b32_e32 v8, s2
; GFX9-NEXT: v_mov_b32_e32 v9, s3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX9-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc
; GFX9-NEXT: v_readfirstlane_b32 s0, v5
; GFX9-NEXT: v_readfirstlane_b32 s1, v4
; GFX9-NEXT: v_readfirstlane_b32 s2, v6
; GFX9-NEXT: v_readfirstlane_b32 s3, v7
; GFX9-NEXT: v_readfirstlane_b32 s4, v0
; GFX9-NEXT: v_readfirstlane_b32 s5, v1
; GFX9-NEXT: v_readfirstlane_b32 s6, v2
; GFX9-NEXT: v_readfirstlane_b32 s7, v3
; GFX9-NEXT: ; return to shader part epilog
;
; GFX10-LABEL: s_ssubsat_v2i128:
; GFX10: ; %bb.0:
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432
2021-03-04 21:40:31 +08:00
; GFX10-NEXT: s_sub_u32 s16, s0, s8
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cselect_b32 s17, 1, 0
; GFX10-NEXT: s_and_b32 s17, s17, 1
; GFX10-NEXT: s_cmp_lg_u32 s17, 0
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432
2021-03-04 21:40:31 +08:00
; GFX10-NEXT: s_subb_u32 s17, s1, s9
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cselect_b32 s18, 1, 0
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: v_cmp_lt_u64_e64 s0, s[16:17], s[0:1]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_and_b32 s18, s18, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_gt_u64_e64 s1, s[8:9], 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s18, 0
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: s_subb_u32 s18, s2, s10
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cselect_b32 s19, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
; GFX10-NEXT: s_and_b32 s19, s19, 1
; GFX10-NEXT: s_cmp_lg_u32 s19, 0
[AMDGPU] Experiments show that the GCNRegBankReassign pass significantly impacts the compilation time and there is no case for which we see any improvement in performance. This patch removes this pass and its associated test cases from the tree. Differential Revision: https://reviews.llvm.org/D101313 Change-Id: I0599169a7609c19a887f8d847a71e664030cc141
2021-04-27 03:48:12 +08:00
; GFX10-NEXT: s_subb_u32 s19, s3, s11
; GFX10-NEXT: v_cmp_lt_i64_e64 s0, s[18:19], s[2:3]
; GFX10-NEXT: s_cmp_eq_u64 s[18:19], s[2:3]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_mov_b32_e32 v3, s19
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cselect_b32 s20, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
; GFX10-NEXT: s_and_b32 s0, 1, s20
; GFX10-NEXT: s_cmp_eq_u64 s[10:11], 0
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432
2021-03-04 21:40:31 +08:00
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_cselect_b32 s0, 1, 0
; GFX10-NEXT: s_ashr_i32 s3, s19, 31
; GFX10-NEXT: s_and_b32 s0, 1, s0
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432
2021-03-04 21:40:31 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc_lo
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v1, 0, 1, s1
; GFX10-NEXT: v_cmp_gt_i64_e64 s1, s[10:11], 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_add_u32 s0, s3, 0
; GFX10-NEXT: s_brev_b32 s10, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v2, 0, 1, s1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_cselect_b32 s1, 1, 0
; GFX10-NEXT: s_and_b32 s1, s1, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s1, 0
Reland AMDGPU/GlobalISel: Combine zext(trunc x) to x after RegBankSelect Recommit bf5a5826504754788a8f1e3fec7a7dc95cda5782. Depends on 4c8fb7ddd6fa49258e0e9427e7345fb56ba522d4 which was reverted. RegBankSelect creates zext and trunc when it selects banks for uniform i1. Add zext_trunc_fold from generic combiner to post RegBankSelect combiner. Differential Revision: https://reviews.llvm.org/D95432
2021-03-04 21:40:31 +08:00
; GFX10-NEXT: v_mov_b32_e32 v2, s17
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_addc_u32 s1, s3, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_xor_b32_e32 v0, v1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_and_b32 s2, s2, 1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_mov_b32_e32 v1, s16
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s2, 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_and_b32_e32 v0, 1, v0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_addc_u32 s2, s3, 0
[GlobalISel] Simplify G_ICMP to true/false when the result is known Use existing KnownBits helpers from KnownBits.h to simplify G_ICMPs. E.g. x == x -> true x != x -> false load(x) > 1 -> true (when the load is known to be greater than 1) And so on. Differential Revision: https://reviews.llvm.org/D102542
2021-05-15 07:53:52 +08:00
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
; GFX10-NEXT: s_and_b32 s8, s8, 1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v0
[GlobalISel] Simplify G_ICMP to true/false when the result is known Use existing KnownBits helpers from KnownBits.h to simplify G_ICMPs. E.g. x == x -> true x != x -> false load(x) > 1 -> true (when the load is known to be greater than 1) And so on. Differential Revision: https://reviews.llvm.org/D102542
2021-05-15 07:53:52 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s8, 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_addc_u32 s3, s3, s10
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo
; GFX10-NEXT: s_sub_u32 s0, s4, s12
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
; GFX10-NEXT: v_cndmask_b32_e64 v1, v2, s1, vcc_lo
; GFX10-NEXT: s_and_b32 s8, s8, 1
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: v_mov_b32_e32 v2, s18
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s8, 0
; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s3, vcc_lo
; GFX10-NEXT: s_subb_u32 s1, s5, s13
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cselect_b32 s8, 1, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, s[0:1], s[4:5]
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_and_b32 s8, s8, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s8, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_gt_u64_e64 s3, s[12:13], 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_subb_u32 s8, s6, s14
; GFX10-NEXT: s_cselect_b32 s9, 1, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v4, 0, 1, s4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_and_b32 s9, s9, 1
; GFX10-NEXT: v_mov_b32_e32 v7, s8
; GFX10-NEXT: s_cmp_lg_u32 s9, 0
; GFX10-NEXT: s_subb_u32 s9, s7, s15
; GFX10-NEXT: s_cmp_eq_u64 s[8:9], s[6:7]
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, s[8:9], s[6:7]
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_mov_b32_e32 v8, s9
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_and_b32 s2, 1, s2
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cmp_eq_u64 s[14:15], 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s2
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s4
; GFX10-NEXT: s_cselect_b32 s2, 1, 0
; GFX10-NEXT: s_ashr_i32 s5, s9, 31
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v5, 0, 1, s3
; GFX10-NEXT: v_cmp_gt_i64_e64 s3, s[14:15], 0
; GFX10-NEXT: v_cndmask_b32_e64 v6, 0, 1, s3
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_and_b32 s3, 1, s2
; GFX10-NEXT: s_add_u32 s2, s5, 0
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s3
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_and_b32 s4, s4, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s4, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_mov_b32_e32 v6, s1
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_addc_u32 s3, s5, 0
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: v_xor_b32_e32 v4, v5, v4
; GFX10-NEXT: s_and_b32 s4, s4, 1
; GFX10-NEXT: v_mov_b32_e32 v5, s0
; GFX10-NEXT: s_cmp_lg_u32 s4, 0
; GFX10-NEXT: v_readfirstlane_b32 s0, v0
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: v_and_b32_e32 v4, 1, v4
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: s_addc_u32 s4, s5, 0
Revert "[GlobalISel] Simplify G_ICMP to true/false when the result is known" This reverts commit 892497c806306a4b7185ead16d60b0ebcca0a304. Breaks tests, see comments on https://reviews.llvm.org/D102542
2021-05-19 21:02:27 +08:00
; GFX10-NEXT: s_cselect_b32 s6, 1, 0
; GFX10-NEXT: s_and_b32 s6, s6, 1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v4
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: s_cmp_lg_u32 s6, 0
[GlobalISel] Add a constant folding combine. Use it AArch64 post-legal combiner. These don't always get folded because when the instructions are created the constants are obscured by artifacts. Differential Revision: https://reviews.llvm.org/D106776
2021-07-26 05:42:38 +08:00
; GFX10-NEXT: s_addc_u32 s1, s5, s10
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v4, v5, s2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v5, v6, s3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v6, v7, s4, vcc_lo
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_cndmask_b32_e64 v7, v8, s1, vcc_lo
; GFX10-NEXT: v_readfirstlane_b32 s1, v1
Recommit "[GlobalISel] Simplify G_ICMP to true/false when the result is known" Add missing REQUIRES line to prelegalizer-combiner-icmp-to-true-false-known-bits.
2021-05-20 00:18:52 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s2, v2
; GFX10-NEXT: v_readfirstlane_b32 s3, v3
[GlobalISel][AMDGPU] Legalize saturating add/subtract Add support in LegalizerHelper for lowering G_SADDSAT etc. either using add/subtract-with-overflow or using max/min instructions. Enable this lowering for AMDGPU so it can be tested. The legalization rules are still approximate and skips out on using the clamp bit to treat these as legal, which has never been used before. This also doesn't yet try to deal with expanding SALU cases.
2020-07-13 02:18:45 +08:00
; GFX10-NEXT: v_readfirstlane_b32 s4, v4
; GFX10-NEXT: v_readfirstlane_b32 s5, v5
; GFX10-NEXT: v_readfirstlane_b32 s6, v6
; GFX10-NEXT: v_readfirstlane_b32 s7, v7
; GFX10-NEXT: ; return to shader part epilog
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result
}
declare i7 @llvm.ssub.sat.i7(i7, i7) #0
declare i8 @llvm.ssub.sat.i8(i8, i8) #0
declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>) #0
declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>) #0
declare i16 @llvm.ssub.sat.i16(i16, i16) #0
declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>) #0
declare <3 x i16> @llvm.ssub.sat.v3i16(<3 x i16>, <3 x i16>) #0
declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>) #0
declare <5 x i16> @llvm.ssub.sat.v5i16(<5 x i16>, <5 x i16>) #0
declare <6 x i16> @llvm.ssub.sat.v6i16(<6 x i16>, <6 x i16>) #0
declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>) #0
declare i24 @llvm.ssub.sat.i24(i24, i24) #0
declare i32 @llvm.ssub.sat.i32(i32, i32) #0
declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>) #0
declare <3 x i32> @llvm.ssub.sat.v3i32(<3 x i32>, <3 x i32>) #0
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>) #0
declare <5 x i32> @llvm.ssub.sat.v5i32(<5 x i32>, <5 x i32>) #0
declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>) #0
declare i48 @llvm.ssub.sat.i48(i48, i48) #0
declare i64 @llvm.ssub.sat.i64(i64, i64) #0
declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>) #0
declare i128 @llvm.ssub.sat.i128(i128, i128) #0
declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>) #0
attributes #0 = { nounwind readnone speculatable willreturn }