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llvm-project/llvm/lib/Target/Mips/MipsMSAInstrInfo.td

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[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
//===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=//
//
// The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes Mips MSA ASE instructions.
//
//===----------------------------------------------------------------------===//
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>;
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
2013-09-24 18:46:19 +08:00
def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
SDTCisInt<1>,
SDTCisSameAs<1, 2>,
SDTCisVT<3, OtherVT>]>;
def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>,
SDTCisFP<1>,
SDTCisSameAs<1, 2>,
SDTCisVT<3, OtherVT>]>;
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>,
SDTCisInt<1>, SDTCisVec<1>,
SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>;
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) llvm-svn: 191302
2013-09-24 22:20:00 +08:00
def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>;
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics) llvm-svn: 191304
2013-09-24 22:36:12 +08:00
def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>,
SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>;
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>,
SDTCisVT<2, i32>, SDTCisSameAs<0, 3>,
SDTCisVT<4, i32>]>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>;
def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>;
def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>;
def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>;
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) llvm-svn: 191291
2013-09-24 20:18:31 +08:00
def MipsVSMax : SDNode<"MipsISD::VSMAX", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def MipsVSMin : SDNode<"MipsISD::VSMIN", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def MipsVUMax : SDNode<"MipsISD::VUMAX", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
def MipsVUMin : SDNode<"MipsISD::VUMIN", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) llvm-svn: 191195
2013-09-23 21:22:24 +08:00
def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp,
[SDNPCommutative, SDNPAssociative]>;
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) llvm-svn: 191302
2013-09-24 22:20:00 +08:00
def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>;
[mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics) llvm-svn: 191304
2013-09-24 22:36:12 +08:00
def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>;
def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>;
def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>;
def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>;
[mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics) llvm-svn: 191306
2013-09-24 22:53:25 +08:00
def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>;
def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>;
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>;
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
2013-09-24 18:46:19 +08:00
def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>;
def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT",
SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT",
SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>;
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>;
def immZExt6Ptr : ImmLeaf<iPTR, [{return isUInt<6>(Imm);}]>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
// Operands
[mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. llvm-svn: 195004
2013-11-18 20:32:49 +08:00
// The immediate of an LSA instruction needs special handling
// as the encoded value should be subtracted by one.
def uimm2LSAAsmOperand : AsmOperandClass {
let Name = "LSAImm";
[mips] Rename MipsAsmParser functions to conform to the LLVM Coding Standards. No functional changes. Summary: There are still some functions which should be renamed, but they are inherited from the generic MC classes. Reviewers: dsanders Reviewed By: dsanders Differential Revision: http://reviews.llvm.org/D5068 llvm-svn: 217145
2014-09-04 21:23:44 +08:00
let ParserMethod = "parseLSAImm";
[mips][msa] Fix immediate value of LSA instruction as it was being wrongly encoded. The immediate field should be encoded as "imm - 1" as the CPU always adds one to that field. llvm-svn: 195004
2013-11-18 20:32:49 +08:00
let RenderMethod = "addImmOperands";
}
def LSAImm : Operand<i32> {
let PrintMethod = "printUnsignedImm";
let EncoderMethod = "getLSAImmEncoding";
let DecoderMethod = "DecodeLSAImm";
let ParserMatchClass = uimm2LSAAsmOperand;
}
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def uimm4 : Operand<i32> {
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
let PrintMethod = "printUnsignedImm8";
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
}
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
def uimm4_ptr : Operand<iPTR> {
let PrintMethod = "printUnsignedImm8";
}
def uimm6_ptr : Operand<iPTR> {
let PrintMethod = "printUnsignedImm8";
}
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def uimm8 : Operand<i32> {
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
let PrintMethod = "printUnsignedImm8";
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
}
def simm5 : Operand<i32>;
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
def vsplat_uimm1 : Operand<vAny> {
let PrintMethod = "printUnsignedImm8";
}
def vsplat_uimm2 : Operand<vAny> {
let PrintMethod = "printUnsignedImm8";
}
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplat_uimm3 : Operand<vAny> {
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
let PrintMethod = "printUnsignedImm8";
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
}
def vsplat_uimm4 : Operand<vAny> {
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
let PrintMethod = "printUnsignedImm8";
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
}
def vsplat_uimm5 : Operand<vAny> {
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
let PrintMethod = "printUnsignedImm8";
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
}
def vsplat_uimm6 : Operand<vAny> {
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
let PrintMethod = "printUnsignedImm8";
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
}
def vsplat_uimm8 : Operand<vAny> {
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
let PrintMethod = "printUnsignedImm8";
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
}
def vsplat_simm5 : Operand<vAny>;
def vsplat_simm10 : Operand<vAny>;
[mips][msa] Added lsa instruction llvm-svn: 192895
2013-10-17 21:38:20 +08:00
def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
// Pattern fragments
def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i8)>;
def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i16)>;
def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i32)>;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractSExt node:$vec, node:$idx, i64)>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i8)>;
def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i16)>;
def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i32)>;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx),
(MipsVExtractZExt node:$vec, node:$idx, i64)>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx),
(v16i8 (vector_insert node:$vec, node:$val, node:$idx))>;
def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx),
(v8i16 (vector_insert node:$vec, node:$val, node:$idx))>;
def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx),
(v4i32 (vector_insert node:$vec, node:$val, node:$idx))>;
[mips][msa] Add insert.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200543
2014-01-31 21:31:20 +08:00
def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx),
(v2i64 (vector_insert node:$vec, node:$val, node:$idx))>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2),
(v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>;
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
2013-09-24 18:46:19 +08:00
class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> :
PatFrag<(ops node:$lhs, node:$rhs),
(ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>;
// ISD::SETFALSE cannot occur
def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>;
def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>;
def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>;
def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>;
def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>;
def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>;
def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>;
def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>;
def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>;
def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>;
def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>;
def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>;
def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>;
def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>;
def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>;
def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>;
def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>;
def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>;
def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>;
def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>;
def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>;
def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>;
def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>;
def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>;
def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>;
def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>;
def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>;
def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>;
// ISD::SETTRUE cannot occur
// ISD::SETFALSE2 cannot occur
// ISD::SETTRUE2 cannot occur
class vsetcc_type<ValueType ResTy, CondCode CC> :
PatFrag<(ops node:$lhs, node:$rhs),
(ResTy (vsetcc node:$lhs, node:$rhs, CC))>;
def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>;
def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>;
def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>;
def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>;
def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>;
def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>;
def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>;
def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>;
def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>;
def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>;
def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>;
def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>;
def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>;
def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>;
def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>;
def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>;
def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>;
def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>;
def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>;
def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplati8 : PatFrag<(ops node:$e0),
(v16i8 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0))>;
def vsplati16 : PatFrag<(ops node:$e0),
(v8i16 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0,
node:$e0, node:$e0))>;
def vsplati32 : PatFrag<(ops node:$e0),
(v4i32 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0))>;
def vsplati64 : PatFrag<(ops node:$e0),
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
(v2i64 (build_vector node:$e0, node:$e0))>;
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
def vsplatf32 : PatFrag<(ops node:$e0),
(v4f32 (build_vector node:$e0, node:$e0,
node:$e0, node:$e0))>;
def vsplatf64 : PatFrag<(ops node:$e0),
(v2f64 (build_vector node:$e0, node:$e0))>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
2013-10-30 21:07:44 +08:00
def vsplati8_elt : PatFrag<(ops node:$v, node:$i),
(MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>;
def vsplati16_elt : PatFrag<(ops node:$v, node:$i),
(MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>;
def vsplati32_elt : PatFrag<(ops node:$v, node:$i),
(MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>;
def vsplati64_elt : PatFrag<(ops node:$v, node:$i),
(MipsVSHF (vsplati64 node:$i), node:$v, node:$v)>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}],
SDNodeXForm xform = NOOP_SDNodeXForm>
: PatLeaf<frag, pred, xform> {
Operand OpClass = opclass;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
}
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn,
list<SDNode> roots = [],
list<SDNodeProperty> props = []> :
ComplexPattern<ty, numops, fn, roots, props> {
Operand OpClass = opclass;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
}
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1,
"selectVSplatUimm3",
[build_vector, bitconvert]>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1,
"selectVSplatUimm4",
[build_vector, bitconvert]>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1,
"selectVSplatUimm5",
[build_vector, bitconvert]>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1,
"selectVSplatUimm8",
[build_vector, bitconvert]>;
def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1,
"selectVSplatSimm5",
[build_vector, bitconvert]>;
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1,
"selectVSplatUimm3",
[build_vector, bitconvert]>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1,
"selectVSplatUimm4",
[build_vector, bitconvert]>;
def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1,
"selectVSplatUimm5",
[build_vector, bitconvert]>;
def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1,
"selectVSplatSimm5",
[build_vector, bitconvert]>;
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1,
"selectVSplatUimm2",
[build_vector, bitconvert]>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1,
"selectVSplatUimm5",
[build_vector, bitconvert]>;
def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1,
"selectVSplatSimm5",
[build_vector, bitconvert]>;
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1,
"selectVSplatUimm1",
[build_vector, bitconvert]>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1,
"selectVSplatUimm5",
[build_vector, bitconvert]>;
def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1,
"selectVSplatUimm6",
[build_vector, bitconvert]>;
def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1,
"selectVSplatSimm5",
[build_vector, bitconvert]>;
// Any build_vector that is a constant splat with a value that is an exact
// power of 2
def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2",
[build_vector, bitconvert]>;
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
// Any build_vector that is a constant splat with a value that is the bitwise
// inverse of an exact power of 2
def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2",
[build_vector, bitconvert]>;
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
2013-10-30 22:45:14 +08:00
// Any build_vector that is a constant splat with only a consecutive sequence
// of left-most bits set.
def vsplat_maskl_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
"selectVSplatMaskL",
[build_vector, bitconvert]>;
// Any build_vector that is a constant splat with only a consecutive sequence
// of right-most bits set.
def vsplat_maskr_bits : SplatComplexPattern<vsplat_uimm8, vAny, 1,
"selectVSplatMaskR",
[build_vector, bitconvert]>;
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
// Any build_vector that is a constant splat with a value that equals 1
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
// FIXME: These should be a ComplexPattern but we can't use them because the
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
// ISel generator requires the uses to have a name, but providing a name
// causes other errors ("used in pattern but not operand list")
def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{
APInt Imm;
EVT EltTy = N->getValueType(0).getVectorElementType();
[mips] Correct and improve special-case shuffle instructions. Summary: The documentation writes vectors highest-index first whereas LLVM-IR writes them lowest-index first. As a result, instructions defined in terms of left_half() and right_half() had the halves reversed. In addition to correcting them, they have been improved to allow shuffles that use the same operand twice or in reverse order. For example, ilvev used to accept masks of the form: <0, n, 2, n+2, 4, n+4, ...> but now accepts: <0, 0, 2, 2, 4, 4, ...> <n, n, n+2, n+2, n+4, n+4, ...> <0, n, 2, n+2, 4, n+4, ...> <n, 0, n+2, 2, n+4, 4, ...> One further improvement is that splati.[bhwd] is now the preferred instruction for splat-like operations. The other special shuffles are no longer used for splats. This lead to the discovery that <0, 0, ...> would not cause splati.[hwd] to be selected and this has also been fixed. This fixes the enc-3des test from the test-suite on Mips64r6 with MSA. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9660 llvm-svn: 237689
2015-05-19 20:24:52 +08:00
return selectVSplat(N, Imm, EltTy.getSizeInBits()) &&
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
}]>;
def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{
APInt Imm;
SDNode *BV = N->getOperand(0).getNode();
EVT EltTy = N->getValueType(0).getVectorElementType();
[mips] Correct and improve special-case shuffle instructions. Summary: The documentation writes vectors highest-index first whereas LLVM-IR writes them lowest-index first. As a result, instructions defined in terms of left_half() and right_half() had the halves reversed. In addition to correcting them, they have been improved to allow shuffles that use the same operand twice or in reverse order. For example, ilvev used to accept masks of the form: <0, n, 2, n+2, 4, n+4, ...> but now accepts: <0, 0, 2, 2, 4, 4, ...> <n, n, n+2, n+2, n+4, n+4, ...> <0, n, 2, n+2, 4, n+4, ...> <n, 0, n+2, 2, n+4, 4, ...> One further improvement is that splati.[bhwd] is now the preferred instruction for splat-like operations. The other special shuffles are no longer used for splats. This lead to the discovery that <0, 0, ...> would not cause splati.[hwd] to be selected and this has also been fixed. This fixes the enc-3des test from the test-suite on Mips64r6 with MSA. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9660 llvm-svn: 237689
2015-05-19 20:24:52 +08:00
return selectVSplat(BV, Imm, EltTy.getSizeInBits()) &&
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1;
}]>;
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
def vbclr_b : PatFrag<(ops node:$ws, node:$wt),
(and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
immAllOnesV))>;
def vbclr_h : PatFrag<(ops node:$ws, node:$wt),
(and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
immAllOnesV))>;
def vbclr_w : PatFrag<(ops node:$ws, node:$wt),
(and node:$ws, (xor (shl vsplat_imm_eq_1, node:$wt),
immAllOnesV))>;
def vbclr_d : PatFrag<(ops node:$ws, node:$wt),
(and node:$ws, (xor (shl (v2i64 vsplati64_imm_eq_1),
node:$wt),
(bitconvert (v4i32 immAllOnesV))))>;
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
def vbneg_b : PatFrag<(ops node:$ws, node:$wt),
(xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
def vbneg_h : PatFrag<(ops node:$ws, node:$wt),
(xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
def vbneg_w : PatFrag<(ops node:$ws, node:$wt),
(xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
def vbneg_d : PatFrag<(ops node:$ws, node:$wt),
(xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
node:$wt))>;
def vbset_b : PatFrag<(ops node:$ws, node:$wt),
(or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
def vbset_h : PatFrag<(ops node:$ws, node:$wt),
(or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
def vbset_w : PatFrag<(ops node:$ws, node:$wt),
(or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>;
def vbset_d : PatFrag<(ops node:$ws, node:$wt),
(or node:$ws, (shl (v2i64 vsplati64_imm_eq_1),
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
node:$wt))>;
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
[mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics) llvm-svn: 192435
2013-10-11 18:27:32 +08:00
def fms : PatFrag<(ops node:$wd, node:$ws, node:$wt),
(fsub node:$wd, (fmul node:$ws, node:$wt))>;
[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) llvm-svn: 192438
2013-10-11 18:50:42 +08:00
def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt),
(add node:$wd, (mul node:$ws, node:$wt))>;
def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt),
(sub node:$wd, (mul node:$ws, node:$wt))>;
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) llvm-svn: 193239
2013-10-23 18:36:52 +08:00
def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt),
(fmul node:$ws, (fexp2 node:$wt))>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
// Immediates
def immSExt5 : ImmLeaf<i32, [{return isInt<5>(Imm);}]>;
def immSExt10: ImmLeaf<i32, [{return isInt<10>(Imm);}]>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
// Instruction encoding.
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>;
class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>;
class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>;
class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>;
class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>;
class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>;
class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>;
class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>;
class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>;
class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>;
class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>;
class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>;
class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>;
class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>;
class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>;
class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>;
class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>;
class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>;
class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>;
class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>;
class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>;
class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>;
class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>;
class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>;
class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>;
class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>;
class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>;
class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>;
class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>;
class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>;
class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>;
class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>;
class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>;
class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>;
class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>;
class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>;
class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>;
class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>;
class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>;
class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>;
class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>;
class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>;
class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>;
class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>;
class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>;
class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>;
class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>;
class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>;
class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>;
class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>;
class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>;
class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>;
class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>;
class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>;
class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>;
class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>;
class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>;
class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>;
class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>;
class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>;
class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>;
class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>;
class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>;
class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>;
class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>;
class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>;
class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>;
class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>;
class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>;
class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>;
class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>;
class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>;
class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>;
class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>;
class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>;
class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>;
class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>;
class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>;
class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>;
class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>;
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>;
class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>;
class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>;
class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[mips][msa] Update encoding of bnz.v (typo). Note that there's no hardware yet that relies on that encoding. llvm-svn: 195006
2013-11-18 21:09:54 +08:00
class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>;
class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>;
class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>;
class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>;
class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>;
class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>;
class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>;
class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>;
class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>;
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>;
class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>;
class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>;
class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>;
class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>;
class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>;
class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>;
class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>;
class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>;
class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>;
class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>;
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>;
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
2013-08-28 18:26:24 +08:00
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>;
class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>;
class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>;
class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>;
class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>;
class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>;
class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>;
class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>;
class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>;
class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>;
class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>;
class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>;
class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>;
class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>;
class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>;
class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>;
class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>;
class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>;
class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>;
class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>;
class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>;
class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>;
class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>;
class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>;
class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>;
class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>;
class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>;
class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>;
class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>;
class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>;
class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>;
class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>;
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>;
class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>;
class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
class COPY_U_D_ENC : MSA_ELM_COPY_D_FMT<0b0011, 0b011001>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>;
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
2013-08-28 18:26:24 +08:00
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>;
class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>;
class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>;
class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>;
class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>;
class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>;
class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>;
class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>;
class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>;
class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>;
class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>;
class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>;
class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>;
class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>;
class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>;
class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>;
class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>;
class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>;
class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>;
class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>;
class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>;
class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>;
class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>;
class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>;
class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>;
class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>;
class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>;
class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>;
class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>;
class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>;
class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>;
class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>;
class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>;
class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>;
class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>;
class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>;
class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>;
class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>;
class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>;
class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>;
class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>;
class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>;
class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>;
class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>;
class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>;
class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>;
class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>;
class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>;
class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>;
class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>;
class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>;
class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>;
class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>;
class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>;
class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>;
class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>;
class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>;
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
2013-10-01 01:43:04 +08:00
class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>;
class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>;
class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>;
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>;
class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>;
class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>;
class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>;
class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>;
class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>;
class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>;
class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>;
class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>;
class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>;
class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>;
class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>;
class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>;
class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>;
class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>;
class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>;
class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>;
class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>;
class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>;
class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>;
class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>;
class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>;
class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>;
class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>;
class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>;
class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>;
class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>;
class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>;
class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>;
class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>;
class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>;
class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>;
class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>;
class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>;
class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>;
class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>;
class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>;
class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>;
class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>;
class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>;
class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>;
class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>;
class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>;
class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>;
class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>;
class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>;
class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>;
class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>;
[mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq. Define these three instructions in alphabetical order (like the rest of the file). No functional change. llvm-svn: 192880
2013-10-17 18:30:12 +08:00
class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>;
class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>;
class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>;
class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>;
class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>;
class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>;
class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>;
class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>;
class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>;
class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>;
class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>;
class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>;
class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>;
class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>;
class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>;
class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>;
class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>;
class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>;
class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>;
class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>;
class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>;
class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>;
class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>;
class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>;
class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>;
class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>;
class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>;
class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>;
class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>;
class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>;
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
2013-10-14 19:49:30 +08:00
class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>;
class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>;
class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>;
[mips][msa] Add insert.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200543
2014-01-31 21:31:20 +08:00
class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added insve llvm-svn: 188777
2013-08-20 17:22:54 +08:00
class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>;
class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>;
class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>;
class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>;
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>;
class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>;
class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>;
class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Update encoding of LDI instruction. The encoding was updated in MSA r1.07. llvm-svn: 194255
2013-11-08 18:43:11 +08:00
class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>;
class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>;
class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>;
class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>;
[mips][msa] Added load/store intrinsics. llvm-svn: 189476
2013-08-28 20:04:29 +08:00
[mips][msa] Direct Object Emission support for the LSA instruction. llvm-svn: 193240
2013-10-23 21:20:07 +08:00
class LSA_ENC : SPECIAL_LSA_FMT<0b000101>;
[mips][msa] Add DLSA instruction. llvm-svn: 201081
2014-02-10 20:05:17 +08:00
class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>;
[mips][msa] Added lsa instruction llvm-svn: 192895
2013-10-17 21:38:20 +08:00
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>;
class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>;
class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>;
class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>;
class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>;
class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>;
class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>;
class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>;
class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>;
class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>;
class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>;
class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>;
class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>;
class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>;
class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>;
class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>;
class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>;
class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>;
class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>;
class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>;
class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>;
class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>;
class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>;
class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>;
class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>;
class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>;
class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>;
class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>;
class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>;
class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>;
class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>;
class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>;
class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>;
class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>;
class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>;
class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>;
class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>;
class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>;
class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>;
class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>;
class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>;
class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>;
class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>;
class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>;
class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>;
class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>;
class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>;
class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>;
class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>;
class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>;
class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>;
class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>;
class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>;
class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>;
[mips][msa] Added move.v llvm-svn: 189471
2013-08-28 18:44:47 +08:00
class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>;
class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>;
class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>;
class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>;
class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>;
class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>;
[mips][msa] Updates encoding of 3RF instructions to match the latest revision of the MSA spec (1.06). This does not affect any of the existing output. Patch by Matheus Almeida llvm-svn: 191460
2013-09-27 05:18:57 +08:00
class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>;
class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>;
class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>;
class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>;
class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>;
class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>;
class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>;
class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>;
class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>;
class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>;
class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>;
class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>;
class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>;
class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>;
class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>;
class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>;
class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>;
class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>;
class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>;
class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>;
class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>;
class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>;
class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>;
class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>;
class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>;
class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>;
class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>;
class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>;
class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>;
class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>;
class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>;
class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>;
class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>;
class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>;
class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>;
class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>;
class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>;
[mips][msa] Fix definition of SLD instruction. The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
2013-10-21 19:47:56 +08:00
class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>;
class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>;
class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>;
class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>;
class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>;
class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>;
class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>;
class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>;
class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>;
class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>;
class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>;
class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>;
class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>;
class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>;
class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>;
[mips][msa] Direct Object Emission of SPLAT instruction. llvm-svn: 193077
2013-10-21 20:07:26 +08:00
class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>;
class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>;
class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>;
class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>;
class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>;
class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>;
class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>;
class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>;
class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>;
class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>;
class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>;
class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>;
class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>;
class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>;
class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>;
class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>;
class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>;
class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>;
class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>;
class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>;
class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>;
class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>;
class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>;
class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>;
class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>;
class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>;
class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>;
class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>;
class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>;
class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>;
class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>;
class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>;
class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>;
class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>;
class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>;
class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>;
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>;
class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>;
class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>;
class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>;
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>;
class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>;
class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>;
class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>;
class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>;
class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>;
class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>;
class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>;
[mips][msa] Updates encoding of 3R instructions to match the latest revision of the MSA spec (1.06). Internal changes only. Patch by Matheus Almeida llvm-svn: 191414
2013-09-26 08:02:44 +08:00
class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>;
class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>;
class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>;
class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>;
class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>;
class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>;
class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>;
class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>;
class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>;
class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>;
class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>;
class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>;
class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>;
class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>;
class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>;
class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>;
class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>;
class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>;
class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>;
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
// Instruction desc.
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size No functional change llvm-svn: 190134
2013-09-06 19:01:38 +08:00
class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
ComplexPattern Imm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m);
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size No functional change llvm-svn: 190134
2013-09-06 19:01:38 +08:00
class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
ComplexPattern Imm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m);
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size No functional change llvm-svn: 190134
2013-09-06 19:01:38 +08:00
class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
ComplexPattern Imm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m);
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Sorted MSA_BIT_[BHWD]_DESC_BASE into ascending order of element size No functional change llvm-svn: 190134
2013-09-06 19:01:38 +08:00
class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
ComplexPattern Imm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))];
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
InstrItinClass Itinerary = itin;
}
// This class is deprecated and will be removed soon.
class MSA_BIT_B_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm3:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt3:$m))];
InstrItinClass Itinerary = itin;
}
// This class is deprecated and will be removed soon.
class MSA_BIT_H_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm4:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt4:$m))];
InstrItinClass Itinerary = itin;
}
// This class is deprecated and will be removed soon.
class MSA_BIT_W_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm5:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt5:$m))];
InstrItinClass Itinerary = itin;
}
// This class is deprecated and will be removed soon.
class MSA_BIT_D_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
dag InOperandList = (ins ROWS:$ws, uimm6:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, immZExt6:$m))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
2013-10-30 22:45:14 +08:00
class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty,
ComplexPattern Mask, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, vsplat_uimm8:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
2014-03-12 19:54:00 +08:00
// Note that binsxi and vselect treat the condition operand the opposite
// way to each other.
// (vselect cond, if_set, if_clear)
// (BSEL_V cond, if_clear, if_set)
list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws),
ROWS:$wd_in))];
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
2013-10-30 22:45:14 +08:00
InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty,
RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> :
MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskl_bits, ROWD, ROWS, itin>;
class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty,
RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> :
MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, vsplat_maskr_bits, ROWD, ROWS, itin>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
SplatComplexPattern SplatImm,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))];
[mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics) llvm-svn: 191285
2013-09-24 18:28:18 +08:00
InstrItinClass Itinerary = itin;
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
ValueType VecTy, RegisterOperand ROD,
RegisterOperand ROWS,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
dag OutOperandList = (outs ROD:$rd);
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
dag InOperandList = (ins ROWS:$ws, uimm4_ptr:$n);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]");
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), immZExt4Ptr:$n))];
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Correct sld and sldi builtins. Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
2013-12-10 19:37:00 +08:00
class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips][msa] Correct sld and sldi builtins. Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
2013-12-10 19:37:00 +08:00
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, uimm4:$n);
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
[mips][msa] Correct sld and sldi builtins. Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
2013-12-10 19:37:00 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
immZExt4:$n))];
string Constraints = "$wd = $wd_in";
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
2013-09-27 20:17:32 +08:00
class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy,
RegisterClass RCD, RegisterClass RCWS> :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, uimm4_ptr:$n),
[(set RCD:$wd, (OpNode (VecTy RCWS:$ws), immZExt4Ptr:$n))]> {
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
2013-09-27 20:17:32 +08:00
bit usesCustomInserter = 1;
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
SplatComplexPattern SplatImm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm);
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm");
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
SplatComplexPattern SplatImm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))];
[mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics) llvm-svn: 191293
2013-09-24 20:32:47 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) llvm-svn: 191302
2013-09-24 22:20:00 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, uimm8:$u8);
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) llvm-svn: 191302
2013-09-24 22:20:00 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8");
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
list<dag> Pattern = [(set ROWD:$wd, (MipsSHF immZExt8:$u8, ROWS:$ws))];
[mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) llvm-svn: 191302
2013-09-24 22:20:00 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Direct Object Emission support for LDI instructions. llvm-svn: 193081
2013-10-21 20:56:20 +08:00
class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD,
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for LDI instructions. llvm-svn: 193081
2013-10-21 20:56:20 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins vsplat_simm10:$s10);
string AsmString = !strconcat(instr_asm, "\t$wd, $s10");
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
// LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp
list<dag> Pattern = [];
bit hasSideEffects = 0;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for 2R instructions. This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
2013-10-01 01:52:33 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for 2R instructions. This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
2013-10-01 01:52:33 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
[mips][msa] Direct Object Emission for 2R instructions. This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
2013-10-01 01:52:33 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT,
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
2013-10-01 01:43:04 +08:00
SDPatternOperator OpNode, RegisterOperand ROWD,
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
RegisterOperand ROS = ROWD,
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
InstrItinClass itin = NoItinerary> {
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
2013-10-01 01:43:04 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
dag InOperandList = (ins ROS:$rs);
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
2013-10-01 01:43:04 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $rs");
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))];
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
class MSA_2R_FILL_PSEUDO_BASE<ValueType VT, SDPatternOperator OpNode,
RegisterClass RCWD, RegisterClass RCWS = RCWD> :
[mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
2013-11-20 22:32:28 +08:00
MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs),
[(set RCWD:$wd, (OpNode RCWS:$fs))]> {
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
let usesCustomInserter = 1;
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for the MSA instruction set. In more detail, this patch adds the ability to parse, encode and decode MSA registers ($w0-$w31). The format of 2RF instructions (MipsMSAInstrFormat.td) was updated so that we could attach a test case to this patch i.e., the test case parses, encodes and decodes 2 MSA instructions. Following patches will add the remainder of the instructions. Note that DecodeMSA128BRegisterClass is missing from MipsDisassembler.td because it's not yet required at this stage and having it would cause a compiler warning (unused function). Patch by Matheus Almeida llvm-svn: 191412
2013-09-26 07:50:44 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))];
InstrItinClass Itinerary = itin;
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests llvm-svn: 193695
2013-10-30 23:45:42 +08:00
class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
ROWT:$wt))];
string Constraints = "$wd = $wd_in";
InstrItinClass Itinerary = itin;
}
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
2013-10-30 21:07:44 +08:00
class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
dag OutOperandList = (outs ROWD:$wd);
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt);
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
2013-10-30 21:07:44 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))];
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
2013-10-30 21:07:44 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD,
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws,
ROWT:$wt))];
[mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) llvm-svn: 191301
2013-09-24 22:02:15 +08:00
string Constraints = "$wd = $wd_in";
InstrItinClass Itinerary = itin;
}
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
2013-10-30 21:07:44 +08:00
class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
InstrItinClass itin = NoItinerary> {
[mips][msa] Fix definition of SLD instruction. The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
2013-10-21 19:47:56 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt);
[mips][msa] Fix definition of SLD instruction. The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
2013-10-21 19:47:56 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]");
[mips][msa] Correct sld and sldi builtins. Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
2013-12-10 19:37:00 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
GPR32Opnd:$rt))];
[mips][msa] Fix definition of SLD instruction. The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
2013-10-21 19:47:56 +08:00
InstrItinClass Itinerary = itin;
[mips][msa] Correct sld and sldi builtins. Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
2013-12-10 19:37:00 +08:00
string Constraints = "$wd = $wd_in";
[mips][msa] Fix definition of SLD instruction. The second parameter of the SLD intrinsic is the number of columns (GPR) to slide left the source array. llvm-svn: 193076
2013-10-21 19:47:56 +08:00
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
[mips][msa] Correct sld and sldi builtins. Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
2013-12-10 19:37:00 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws,
ROWT:$wt))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD,
InstrItinClass itin = NoItinerary> :
MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD,
InstrItinClass itin = NoItinerary> :
MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> {
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
dag OutOperandList = (outs);
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
dag InOperandList = (ins ROWD:$wt, brtarget:$offset);
string AsmString = !strconcat(instr_asm, "\t$wt, $offset");
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
list<dag> Pattern = [];
InstrItinClass Itinerary = IIBranch;
bit isBranch = 1;
bit isTerminator = 1;
bit hasDelaySlot = 1;
list<Register> Defs = [AT];
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
2013-10-14 19:49:30 +08:00
RegisterOperand ROWD, RegisterOperand ROS,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
2013-10-14 19:49:30 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, uimm6_ptr:$n);
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs");
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
2013-10-14 19:49:30 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
ROS:$rs,
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
immZExt6Ptr:$n))];
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
RegisterOperand ROWD, RegisterOperand ROFS> :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, uimm6_ptr:$n, ROFS:$fs),
[mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
2013-11-20 22:32:28 +08:00
[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
immZExt6Ptr:$n))]> {
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
bit usesCustomInserter = 1;
string Constraints = "$wd = $wd_in";
}
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty,
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
RegisterOperand ROWD, RegisterOperand ROFS,
RegisterOperand ROIdx> :
MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs),
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
[(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs,
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
ROIdx:$n))]> {
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
bit usesCustomInserter = 1;
string Constraints = "$wd = $wd_in";
}
[mips][msa] Added insve llvm-svn: 188777
2013-08-20 17:22:54 +08:00
class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
dag OutOperandList = (outs ROWD:$wd);
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
dag InOperandList = (ins ROWD:$wd_in, uimm6:$n, ROWS:$ws, uimmz:$n2);
string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]");
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in,
[mips][msa] Made the operand register sets optional for the ELM_INSVE formats Their default is to be the same as the result register set. No functional change llvm-svn: 190151
2013-09-06 20:50:52 +08:00
immZExt6:$n,
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
ROWS:$ws,
immz:$n2))];
[mips][msa] Added insve llvm-svn: 188777
2013-08-20 17:22:54 +08:00
InstrItinClass Itinerary = itin;
string Constraints = "$wd = $wd_in";
}
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
RegisterOperand ROWD, RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, ROWT:$wt);
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt");
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))];
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
dag OutOperandList = (outs ROWD:$wd);
dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n);
string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]");
list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws,
ROWS:$ws))];
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
RegisterOperand ROWT = ROWD> :
[mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
2013-11-20 22:32:28 +08:00
MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt),
[(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b,
MSA128BOpnd>, IsCommutable;
class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h,
MSA128HOpnd>, IsCommutable;
class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w,
MSA128WOpnd>, IsCommutable;
class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d,
MSA128DOpnd>, IsCommutable;
class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b,
MSA128BOpnd>, IsCommutable;
class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h,
MSA128HOpnd>, IsCommutable;
class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w,
MSA128WOpnd>, IsCommutable;
class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d,
MSA128DOpnd>, IsCommutable;
class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b,
MSA128BOpnd>, IsCommutable;
class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h,
MSA128HOpnd>, IsCommutable;
class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w,
MSA128WOpnd>, IsCommutable;
class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d,
MSA128DOpnd>, IsCommutable;
class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable;
class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable;
class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable;
class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable;
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5,
MSA128BOpnd>;
class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5,
MSA128HOpnd>;
class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5,
MSA128WOpnd>;
class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>;
class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>;
class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>;
class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8,
MSA128BOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b,
MSA128BOpnd>;
class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h,
MSA128HOpnd>;
class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w,
MSA128WOpnd>;
class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d,
MSA128DOpnd>;
class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b,
MSA128BOpnd>;
class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h,
MSA128HOpnd>;
class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w,
MSA128WOpnd>;
class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d,
MSA128DOpnd>;
class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>,
[mips][msa] Made the operand register sets optional for the 3R format Their default is to be the same as the result register set. No functional change llvm-svn: 190133
2013-09-06 18:59:24 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b,
MSA128BOpnd>, IsCommutable;
class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h,
MSA128HOpnd>, IsCommutable;
class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w,
MSA128WOpnd>, IsCommutable;
class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d,
MSA128DOpnd>, IsCommutable;
class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b,
MSA128BOpnd>, IsCommutable;
class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h,
MSA128HOpnd>, IsCommutable;
class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w,
MSA128WOpnd>, IsCommutable;
class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d,
MSA128DOpnd>, IsCommutable;
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>;
class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>;
class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>;
class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2,
MSA128BOpnd>;
class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2,
MSA128HOpnd>;
class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2,
MSA128WOpnd>;
class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests llvm-svn: 193695
2013-10-30 23:45:42 +08:00
class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b,
MSA128BOpnd>;
class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h,
MSA128HOpnd>;
class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w,
MSA128WOpnd>;
class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
2013-10-30 22:45:14 +08:00
class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, MSA128BOpnd>;
class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, MSA128HOpnd>;
class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, MSA128WOpnd>;
class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Correct definition of bins[lr] and CHECK-DAG-ize related tests llvm-svn: 193695
2013-10-30 23:45:42 +08:00
class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b,
MSA128BOpnd>;
class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h,
MSA128HOpnd>;
class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w,
MSA128WOpnd>;
class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bins[lr]i.[bhwd] from normal IR (i.e. not intrinsics) This required correcting the definition of the bins[lr]i intrinsics because the result is also the first operand. It also required removing the (arbitrary) check for 32-bit immediates in MipsSEDAGToDAGISel::selectVSplat(). Currently using binsli.d with 2 bits set in the mask doesn't select binsli.d because the constant is legalized into a ConstantPool. Similar things can happen with binsri.d with more than 10 bits set in the mask. The resulting code when this happens is correct but not optimal. llvm-svn: 193687
2013-10-30 22:45:14 +08:00
class BINSRI_B_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, MSA128BOpnd>;
class BINSRI_H_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, MSA128HOpnd>;
class BINSRI_W_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, MSA128WOpnd>;
class BINSRI_D_DESC : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
2013-10-30 23:20:38 +08:00
class BMNZ_V_DESC {
dag OutOperandList = (outs MSA128BOpnd:$wd);
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
MSA128BOpnd:$wt);
string AsmString = "bmnz.v\t$wd, $ws, $wt";
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
MSA128BOpnd:$ws,
MSA128BOpnd:$wd_in))];
InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
2013-10-30 23:20:38 +08:00
class BMNZI_B_DESC {
dag OutOperandList = (outs MSA128BOpnd:$wd);
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
vsplat_uimm8:$u8);
string AsmString = "bmnzi.b\t$wd, $ws, $u8";
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
MSA128BOpnd:$ws,
MSA128BOpnd:$wd_in))];
InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
2013-10-30 23:20:38 +08:00
class BMZ_V_DESC {
dag OutOperandList = (outs MSA128BOpnd:$wd);
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
MSA128BOpnd:$wt);
string AsmString = "bmz.v\t$wd, $ws, $wt";
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt,
MSA128BOpnd:$wd_in,
MSA128BOpnd:$ws))];
InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[mips][msa] Added support for matching bmnz, bmnzi, bmz, and bmzi from normal IR (i.e. not intrinsics) Also corrected the definition of the intrinsics for these instructions (the result register is also the first operand), and added intrinsics for bsel and bseli to clang (they already existed in the backend). These four operations are mostly equivalent to bsel, and bseli (the difference is which operand is tied to the result). As a result some of the tests changed as described below. bitwise.ll: - bsel.v test adapted so that the mask is unknown at compile-time. This stops it emitting bmnzi.b instead of the intended bsel.v. - The bseli.b test now tests the right thing. Namely the case when one of the values is an uimm8, rather than when the condition is a uimm8 (which is covered by bmnzi.b) compare.ll: - bsel.v tests now (correctly) emits bmnz.v instead of bsel.v because this is the same operation (see MSA.txt). i8.ll - CHECK-DAG-ized test. - bmzi.b test now (correctly) emits equivalent bmnzi.b with swapped operands because this is the same operation (see MSA.txt). - bseli.b still emits bseli.b though because the immediate makes it distinguishable from bmnzi.b. vec.ll: - CHECK-DAG-ized test. - bmz.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). - bsel.v tests now (correctly) emits bmnz.v with swapped operands (see MSA.txt). llvm-svn: 193693
2013-10-30 23:20:38 +08:00
class BMZI_B_DESC {
dag OutOperandList = (outs MSA128BOpnd:$wd);
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
vsplat_uimm8:$u8);
string AsmString = "bmzi.b\t$wd, $ws, $u8";
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8,
MSA128BOpnd:$wd_in,
MSA128BOpnd:$ws))];
InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>;
class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>;
class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>;
class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
long line correction llvm-svn: 195175
2013-11-20 08:12:44 +08:00
class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2,
MSA128BOpnd>;
class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2,
MSA128HOpnd>;
class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2,
MSA128WOpnd>;
class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>;
class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>;
class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>;
class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
class BSEL_V_DESC {
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
dag OutOperandList = (outs MSA128BOpnd:$wd);
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
MSA128BOpnd:$wt);
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
string AsmString = "bsel.v\t$wd, $ws, $wt";
[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
2014-03-12 19:54:00 +08:00
// Note that vselect and BSEL_V treat the condition operand the opposite way
// from each other.
// (vselect cond, if_set, if_clear)
// (BSEL_V cond, if_clear, if_set)
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
list<dag> Pattern = [(set MSA128BOpnd:$wd,
[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
2014-03-12 19:54:00 +08:00
(vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt,
MSA128BOpnd:$ws))];
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
class BSELI_B_DESC {
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
dag OutOperandList = (outs MSA128BOpnd:$wd);
dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws,
vsplat_uimm8:$u8);
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
string AsmString = "bseli.b\t$wd, $ws, $u8";
[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
2014-03-12 19:54:00 +08:00
// Note that vselect and BSEL_V treat the condition operand the opposite way
// from each other.
// (vselect cond, if_set, if_clear)
// (BSEL_V cond, if_clear, if_set)
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in,
[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
2014-03-12 19:54:00 +08:00
vsplati8_uimm8:$u8,
MSA128BOpnd:$ws))];
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
InstrItinClass Itinerary = NoItinerary;
string Constraints = "$wd = $wd_in";
}
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>;
class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>;
class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>;
class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching bclr, and bclri from normal IR (i.e. not intrinsics) llvm-svn: 194471
2013-11-12 18:45:18 +08:00
class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2,
MSA128BOpnd>;
class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2,
MSA128HOpnd>;
class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2,
MSA128WOpnd>;
class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>;
class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>;
class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>;
class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[mips][msa] Direct Object Emission support for conditional branches. These branches have a 16-bit offset (R_MIPS_PC16). List of conditional branch instructions: bnz.{b,h,w,d} bnz.v bz.{b,h,w,d} bz.v llvm-svn: 193157
2013-10-22 17:43:32 +08:00
class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
2013-08-28 18:26:24 +08:00
class CFCMSA_DESC {
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
dag OutOperandList = (outs GPR32Opnd:$rd);
dag InOperandList = (ins MSA128CROpnd:$cs);
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
2013-08-28 18:26:24 +08:00
string AsmString = "cfcmsa\t$rd, $cs";
InstrItinClass Itinerary = NoItinerary;
bit hasSideEffects = 1;
}
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>;
class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>;
class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>;
class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>;
class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>;
class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>;
class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati8_simm5, MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati16_simm5, MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati32_simm5, MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati64_simm5, MSA128DOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati8_uimm5, MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati16_uimm5, MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati32_uimm5, MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati64_uimm5, MSA128DOpnd>;
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
2013-09-24 18:46:19 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>;
class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>;
class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>;
class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>;
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
2013-09-24 18:46:19 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>;
class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>;
class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>;
class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>;
[mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) MIPS SelectionDAG changes: * Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask. llvm-svn: 191286
2013-09-24 18:46:19 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati8_simm5, MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati16_simm5, MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati32_simm5, MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati64_simm5, MSA128DOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati8_uimm5, MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati16_uimm5, MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati32_uimm5, MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
vsplati64_uimm5, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
GPR32Opnd, MSA128BOpnd>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
GPR32Opnd, MSA128HOpnd>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
GPR32Opnd, MSA128WOpnd>;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64,
GPR64Opnd, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
GPR32Opnd, MSA128BOpnd>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
GPR32Opnd, MSA128HOpnd>;
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
GPR32Opnd, MSA128WOpnd>;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
class COPY_U_D_DESC : MSA_COPY_DESC_BASE<"copy_u.d", vextract_zext_i64, v2i64,
GPR64Opnd, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
2013-09-27 20:17:32 +08:00
class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, FGR32,
MSA128W>;
class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, FGR64,
MSA128D>;
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
2013-08-28 18:26:24 +08:00
class CTCMSA_DESC {
dag OutOperandList = (outs);
[mips][msa] Direct Object Emission support for CTCMSA and CFCMSA. These instructions are logically related as they allow read/write of MSA control registers. Currently MSA control registers are emitted by number but hopefully that will change as soon as GAS starts accepting them by name as that would make the assembly easier to read. llvm-svn: 193078
2013-10-21 20:26:50 +08:00
dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs);
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
2013-08-28 18:26:24 +08:00
string AsmString = "ctcmsa\t$cd, $rs";
InstrItinClass Itinerary = NoItinerary;
bit hasSideEffects = 1;
}
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>;
class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>;
class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>;
class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>;
class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>;
class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>;
class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>;
class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>;
class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h,
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
IsCommutable;
class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w,
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
IsCommutable;
class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d,
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
IsCommutable;
class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h,
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>,
IsCommutable;
class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w,
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>,
IsCommutable;
class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d,
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>,
IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128HOpnd, MSA128BOpnd,
MSA128BOpnd>, IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128WOpnd, MSA128HOpnd,
MSA128HOpnd>, IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128DOpnd, MSA128WOpnd,
MSA128WOpnd>, IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128HOpnd, MSA128BOpnd,
MSA128BOpnd>, IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128WOpnd, MSA128HOpnd,
MSA128HOpnd>, IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128DOpnd, MSA128WOpnd,
MSA128WOpnd>, IsCommutable;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128HOpnd, MSA128BOpnd,
MSA128BOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128WOpnd, MSA128HOpnd,
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128DOpnd, MSA128WOpnd,
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128HOpnd, MSA128BOpnd,
MSA128BOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128WOpnd, MSA128HOpnd,
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128DOpnd, MSA128WOpnd,
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>,
IsCommutable;
class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>,
IsCommutable;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w,
MSA128WOpnd>;
class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>;
class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>;
class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>,
[mips][msa] Indentation llvm-svn: 190156
2013-09-06 21:25:06 +08:00
IsCommutable;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>;
class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) llvm-svn: 193239
2013-10-23 18:36:52 +08:00
// The fexp2.df instruction multiplies the first operand by 2 to the power of
// the second operand. We therefore need a pseudo-insn in order to invent the
// 1.0 when we only need to match ISD::FEXP2.
class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>;
class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>;
let usesCustomInserter = 1 in {
class FEXP2_W_1_PSEUDO_DESC :
[mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
2013-11-20 22:32:28 +08:00
MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws),
[(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>;
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) llvm-svn: 193239
2013-10-23 18:36:52 +08:00
class FEXP2_D_1_PSEUDO_DESC :
[mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
2013-11-20 22:32:28 +08:00
MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws),
[(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>;
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) llvm-svn: 193239
2013-10-23 18:36:52 +08:00
}
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128WOpnd, MSA128HOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128DOpnd, MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128WOpnd, MSA128HOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128DOpnd, MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) llvm-svn: 192429
2013-10-11 18:00:06 +08:00
class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>;
class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Added support for matching ffint_[us].[wd], and ftrunc_[us].[wd] from normal IR (i.e. not intrinsics) llvm-svn: 192429
2013-10-11 18:00:06 +08:00
class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>;
class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128WOpnd, MSA128HOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128DOpnd, MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128WOpnd, MSA128HOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128DOpnd, MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR and not an MSA register Patch by Matheus Almeida llvm-svn: 191684
2013-10-01 01:43:04 +08:00
class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8,
MSA128BOpnd, GPR32Opnd>;
class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16,
MSA128HOpnd, GPR32Opnd>;
class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32,
MSA128WOpnd, GPR32Opnd>;
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64,
MSA128DOpnd, GPR64Opnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v4f32, vsplatf32, MSA128W,
FGR32>;
class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<v2f64, vsplatf64, MSA128D,
FGR64>;
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>;
class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Added support for matching fmadd.[wd] from normal IR (i.e. not intrinsics) llvm-svn: 192430
2013-10-11 18:14:25 +08:00
class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>;
class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>;
class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>;
class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Added support for matching fmsub.[wd] from normal IR (i.e. not intrinsics) llvm-svn: 192435
2013-10-11 18:27:32 +08:00
class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", fms, MSA128WOpnd>;
class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", fms, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>;
class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>;
class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>;
class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>;
class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>;
class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>;
class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>;
class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>;
class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>;
class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>;
class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>;
class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w,
MSA128WOpnd>;
class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d,
MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w,
MSA128WOpnd>;
class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d,
MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w,
MSA128WOpnd>;
class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d,
MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w,
MSA128WOpnd>;
class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d,
MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w,
MSA128WOpnd>;
class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d,
MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d,
[mips][msa] Direct Object Emission for 2RF instructions. Patch by Matheus Almeida llvm-svn: 191413
2013-09-26 07:56:25 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq. Define these three instructions in alphabetical order (like the rest of the file). No functional change. llvm-svn: 192880
2013-10-17 18:30:12 +08:00
class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint,
MSA128WOpnd>;
class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint,
MSA128DOpnd>;
class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint,
MSA128WOpnd>;
class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint,
MSA128DOpnd>;
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h,
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w,
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d,
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h,
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w,
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d,
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h,
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w,
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d,
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h,
MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>;
class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w,
MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>;
class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d,
MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>;
class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>;
class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>;
class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>;
class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>;
class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>;
class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>;
class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>;
class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>;
class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>;
class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>;
class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>;
class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>;
class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>;
class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>;
class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>;
class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission of INSERT.{B,H,W} instruction. INSERT is the first type of MSA instruction that requires a change to the way MSA registers are parsed. This happens because MSA registers may be suffixed by an index in the form of an immediate or a general purpose register. The changes to parseMSARegs reflect that requirement. llvm-svn: 192582
2013-10-14 19:49:30 +08:00
class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8,
MSA128BOpnd, GPR32Opnd>;
class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16,
MSA128HOpnd, GPR32Opnd>;
class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32,
MSA128WOpnd, GPR32Opnd>;
[mips][msa] Add insert.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200543
2014-01-31 21:31:20 +08:00
class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64,
MSA128DOpnd, GPR64Opnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
class INSERT_B_VIDX_PSEUDO_DESC :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
class INSERT_H_VIDX_PSEUDO_DESC :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
class INSERT_W_VIDX_PSEUDO_DESC :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
class INSERT_D_VIDX_PSEUDO_DESC :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
MSA128WOpnd, FGR32Opnd>;
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
MSA128DOpnd, FGR64Opnd>;
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
class INSERT_FW_VIDX_PSEUDO_DESC :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
class INSERT_FD_VIDX_PSEUDO_DESC :
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>;
class INSERT_B_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>;
class INSERT_H_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>;
class INSERT_W_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>;
class INSERT_D_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>;
class INSERT_FW_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>;
class INSERT_FD_VIDX64_PSEUDO_DESC :
MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
MSA128BOpnd>;
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
MSA128HOpnd>;
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
MSA128WOpnd>;
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64,
[mips][msa] Direct Object Emission of INSVE.{b,h,w,d}. llvm-svn: 192587
2013-10-14 20:38:17 +08:00
MSA128DOpnd>;
[mips][msa] Added insve llvm-svn: 188777
2013-08-20 17:22:54 +08:00
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
ValueType TyNode, RegisterOperand ROWD,
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
2014-03-03 22:31:21 +08:00
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
dag OutOperandList = (outs ROWD:$wd);
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
dag InOperandList = (ins MemOpnd:$addr);
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))];
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
InstrItinClass Itinerary = itin;
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
string DecoderMethod = "DecodeMSA128Mem";
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
}
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd>;
class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd>;
class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd>;
class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Direct Object Emission support for LDI instructions. llvm-svn: 193081
2013-10-21 20:56:20 +08:00
class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>;
class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>;
class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>;
class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Make LSA_DESC a parameterizable class. This way it's possible to share the instruction's description for LSA and DLSA (to be added). No functional changes. llvm-svn: 201078
2014-02-10 19:15:37 +08:00
class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD,
RegisterOperand RORS = RORD, RegisterOperand RORT = RORD,
InstrItinClass itin = NoItinerary > {
dag OutOperandList = (outs RORD:$rd);
dag InOperandList = (ins RORS:$rs, RORT:$rt, LSAImm:$sa);
string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa");
list<dag> Pattern = [(set RORD:$rd, (add RORT:$rt,
(shl RORS:$rs,
[mips][msa] Direct Object Emission support for the LSA instruction. llvm-svn: 193240
2013-10-23 21:20:07 +08:00
immZExt2Lsa:$sa)))];
[mips][msa] Make LSA_DESC a parameterizable class. This way it's possible to share the instruction's description for LSA and DLSA (to be added). No functional changes. llvm-svn: 201078
2014-02-10 19:15:37 +08:00
InstrItinClass Itinerary = itin;
[mips][msa] Added lsa instruction llvm-svn: 192895
2013-10-17 21:38:20 +08:00
}
[mips][msa] Added load/store intrinsics. llvm-svn: 189476
2013-08-28 20:04:29 +08:00
[mips][msa] Make LSA_DESC a parameterizable class. This way it's possible to share the instruction's description for LSA and DLSA (to be added). No functional changes. llvm-svn: 201078
2014-02-10 19:15:37 +08:00
class LSA_DESC : LSA_DESC_BASE<"lsa", GPR32Opnd>;
[mips][msa] Add DLSA instruction. llvm-svn: 201081
2014-02-10 20:05:17 +08:00
class DLSA_DESC : LSA_DESC_BASE<"dlsa", GPR64Opnd>;
[mips][msa] Make LSA_DESC a parameterizable class. This way it's possible to share the instruction's description for LSA and DLSA (to be added). No functional changes. llvm-svn: 201078
2014-02-10 19:15:37 +08:00
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MADD_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.h", int_mips_madd_q_h,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MADD_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"madd_q.w", int_mips_madd_q_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MADDR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.h", int_mips_maddr_q_h,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MADDR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"maddr_q.w", int_mips_maddr_q_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) llvm-svn: 192438
2013-10-11 18:50:42 +08:00
class MADDV_B_DESC : MSA_3R_4R_DESC_BASE<"maddv.b", muladd, MSA128BOpnd>;
class MADDV_H_DESC : MSA_3R_4R_DESC_BASE<"maddv.h", muladd, MSA128HOpnd>;
class MADDV_W_DESC : MSA_3R_4R_DESC_BASE<"maddv.w", muladd, MSA128WOpnd>;
class MADDV_D_DESC : MSA_3R_4R_DESC_BASE<"maddv.d", muladd, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MAX_A_B_DESC : MSA_3R_DESC_BASE<"max_a.b", int_mips_max_a_b, MSA128BOpnd>;
class MAX_A_H_DESC : MSA_3R_DESC_BASE<"max_a.h", int_mips_max_a_h, MSA128HOpnd>;
class MAX_A_W_DESC : MSA_3R_DESC_BASE<"max_a.w", int_mips_max_a_w, MSA128WOpnd>;
class MAX_A_D_DESC : MSA_3R_DESC_BASE<"max_a.d", int_mips_max_a_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MAX_S_B_DESC : MSA_3R_DESC_BASE<"max_s.b", MipsVSMax, MSA128BOpnd>;
class MAX_S_H_DESC : MSA_3R_DESC_BASE<"max_s.h", MipsVSMax, MSA128HOpnd>;
class MAX_S_W_DESC : MSA_3R_DESC_BASE<"max_s.w", MipsVSMax, MSA128WOpnd>;
class MAX_S_D_DESC : MSA_3R_DESC_BASE<"max_s.d", MipsVSMax, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MAX_U_B_DESC : MSA_3R_DESC_BASE<"max_u.b", MipsVUMax, MSA128BOpnd>;
class MAX_U_H_DESC : MSA_3R_DESC_BASE<"max_u.h", MipsVUMax, MSA128HOpnd>;
class MAX_U_W_DESC : MSA_3R_DESC_BASE<"max_u.w", MipsVUMax, MSA128WOpnd>;
class MAX_U_D_DESC : MSA_3R_DESC_BASE<"max_u.d", MipsVUMax, MSA128DOpnd>;
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) llvm-svn: 191291
2013-09-24 20:18:31 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_S_B_DESC : MSA_I5_DESC_BASE<"maxi_s.b", MipsVSMax, vsplati8_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_S_H_DESC : MSA_I5_DESC_BASE<"maxi_s.h", MipsVSMax, vsplati16_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_S_W_DESC : MSA_I5_DESC_BASE<"maxi_s.w", MipsVSMax, vsplati32_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_S_D_DESC : MSA_I5_DESC_BASE<"maxi_s.d", MipsVSMax, vsplati64_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128DOpnd>;
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) llvm-svn: 191291
2013-09-24 20:18:31 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_U_B_DESC : MSA_I5_DESC_BASE<"maxi_u.b", MipsVUMax, vsplati8_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_U_H_DESC : MSA_I5_DESC_BASE<"maxi_u.h", MipsVUMax, vsplati16_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_U_W_DESC : MSA_I5_DESC_BASE<"maxi_u.w", MipsVUMax, vsplati32_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MAXI_U_D_DESC : MSA_I5_DESC_BASE<"maxi_u.d", MipsVUMax, vsplati64_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MIN_A_B_DESC : MSA_3R_DESC_BASE<"min_a.b", int_mips_min_a_b, MSA128BOpnd>;
class MIN_A_H_DESC : MSA_3R_DESC_BASE<"min_a.h", int_mips_min_a_h, MSA128HOpnd>;
class MIN_A_W_DESC : MSA_3R_DESC_BASE<"min_a.w", int_mips_min_a_w, MSA128WOpnd>;
class MIN_A_D_DESC : MSA_3R_DESC_BASE<"min_a.d", int_mips_min_a_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MIN_S_B_DESC : MSA_3R_DESC_BASE<"min_s.b", MipsVSMin, MSA128BOpnd>;
class MIN_S_H_DESC : MSA_3R_DESC_BASE<"min_s.h", MipsVSMin, MSA128HOpnd>;
class MIN_S_W_DESC : MSA_3R_DESC_BASE<"min_s.w", MipsVSMin, MSA128WOpnd>;
class MIN_S_D_DESC : MSA_3R_DESC_BASE<"min_s.d", MipsVSMin, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MIN_U_B_DESC : MSA_3R_DESC_BASE<"min_u.b", MipsVUMin, MSA128BOpnd>;
class MIN_U_H_DESC : MSA_3R_DESC_BASE<"min_u.h", MipsVUMin, MSA128HOpnd>;
class MIN_U_W_DESC : MSA_3R_DESC_BASE<"min_u.w", MipsVUMin, MSA128WOpnd>;
class MIN_U_D_DESC : MSA_3R_DESC_BASE<"min_u.d", MipsVUMin, MSA128DOpnd>;
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) llvm-svn: 191291
2013-09-24 20:18:31 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_S_B_DESC : MSA_I5_DESC_BASE<"mini_s.b", MipsVSMin, vsplati8_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_S_H_DESC : MSA_I5_DESC_BASE<"mini_s.h", MipsVSMin, vsplati16_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_S_W_DESC : MSA_I5_DESC_BASE<"mini_s.w", MipsVSMin, vsplati32_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_S_D_DESC : MSA_I5_DESC_BASE<"mini_s.d", MipsVSMin, vsplati64_simm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128DOpnd>;
[mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) llvm-svn: 191291
2013-09-24 20:18:31 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_U_B_DESC : MSA_I5_DESC_BASE<"mini_u.b", MipsVUMin, vsplati8_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_U_H_DESC : MSA_I5_DESC_BASE<"mini_u.h", MipsVUMin, vsplati16_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_U_W_DESC : MSA_I5_DESC_BASE<"mini_u.w", MipsVUMin, vsplati32_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class MINI_U_D_DESC : MSA_I5_DESC_BASE<"mini_u.d", MipsVUMin, vsplati64_uimm5,
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics) llvm-svn: 191737
2013-10-01 18:22:35 +08:00
class MOD_S_B_DESC : MSA_3R_DESC_BASE<"mod_s.b", srem, MSA128BOpnd>;
class MOD_S_H_DESC : MSA_3R_DESC_BASE<"mod_s.h", srem, MSA128HOpnd>;
class MOD_S_W_DESC : MSA_3R_DESC_BASE<"mod_s.w", srem, MSA128WOpnd>;
class MOD_S_D_DESC : MSA_3R_DESC_BASE<"mod_s.d", srem, MSA128DOpnd>;
class MOD_U_B_DESC : MSA_3R_DESC_BASE<"mod_u.b", urem, MSA128BOpnd>;
class MOD_U_H_DESC : MSA_3R_DESC_BASE<"mod_u.h", urem, MSA128HOpnd>;
class MOD_U_W_DESC : MSA_3R_DESC_BASE<"mod_u.w", urem, MSA128WOpnd>;
class MOD_U_D_DESC : MSA_3R_DESC_BASE<"mod_u.d", urem, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added move.v llvm-svn: 189471
2013-08-28 18:44:47 +08:00
class MOVE_V_DESC {
[mips][msa] Direct Object Emission support for MOVE.v. llvm-svn: 193080
2013-10-21 20:43:54 +08:00
dag OutOperandList = (outs MSA128BOpnd:$wd);
dag InOperandList = (ins MSA128BOpnd:$ws);
[mips][msa] Added move.v llvm-svn: 189471
2013-08-28 18:44:47 +08:00
string AsmString = "move.v\t$wd, $ws";
list<dag> Pattern = [];
InstrItinClass Itinerary = NoItinerary;
}
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MSUB_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.h", int_mips_msub_q_h,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MSUB_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msub_q.w", int_mips_msub_q_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MSUBR_Q_H_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.h", int_mips_msubr_q_h,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MSUBR_Q_W_DESC : MSA_3RF_4RF_DESC_BASE<"msubr_q.w", int_mips_msubr_q_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching maddv.[bhwd], and msubv.[bhwd] from normal IR (i.e. not intrinsics) llvm-svn: 192438
2013-10-11 18:50:42 +08:00
class MSUBV_B_DESC : MSA_3R_4R_DESC_BASE<"msubv.b", mulsub, MSA128BOpnd>;
class MSUBV_H_DESC : MSA_3R_4R_DESC_BASE<"msubv.h", mulsub, MSA128HOpnd>;
class MSUBV_W_DESC : MSA_3R_4R_DESC_BASE<"msubv.w", mulsub, MSA128WOpnd>;
class MSUBV_D_DESC : MSA_3R_4R_DESC_BASE<"msubv.d", mulsub, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class MUL_Q_H_DESC : MSA_3RF_DESC_BASE<"mul_q.h", int_mips_mul_q_h,
MSA128HOpnd>;
class MUL_Q_W_DESC : MSA_3RF_DESC_BASE<"mul_q.w", int_mips_mul_q_w,
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MULR_Q_H_DESC : MSA_3RF_DESC_BASE<"mulr_q.h", int_mips_mulr_q_h,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class MULR_Q_W_DESC : MSA_3RF_DESC_BASE<"mulr_q.w", int_mips_mulr_q_w,
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class MULV_B_DESC : MSA_3R_DESC_BASE<"mulv.b", mul, MSA128BOpnd>;
class MULV_H_DESC : MSA_3R_DESC_BASE<"mulv.h", mul, MSA128HOpnd>;
class MULV_W_DESC : MSA_3R_DESC_BASE<"mulv.w", mul, MSA128WOpnd>;
class MULV_D_DESC : MSA_3R_DESC_BASE<"mulv.d", mul, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 2R instructions. This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
2013-10-01 01:52:33 +08:00
class NLOC_B_DESC : MSA_2R_DESC_BASE<"nloc.b", int_mips_nloc_b, MSA128BOpnd>;
class NLOC_H_DESC : MSA_2R_DESC_BASE<"nloc.h", int_mips_nloc_h, MSA128HOpnd>;
class NLOC_W_DESC : MSA_2R_DESC_BASE<"nloc.w", int_mips_nloc_w, MSA128WOpnd>;
class NLOC_D_DESC : MSA_2R_DESC_BASE<"nloc.d", int_mips_nloc_d, MSA128DOpnd>;
[mips][msa] Made the operand register sets optional for the 2RF format Their default is to be the same as the result register set. No functional change llvm-svn: 190143
2013-09-06 20:28:13 +08:00
[mips][msa] Direct Object Emission for 2R instructions. This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
2013-10-01 01:52:33 +08:00
class NLZC_B_DESC : MSA_2R_DESC_BASE<"nlzc.b", ctlz, MSA128BOpnd>;
class NLZC_H_DESC : MSA_2R_DESC_BASE<"nlzc.h", ctlz, MSA128HOpnd>;
class NLZC_W_DESC : MSA_2R_DESC_BASE<"nlzc.w", ctlz, MSA128WOpnd>;
class NLZC_D_DESC : MSA_2R_DESC_BASE<"nlzc.d", ctlz, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
class NOR_V_DESC : MSA_VEC_DESC_BASE<"nor.v", MipsVNOR, MSA128BOpnd>;
class NOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128HOpnd>;
class NOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128WOpnd>;
class NOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<MipsVNOR, MSA128DOpnd>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class NORI_B_DESC : MSA_I8_DESC_BASE<"nori.b", MipsVNOR, vsplati8_uimm8,
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
MSA128BOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
class OR_V_DESC : MSA_VEC_DESC_BASE<"or.v", or, MSA128BOpnd>;
class OR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128HOpnd>;
class OR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128WOpnd>;
class OR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<or, MSA128DOpnd>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
class ORI_B_DESC : MSA_I8_DESC_BASE<"ori.b", or, vsplati8_uimm8, MSA128BOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class PCKEV_B_DESC : MSA_3R_DESC_BASE<"pckev.b", MipsPCKEV, MSA128BOpnd>;
class PCKEV_H_DESC : MSA_3R_DESC_BASE<"pckev.h", MipsPCKEV, MSA128HOpnd>;
class PCKEV_W_DESC : MSA_3R_DESC_BASE<"pckev.w", MipsPCKEV, MSA128WOpnd>;
class PCKEV_D_DESC : MSA_3R_DESC_BASE<"pckev.d", MipsPCKEV, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class PCKOD_B_DESC : MSA_3R_DESC_BASE<"pckod.b", MipsPCKOD, MSA128BOpnd>;
class PCKOD_H_DESC : MSA_3R_DESC_BASE<"pckod.h", MipsPCKOD, MSA128HOpnd>;
class PCKOD_W_DESC : MSA_3R_DESC_BASE<"pckod.w", MipsPCKOD, MSA128WOpnd>;
class PCKOD_D_DESC : MSA_3R_DESC_BASE<"pckod.d", MipsPCKOD, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 2R instructions. This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}. Patch by Matheus Almeida llvm-svn: 191685
2013-10-01 01:52:33 +08:00
class PCNT_B_DESC : MSA_2R_DESC_BASE<"pcnt.b", ctpop, MSA128BOpnd>;
class PCNT_H_DESC : MSA_2R_DESC_BASE<"pcnt.h", ctpop, MSA128HOpnd>;
class PCNT_W_DESC : MSA_2R_DESC_BASE<"pcnt.w", ctpop, MSA128WOpnd>;
class PCNT_D_DESC : MSA_2R_DESC_BASE<"pcnt.d", ctpop, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
class SAT_S_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_s.b", int_mips_sat_s_b,
MSA128BOpnd>;
class SAT_S_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_s.h", int_mips_sat_s_h,
MSA128HOpnd>;
class SAT_S_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_s.w", int_mips_sat_s_w,
MSA128WOpnd>;
class SAT_S_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_s.d", int_mips_sat_s_d,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
class SAT_U_B_DESC : MSA_BIT_B_X_DESC_BASE<"sat_u.b", int_mips_sat_u_b,
MSA128BOpnd>;
class SAT_U_H_DESC : MSA_BIT_H_X_DESC_BASE<"sat_u.h", int_mips_sat_u_h,
MSA128HOpnd>;
class SAT_U_W_DESC : MSA_BIT_W_X_DESC_BASE<"sat_u.w", int_mips_sat_u_w,
MSA128WOpnd>;
class SAT_U_D_DESC : MSA_BIT_D_X_DESC_BASE<"sat_u.d", int_mips_sat_u_d,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
class SHF_B_DESC : MSA_I8_SHF_DESC_BASE<"shf.b", MSA128BOpnd>;
class SHF_H_DESC : MSA_I8_SHF_DESC_BASE<"shf.h", MSA128HOpnd>;
class SHF_W_DESC : MSA_I8_SHF_DESC_BASE<"shf.w", MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
2013-10-30 21:07:44 +08:00
class SLD_B_DESC : MSA_3R_SLD_DESC_BASE<"sld.b", int_mips_sld_b, MSA128BOpnd>;
class SLD_H_DESC : MSA_3R_SLD_DESC_BASE<"sld.h", int_mips_sld_h, MSA128HOpnd>;
class SLD_W_DESC : MSA_3R_SLD_DESC_BASE<"sld.w", int_mips_sld_w, MSA128WOpnd>;
class SLD_D_DESC : MSA_3R_SLD_DESC_BASE<"sld.d", int_mips_sld_d, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Correct sld and sldi builtins. Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
2013-12-10 19:37:00 +08:00
class SLDI_B_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.b", int_mips_sldi_b,
MSA128BOpnd>;
class SLDI_H_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.h", int_mips_sldi_h,
MSA128HOpnd>;
class SLDI_W_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.w", int_mips_sldi_w,
MSA128WOpnd>;
class SLDI_D_DESC : MSA_ELM_SLD_DESC_BASE<"sldi.d", int_mips_sldi_d,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class SLL_B_DESC : MSA_3R_DESC_BASE<"sll.b", shl, MSA128BOpnd>;
class SLL_H_DESC : MSA_3R_DESC_BASE<"sll.h", shl, MSA128HOpnd>;
class SLL_W_DESC : MSA_3R_DESC_BASE<"sll.w", shl, MSA128WOpnd>;
class SLL_D_DESC : MSA_3R_DESC_BASE<"sll.d", shl, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SLLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.b", shl, vsplati8_uimm3,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SLLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.h", shl, vsplati16_uimm4,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SLLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.w", shl, vsplati32_uimm5,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SLLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"slli.d", shl, vsplati64_uimm6,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching splat.[bhw] from normal IR (i.e. not intrinsics) splat.d is implemented but this subtest is currently disabled. This is because it is difficult to match the appropriate IR on MIPS32. There is a patch under review that should help with this so I hope to enable the subtest soon. llvm-svn: 193680
2013-10-30 21:07:44 +08:00
class SPLAT_B_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.b", vsplati8_elt,
MSA128BOpnd>;
class SPLAT_H_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.h", vsplati16_elt,
MSA128HOpnd>;
class SPLAT_W_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.w", vsplati32_elt,
MSA128WOpnd>;
class SPLAT_D_DESC : MSA_3R_SPLAT_DESC_BASE<"splat.d", vsplati64_elt,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
class SPLATI_B_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.b", vsplati8_uimm4,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
MSA128BOpnd>;
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
class SPLATI_H_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.h", vsplati16_uimm3,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
MSA128HOpnd>;
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
class SPLATI_W_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.w", vsplati32_uimm2,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
MSA128WOpnd>;
[mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) Updated some of the vshf since they (correctly) emit splati's now llvm-svn: 191511
2013-09-27 19:48:57 +08:00
class SPLATI_D_DESC : MSA_ELM_SPLAT_DESC_BASE<"splati.d", vsplati64_uimm1,
[mips][msa] Direct Object Emission for the majority of the ELM instructions. List of instructions: copy_s.{b,h,w} copy_u.{b,h,w} sldi.{b,h,w,d} splati.{b,h,w,d} llvm-svn: 192586
2013-10-14 20:22:43 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class SRA_B_DESC : MSA_3R_DESC_BASE<"sra.b", sra, MSA128BOpnd>;
class SRA_H_DESC : MSA_3R_DESC_BASE<"sra.h", sra, MSA128HOpnd>;
class SRA_W_DESC : MSA_3R_DESC_BASE<"sra.w", sra, MSA128WOpnd>;
class SRA_D_DESC : MSA_3R_DESC_BASE<"sra.d", sra, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRAI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.b", sra, vsplati8_uimm3,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRAI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.h", sra, vsplati16_uimm4,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRAI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.w", sra, vsplati32_uimm5,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRAI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srai.d", sra, vsplati64_uimm6,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class SRAR_B_DESC : MSA_3R_DESC_BASE<"srar.b", int_mips_srar_b, MSA128BOpnd>;
class SRAR_H_DESC : MSA_3R_DESC_BASE<"srar.h", int_mips_srar_h, MSA128HOpnd>;
class SRAR_W_DESC : MSA_3R_DESC_BASE<"srar.w", int_mips_srar_w, MSA128WOpnd>;
class SRAR_D_DESC : MSA_3R_DESC_BASE<"srar.d", int_mips_srar_d, MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
class SRARI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srari.b", int_mips_srari_b,
MSA128BOpnd>;
class SRARI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srari.h", int_mips_srari_h,
MSA128HOpnd>;
class SRARI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srari.w", int_mips_srari_w,
MSA128WOpnd>;
class SRARI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srari.d", int_mips_srari_d,
MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class SRL_B_DESC : MSA_3R_DESC_BASE<"srl.b", srl, MSA128BOpnd>;
class SRL_H_DESC : MSA_3R_DESC_BASE<"srl.h", srl, MSA128HOpnd>;
class SRL_W_DESC : MSA_3R_DESC_BASE<"srl.w", srl, MSA128WOpnd>;
class SRL_D_DESC : MSA_3R_DESC_BASE<"srl.d", srl, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRLI_B_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.b", srl, vsplati8_uimm3,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128BOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRLI_H_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.h", srl, vsplati16_uimm4,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128HOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRLI_W_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.w", srl, vsplati32_uimm5,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128WOpnd>;
[mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover bitcasted as well as normal vectors. However, it doesn't seem to be possible to match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of immediates, it should be possible to use ldi.b to load v2i64) using TableGen so ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp This made the majority of the constant splat BUILD_VECTOR lowering redundant. The only transformation remaining for constant splats is when an (up-to) 32-bit constant splat is possible but the value does not fit into a 10-bit signed integer. In this case, the BUILD_VECTOR is transformed into a bitcasted BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32 register (which is initialized using the usual lui/addui sequence). There are no additional tests since this is a re-implementation of previous functionality. The change is intended to make it easier to implement some of the upcoming instruction selection patches since they can rely on existing support for BUILD_VECTOR's in the DAGCombiner. compare_float.ll changed slightly because a BITCAST is no longer introduced during legalization. llvm-svn: 191299
2013-09-24 21:33:07 +08:00
class SRLI_D_DESC : MSA_BIT_SPLAT_DESC_BASE<"srli.d", srl, vsplati64_uimm6,
[mips][msa] Direct Object Emission support for BIT instructions. List of instructions: bclri.{b,h,w,d} binsli.{b,h,w,d} binsri.{b,h,w,d} bnegi.{b,h,w,d} bseti.{b,h,w,d} sat_s.{b,h,w,d} sat_u.{b,h,w,d} slli.{b,h,w,d} srai.{b,h,w,d} srari.{b,h,w,d} srli.{b,h,w,d} srlri.{b,h,w,d} llvm-svn: 192589
2013-10-14 21:07:39 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class SRLR_B_DESC : MSA_3R_DESC_BASE<"srlr.b", int_mips_srlr_b, MSA128BOpnd>;
class SRLR_H_DESC : MSA_3R_DESC_BASE<"srlr.h", int_mips_srlr_h, MSA128HOpnd>;
class SRLR_W_DESC : MSA_3R_DESC_BASE<"srlr.w", int_mips_srlr_w, MSA128WOpnd>;
class SRLR_D_DESC : MSA_3R_DESC_BASE<"srlr.d", int_mips_srlr_d, MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Added support for matching bset, bseti, bneg, and bnegi from normal IR (i.e. not intrinsics) llvm-svn: 194469
2013-11-12 18:31:49 +08:00
class SRLRI_B_DESC : MSA_BIT_B_X_DESC_BASE<"srlri.b", int_mips_srlri_b,
MSA128BOpnd>;
class SRLRI_H_DESC : MSA_BIT_H_X_DESC_BASE<"srlri.h", int_mips_srlri_h,
MSA128HOpnd>;
class SRLRI_W_DESC : MSA_BIT_W_X_DESC_BASE<"srlri.w", int_mips_srlri_w,
MSA128WOpnd>;
class SRLRI_D_DESC : MSA_BIT_D_X_DESC_BASE<"srlri.d", int_mips_srlri_d,
MSA128DOpnd>;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode,
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
ValueType TyNode, RegisterOperand ROWD,
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
2014-03-03 22:31:21 +08:00
Operand MemOpnd = mem_msa, ComplexPattern Addr = addrimm10,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
InstrItinClass itin = NoItinerary> {
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
dag OutOperandList = (outs);
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
dag InOperandList = (ins ROWD:$wd, MemOpnd:$addr);
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
string AsmString = !strconcat(instr_asm, "\t$wd, $addr");
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
list<dag> Pattern = [(OpNode (TyNode ROWD:$wd), Addr:$addr)];
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
InstrItinClass Itinerary = itin;
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
string DecoderMethod = "DecodeMSA128Mem";
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
}
[mips][msa] Direct Object Emission support for LD/ST instructions. llvm-svn: 193082
2013-10-21 21:07:13 +08:00
class ST_B_DESC : ST_DESC_BASE<"st.b", store, v16i8, MSA128BOpnd>;
class ST_H_DESC : ST_DESC_BASE<"st.h", store, v8i16, MSA128HOpnd>;
class ST_W_DESC : ST_DESC_BASE<"st.w", store, v4i32, MSA128WOpnd>;
class ST_D_DESC : ST_DESC_BASE<"st.d", store, v2i64, MSA128DOpnd>;
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class SUBS_S_B_DESC : MSA_3R_DESC_BASE<"subs_s.b", int_mips_subs_s_b,
MSA128BOpnd>;
class SUBS_S_H_DESC : MSA_3R_DESC_BASE<"subs_s.h", int_mips_subs_s_h,
MSA128HOpnd>;
class SUBS_S_W_DESC : MSA_3R_DESC_BASE<"subs_s.w", int_mips_subs_s_w,
MSA128WOpnd>;
class SUBS_S_D_DESC : MSA_3R_DESC_BASE<"subs_s.d", int_mips_subs_s_d,
MSA128DOpnd>;
class SUBS_U_B_DESC : MSA_3R_DESC_BASE<"subs_u.b", int_mips_subs_u_b,
MSA128BOpnd>;
class SUBS_U_H_DESC : MSA_3R_DESC_BASE<"subs_u.h", int_mips_subs_u_h,
MSA128HOpnd>;
class SUBS_U_W_DESC : MSA_3R_DESC_BASE<"subs_u.w", int_mips_subs_u_w,
MSA128WOpnd>;
class SUBS_U_D_DESC : MSA_3R_DESC_BASE<"subs_u.d", int_mips_subs_u_d,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUS_U_B_DESC : MSA_3R_DESC_BASE<"subsus_u.b", int_mips_subsus_u_b,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128BOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUS_U_H_DESC : MSA_3R_DESC_BASE<"subsus_u.h", int_mips_subsus_u_h,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUS_U_W_DESC : MSA_3R_DESC_BASE<"subsus_u.w", int_mips_subsus_u_w,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUS_U_D_DESC : MSA_3R_DESC_BASE<"subsus_u.d", int_mips_subsus_u_d,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUU_S_B_DESC : MSA_3R_DESC_BASE<"subsuu_s.b", int_mips_subsuu_s_b,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128BOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUU_S_H_DESC : MSA_3R_DESC_BASE<"subsuu_s.h", int_mips_subsuu_s_h,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128HOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUU_S_W_DESC : MSA_3R_DESC_BASE<"subsuu_s.w", int_mips_subsuu_s_w,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128WOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
class SUBSUU_S_D_DESC : MSA_3R_DESC_BASE<"subsuu_s.d", int_mips_subsuu_s_d,
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class SUBV_B_DESC : MSA_3R_DESC_BASE<"subv.b", sub, MSA128BOpnd>;
class SUBV_H_DESC : MSA_3R_DESC_BASE<"subv.h", sub, MSA128HOpnd>;
class SUBV_W_DESC : MSA_3R_DESC_BASE<"subv.w", sub, MSA128WOpnd>;
class SUBV_D_DESC : MSA_3R_DESC_BASE<"subv.d", sub, MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for I5 instructions. This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}. Patch by Matheus Almeida llvm-svn: 191687
2013-10-01 01:58:07 +08:00
class SUBVI_B_DESC : MSA_I5_DESC_BASE<"subvi.b", sub, vsplati8_uimm5,
MSA128BOpnd>;
class SUBVI_H_DESC : MSA_I5_DESC_BASE<"subvi.h", sub, vsplati16_uimm5,
MSA128HOpnd>;
class SUBVI_W_DESC : MSA_I5_DESC_BASE<"subvi.w", sub, vsplati32_uimm5,
MSA128WOpnd>;
class SUBVI_D_DESC : MSA_I5_DESC_BASE<"subvi.d", sub, vsplati64_uimm5,
MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission for 3R instructions. This is the first set of instructions with a ".b" modifier thus we need to add the required code to disassemble a MSA128B register class. Patch by Matheus Almeida llvm-svn: 191415
2013-09-26 08:09:46 +08:00
class VSHF_B_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.b", MSA128BOpnd>;
class VSHF_H_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.h", MSA128HOpnd>;
class VSHF_W_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.w", MSA128WOpnd>;
class VSHF_D_DESC : MSA_3R_VSHF_DESC_BASE<"vshf.d", MSA128DOpnd>;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
class XOR_V_DESC : MSA_VEC_DESC_BASE<"xor.v", xor, MSA128BOpnd>;
class XOR_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128HOpnd>;
class XOR_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128WOpnd>;
class XOR_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<xor, MSA128DOpnd>;
[mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v llvm-svn: 188767
2013-08-20 16:38:21 +08:00
[mips][msa] Direct Object Emission for I8 instructions. This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b. Patch by Matheus Almeida llvm-svn: 191688
2013-10-01 02:05:18 +08:00
class XORI_B_DESC : MSA_I8_DESC_BASE<"xori.b", xor, vsplati8_uimm8,
MSA128BOpnd>;
[mips][msa] Made the operand register sets optional for the I8 format Their default is to be the same as the result register set. No functional change llvm-svn: 190142
2013-09-06 20:25:47 +08:00
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
// Instruction defs.
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def ADD_A_B : ADD_A_B_ENC, ADD_A_B_DESC;
def ADD_A_H : ADD_A_H_ENC, ADD_A_H_DESC;
def ADD_A_W : ADD_A_W_ENC, ADD_A_W_DESC;
def ADD_A_D : ADD_A_D_ENC, ADD_A_D_DESC;
def ADDS_A_B : ADDS_A_B_ENC, ADDS_A_B_DESC;
def ADDS_A_H : ADDS_A_H_ENC, ADDS_A_H_DESC;
def ADDS_A_W : ADDS_A_W_ENC, ADDS_A_W_DESC;
def ADDS_A_D : ADDS_A_D_ENC, ADDS_A_D_DESC;
def ADDS_S_B : ADDS_S_B_ENC, ADDS_S_B_DESC;
def ADDS_S_H : ADDS_S_H_ENC, ADDS_S_H_DESC;
def ADDS_S_W : ADDS_S_W_ENC, ADDS_S_W_DESC;
def ADDS_S_D : ADDS_S_D_ENC, ADDS_S_D_DESC;
def ADDS_U_B : ADDS_U_B_ENC, ADDS_U_B_DESC;
def ADDS_U_H : ADDS_U_H_ENC, ADDS_U_H_DESC;
def ADDS_U_W : ADDS_U_W_ENC, ADDS_U_W_DESC;
def ADDS_U_D : ADDS_U_D_ENC, ADDS_U_D_DESC;
def ADDV_B : ADDV_B_ENC, ADDV_B_DESC;
def ADDV_H : ADDV_H_ENC, ADDV_H_DESC;
def ADDV_W : ADDV_W_ENC, ADDV_W_DESC;
def ADDV_D : ADDV_D_ENC, ADDV_D_DESC;
def ADDVI_B : ADDVI_B_ENC, ADDVI_B_DESC;
def ADDVI_H : ADDVI_H_ENC, ADDVI_H_DESC;
def ADDVI_W : ADDVI_W_ENC, ADDVI_W_DESC;
def ADDVI_D : ADDVI_D_ENC, ADDVI_D_DESC;
def AND_V : AND_V_ENC, AND_V_DESC;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def AND_V_H_PSEUDO : AND_V_H_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def AND_V_W_PSEUDO : AND_V_W_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def AND_V_D_PSEUDO : AND_V_D_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(AND_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def ANDI_B : ANDI_B_ENC, ANDI_B_DESC;
def ASUB_S_B : ASUB_S_B_ENC, ASUB_S_B_DESC;
def ASUB_S_H : ASUB_S_H_ENC, ASUB_S_H_DESC;
def ASUB_S_W : ASUB_S_W_ENC, ASUB_S_W_DESC;
def ASUB_S_D : ASUB_S_D_ENC, ASUB_S_D_DESC;
def ASUB_U_B : ASUB_U_B_ENC, ASUB_U_B_DESC;
def ASUB_U_H : ASUB_U_H_ENC, ASUB_U_H_DESC;
def ASUB_U_W : ASUB_U_W_ENC, ASUB_U_W_DESC;
def ASUB_U_D : ASUB_U_D_ENC, ASUB_U_D_DESC;
def AVE_S_B : AVE_S_B_ENC, AVE_S_B_DESC;
def AVE_S_H : AVE_S_H_ENC, AVE_S_H_DESC;
def AVE_S_W : AVE_S_W_ENC, AVE_S_W_DESC;
def AVE_S_D : AVE_S_D_ENC, AVE_S_D_DESC;
def AVE_U_B : AVE_U_B_ENC, AVE_U_B_DESC;
def AVE_U_H : AVE_U_H_ENC, AVE_U_H_DESC;
def AVE_U_W : AVE_U_W_ENC, AVE_U_W_DESC;
def AVE_U_D : AVE_U_D_ENC, AVE_U_D_DESC;
def AVER_S_B : AVER_S_B_ENC, AVER_S_B_DESC;
def AVER_S_H : AVER_S_H_ENC, AVER_S_H_DESC;
def AVER_S_W : AVER_S_W_ENC, AVER_S_W_DESC;
def AVER_S_D : AVER_S_D_ENC, AVER_S_D_DESC;
def AVER_U_B : AVER_U_B_ENC, AVER_U_B_DESC;
def AVER_U_H : AVER_U_H_ENC, AVER_U_H_DESC;
def AVER_U_W : AVER_U_W_ENC, AVER_U_W_DESC;
def AVER_U_D : AVER_U_D_ENC, AVER_U_D_DESC;
def BCLR_B : BCLR_B_ENC, BCLR_B_DESC;
def BCLR_H : BCLR_H_ENC, BCLR_H_DESC;
def BCLR_W : BCLR_W_ENC, BCLR_W_DESC;
def BCLR_D : BCLR_D_ENC, BCLR_D_DESC;
def BCLRI_B : BCLRI_B_ENC, BCLRI_B_DESC;
def BCLRI_H : BCLRI_H_ENC, BCLRI_H_DESC;
def BCLRI_W : BCLRI_W_ENC, BCLRI_W_DESC;
def BCLRI_D : BCLRI_D_ENC, BCLRI_D_DESC;
def BINSL_B : BINSL_B_ENC, BINSL_B_DESC;
def BINSL_H : BINSL_H_ENC, BINSL_H_DESC;
def BINSL_W : BINSL_W_ENC, BINSL_W_DESC;
def BINSL_D : BINSL_D_ENC, BINSL_D_DESC;
def BINSLI_B : BINSLI_B_ENC, BINSLI_B_DESC;
def BINSLI_H : BINSLI_H_ENC, BINSLI_H_DESC;
def BINSLI_W : BINSLI_W_ENC, BINSLI_W_DESC;
def BINSLI_D : BINSLI_D_ENC, BINSLI_D_DESC;
def BINSR_B : BINSR_B_ENC, BINSR_B_DESC;
def BINSR_H : BINSR_H_ENC, BINSR_H_DESC;
def BINSR_W : BINSR_W_ENC, BINSR_W_DESC;
def BINSR_D : BINSR_D_ENC, BINSR_D_DESC;
def BINSRI_B : BINSRI_B_ENC, BINSRI_B_DESC;
def BINSRI_H : BINSRI_H_ENC, BINSRI_H_DESC;
def BINSRI_W : BINSRI_W_ENC, BINSRI_W_DESC;
def BINSRI_D : BINSRI_D_ENC, BINSRI_D_DESC;
def BMNZ_V : BMNZ_V_ENC, BMNZ_V_DESC;
def BMNZI_B : BMNZI_B_ENC, BMNZI_B_DESC;
def BMZ_V : BMZ_V_ENC, BMZ_V_DESC;
def BMZI_B : BMZI_B_ENC, BMZI_B_DESC;
def BNEG_B : BNEG_B_ENC, BNEG_B_DESC;
def BNEG_H : BNEG_H_ENC, BNEG_H_DESC;
def BNEG_W : BNEG_W_ENC, BNEG_W_DESC;
def BNEG_D : BNEG_D_ENC, BNEG_D_DESC;
def BNEGI_B : BNEGI_B_ENC, BNEGI_B_DESC;
def BNEGI_H : BNEGI_H_ENC, BNEGI_H_DESC;
def BNEGI_W : BNEGI_W_ENC, BNEGI_W_DESC;
def BNEGI_D : BNEGI_D_ENC, BNEGI_D_DESC;
def BNZ_B : BNZ_B_ENC, BNZ_B_DESC;
def BNZ_H : BNZ_H_ENC, BNZ_H_DESC;
def BNZ_W : BNZ_W_ENC, BNZ_W_DESC;
def BNZ_D : BNZ_D_ENC, BNZ_D_DESC;
def BNZ_V : BNZ_V_ENC, BNZ_V_DESC;
def BSEL_V : BSEL_V_ENC, BSEL_V_DESC;
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
class MSA_BSEL_PSEUDO_BASE<RegisterOperand RO, ValueType Ty> :
[mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
2013-11-20 22:32:28 +08:00
MSAPseudo<(outs RO:$wd), (ins RO:$wd_in, RO:$ws, RO:$wt),
[mips] BSEL's and BINS[RL] operands are reversed compared to the vselect node used in the pattern. Summary: Correct the match patterns and the lowerings that made the CodeGen tests pass despite the mistakes. The original testcase that discovered the problem was SingleSource/UnitTests/SignlessType/factor.c in test-suite. During review, we also found that some of the existing CodeGen tests were incorrect and fixed them: * bitwise.ll: In bsel_v16i8 the IfSet/IfClear were reversed because bsel and bmnz have different operand orders and the test didn't correctly account for this. bmnz goes 'IfClear, IfSet, CondMask', while bsel goes 'CondMask, IfClear, IfSet'. * vec.ll: In the cases where a bsel is emitted as a bmnz (they are the same operation with a different input tied to the result) the operands were in the wrong order. * compare.ll and compare_float.ll: The bsel operand order was correct for a greater-than comparison, but a greater-than comparison instruction doesn't exist. Lowering this operation inverts the condition so the IfSet/IfClear need to be swapped to match. The differences between BSEL, BMNZ, and BMZ and how they map to/from vselect are rather confusing. I've therefore added a note to MSA.txt to explain this in a single place in addition to the comments that explain each case. Reviewers: matheusalmeida, jacksprat Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3028 llvm-svn: 203657
2014-03-12 19:54:00 +08:00
[(set RO:$wd, (Ty (vselect RO:$wd_in, RO:$wt, RO:$ws)))]>,
// Note that vselect and BSEL_V treat the condition operand the opposite way
// from each other.
// (vselect cond, if_set, if_clear)
// (BSEL_V cond, if_clear, if_set)
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(BSEL_V MSA128BOpnd:$wd, MSA128BOpnd:$wd_in,
MSA128BOpnd:$ws, MSA128BOpnd:$wt)> {
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
let Constraints = "$wd_in = $wd";
}
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
def BSEL_H_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128HOpnd, v8i16>;
def BSEL_W_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4i32>;
def BSEL_D_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2i64>;
def BSEL_FW_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128WOpnd, v4f32>;
def BSEL_FD_PSEUDO : MSA_BSEL_PSEUDO_BASE<MSA128DOpnd, v2f64>;
[mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) This required correcting the definition of the bsel and bseli intrinsics. llvm-svn: 191290
2013-09-24 20:04:44 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def BSELI_B : BSELI_B_ENC, BSELI_B_DESC;
def BSET_B : BSET_B_ENC, BSET_B_DESC;
def BSET_H : BSET_H_ENC, BSET_H_DESC;
def BSET_W : BSET_W_ENC, BSET_W_DESC;
def BSET_D : BSET_D_ENC, BSET_D_DESC;
def BSETI_B : BSETI_B_ENC, BSETI_B_DESC;
def BSETI_H : BSETI_H_ENC, BSETI_H_DESC;
def BSETI_W : BSETI_W_ENC, BSETI_W_DESC;
def BSETI_D : BSETI_D_ENC, BSETI_D_DESC;
def BZ_B : BZ_B_ENC, BZ_B_DESC;
def BZ_H : BZ_H_ENC, BZ_H_DESC;
def BZ_W : BZ_W_ENC, BZ_W_DESC;
def BZ_D : BZ_D_ENC, BZ_D_DESC;
def BZ_V : BZ_V_ENC, BZ_V_DESC;
def CEQ_B : CEQ_B_ENC, CEQ_B_DESC;
def CEQ_H : CEQ_H_ENC, CEQ_H_DESC;
def CEQ_W : CEQ_W_ENC, CEQ_W_DESC;
def CEQ_D : CEQ_D_ENC, CEQ_D_DESC;
def CEQI_B : CEQI_B_ENC, CEQI_B_DESC;
def CEQI_H : CEQI_H_ENC, CEQI_H_DESC;
def CEQI_W : CEQI_W_ENC, CEQI_W_DESC;
def CEQI_D : CEQI_D_ENC, CEQI_D_DESC;
def CFCMSA : CFCMSA_ENC, CFCMSA_DESC;
def CLE_S_B : CLE_S_B_ENC, CLE_S_B_DESC;
def CLE_S_H : CLE_S_H_ENC, CLE_S_H_DESC;
def CLE_S_W : CLE_S_W_ENC, CLE_S_W_DESC;
def CLE_S_D : CLE_S_D_ENC, CLE_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CLE_U_B : CLE_U_B_ENC, CLE_U_B_DESC;
def CLE_U_H : CLE_U_H_ENC, CLE_U_H_DESC;
def CLE_U_W : CLE_U_W_ENC, CLE_U_W_DESC;
def CLE_U_D : CLE_U_D_ENC, CLE_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CLEI_S_B : CLEI_S_B_ENC, CLEI_S_B_DESC;
def CLEI_S_H : CLEI_S_H_ENC, CLEI_S_H_DESC;
def CLEI_S_W : CLEI_S_W_ENC, CLEI_S_W_DESC;
def CLEI_S_D : CLEI_S_D_ENC, CLEI_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CLEI_U_B : CLEI_U_B_ENC, CLEI_U_B_DESC;
def CLEI_U_H : CLEI_U_H_ENC, CLEI_U_H_DESC;
def CLEI_U_W : CLEI_U_W_ENC, CLEI_U_W_DESC;
def CLEI_U_D : CLEI_U_D_ENC, CLEI_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CLT_S_B : CLT_S_B_ENC, CLT_S_B_DESC;
def CLT_S_H : CLT_S_H_ENC, CLT_S_H_DESC;
def CLT_S_W : CLT_S_W_ENC, CLT_S_W_DESC;
def CLT_S_D : CLT_S_D_ENC, CLT_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CLT_U_B : CLT_U_B_ENC, CLT_U_B_DESC;
def CLT_U_H : CLT_U_H_ENC, CLT_U_H_DESC;
def CLT_U_W : CLT_U_W_ENC, CLT_U_W_DESC;
def CLT_U_D : CLT_U_D_ENC, CLT_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CLTI_S_B : CLTI_S_B_ENC, CLTI_S_B_DESC;
def CLTI_S_H : CLTI_S_H_ENC, CLTI_S_H_DESC;
def CLTI_S_W : CLTI_S_W_ENC, CLTI_S_W_DESC;
def CLTI_S_D : CLTI_S_D_ENC, CLTI_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CLTI_U_B : CLTI_U_B_ENC, CLTI_U_B_DESC;
def CLTI_U_H : CLTI_U_H_ENC, CLTI_U_H_DESC;
def CLTI_U_W : CLTI_U_W_ENC, CLTI_U_W_DESC;
def CLTI_U_D : CLTI_U_D_ENC, CLTI_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def COPY_S_B : COPY_S_B_ENC, COPY_S_B_DESC;
def COPY_S_H : COPY_S_H_ENC, COPY_S_H_DESC;
def COPY_S_W : COPY_S_W_ENC, COPY_S_W_DESC;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
def COPY_S_D : COPY_S_D_ENC, COPY_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def COPY_U_B : COPY_U_B_ENC, COPY_U_B_DESC;
def COPY_U_H : COPY_U_H_ENC, COPY_U_H_DESC;
def COPY_U_W : COPY_U_W_ENC, COPY_U_W_DESC;
[mips][msa] Add copy_{u,s}.d. These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
2014-01-29 22:05:28 +08:00
def COPY_U_D : COPY_U_D_ENC, COPY_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may be expanded to subregister copies and/or instructions as appropriate. llvm-svn: 191514
2013-09-27 20:17:32 +08:00
def COPY_FW_PSEUDO : COPY_FW_PSEUDO_DESC;
def COPY_FD_PSEUDO : COPY_FD_PSEUDO_DESC;
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def CTCMSA : CTCMSA_ENC, CTCMSA_DESC;
[mips][msa] Added cfcmsa, and ctcmsa The MSA control registers have been added as reserved registers, and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered into these nodes. llvm-svn: 189468
2013-08-28 18:26:24 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DIV_S_B : DIV_S_B_ENC, DIV_S_B_DESC;
def DIV_S_H : DIV_S_H_ENC, DIV_S_H_DESC;
def DIV_S_W : DIV_S_W_ENC, DIV_S_W_DESC;
def DIV_S_D : DIV_S_D_ENC, DIV_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DIV_U_B : DIV_U_B_ENC, DIV_U_B_DESC;
def DIV_U_H : DIV_U_H_ENC, DIV_U_H_DESC;
def DIV_U_W : DIV_U_W_ENC, DIV_U_W_DESC;
def DIV_U_D : DIV_U_D_ENC, DIV_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DOTP_S_H : DOTP_S_H_ENC, DOTP_S_H_DESC;
def DOTP_S_W : DOTP_S_W_ENC, DOTP_S_W_DESC;
def DOTP_S_D : DOTP_S_D_ENC, DOTP_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DOTP_U_H : DOTP_U_H_ENC, DOTP_U_H_DESC;
def DOTP_U_W : DOTP_U_W_ENC, DOTP_U_W_DESC;
def DOTP_U_D : DOTP_U_D_ENC, DOTP_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DPADD_S_H : DPADD_S_H_ENC, DPADD_S_H_DESC;
def DPADD_S_W : DPADD_S_W_ENC, DPADD_S_W_DESC;
def DPADD_S_D : DPADD_S_D_ENC, DPADD_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DPADD_U_H : DPADD_U_H_ENC, DPADD_U_H_DESC;
def DPADD_U_W : DPADD_U_W_ENC, DPADD_U_W_DESC;
def DPADD_U_D : DPADD_U_D_ENC, DPADD_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DPSUB_S_H : DPSUB_S_H_ENC, DPSUB_S_H_DESC;
def DPSUB_S_W : DPSUB_S_W_ENC, DPSUB_S_W_DESC;
def DPSUB_S_D : DPSUB_S_D_ENC, DPSUB_S_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def DPSUB_U_H : DPSUB_U_H_ENC, DPSUB_U_H_DESC;
def DPSUB_U_W : DPSUB_U_W_ENC, DPSUB_U_W_DESC;
def DPSUB_U_D : DPSUB_U_D_ENC, DPSUB_U_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FADD_W : FADD_W_ENC, FADD_W_DESC;
def FADD_D : FADD_D_ENC, FADD_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCAF_W : FCAF_W_ENC, FCAF_W_DESC;
def FCAF_D : FCAF_D_ENC, FCAF_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCEQ_W : FCEQ_W_ENC, FCEQ_W_DESC;
def FCEQ_D : FCEQ_D_ENC, FCEQ_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCLE_W : FCLE_W_ENC, FCLE_W_DESC;
def FCLE_D : FCLE_D_ENC, FCLE_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCLT_W : FCLT_W_ENC, FCLT_W_DESC;
def FCLT_D : FCLT_D_ENC, FCLT_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCLASS_W : FCLASS_W_ENC, FCLASS_W_DESC;
def FCLASS_D : FCLASS_D_ENC, FCLASS_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCNE_W : FCNE_W_ENC, FCNE_W_DESC;
def FCNE_D : FCNE_D_ENC, FCNE_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCOR_W : FCOR_W_ENC, FCOR_W_DESC;
def FCOR_D : FCOR_D_ENC, FCOR_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCUEQ_W : FCUEQ_W_ENC, FCUEQ_W_DESC;
def FCUEQ_D : FCUEQ_D_ENC, FCUEQ_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCULE_W : FCULE_W_ENC, FCULE_W_DESC;
def FCULE_D : FCULE_D_ENC, FCULE_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCULT_W : FCULT_W_ENC, FCULT_W_DESC;
def FCULT_D : FCULT_D_ENC, FCULT_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCUN_W : FCUN_W_ENC, FCUN_W_DESC;
def FCUN_D : FCUN_D_ENC, FCUN_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FCUNE_W : FCUNE_W_ENC, FCUNE_W_DESC;
def FCUNE_D : FCUNE_D_ENC, FCUNE_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FDIV_W : FDIV_W_ENC, FDIV_W_DESC;
def FDIV_D : FDIV_D_ENC, FDIV_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FEXDO_H : FEXDO_H_ENC, FEXDO_H_DESC;
def FEXDO_W : FEXDO_W_ENC, FEXDO_W_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FEXP2_W : FEXP2_W_ENC, FEXP2_W_DESC;
def FEXP2_D : FEXP2_D_ENC, FEXP2_D_DESC;
[mips][msa] Added support for matching fexp2 from normal IR (i.e. not intrinsics) llvm-svn: 193239
2013-10-23 18:36:52 +08:00
def FEXP2_W_1_PSEUDO : FEXP2_W_1_PSEUDO_DESC;
def FEXP2_D_1_PSEUDO : FEXP2_D_1_PSEUDO_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FEXUPL_W : FEXUPL_W_ENC, FEXUPL_W_DESC;
def FEXUPL_D : FEXUPL_D_ENC, FEXUPL_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FEXUPR_W : FEXUPR_W_ENC, FEXUPR_W_DESC;
def FEXUPR_D : FEXUPR_D_ENC, FEXUPR_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FFINT_S_W : FFINT_S_W_ENC, FFINT_S_W_DESC;
def FFINT_S_D : FFINT_S_D_ENC, FFINT_S_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FFINT_U_W : FFINT_U_W_ENC, FFINT_U_W_DESC;
def FFINT_U_D : FFINT_U_D_ENC, FFINT_U_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FFQL_W : FFQL_W_ENC, FFQL_W_DESC;
def FFQL_D : FFQL_D_ENC, FFQL_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FFQR_W : FFQR_W_ENC, FFQR_W_DESC;
def FFQR_D : FFQR_D_ENC, FFQR_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FILL_B : FILL_B_ENC, FILL_B_DESC;
def FILL_H : FILL_H_ENC, FILL_H_DESC;
def FILL_W : FILL_W_ENC, FILL_W_DESC;
[mips][msa] Add fill.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
2014-01-29 23:12:02 +08:00
def FILL_D : FILL_D_ENC, FILL_D_DESC;
[mips][msa] Added support for build_vector for v4f32 and v2f64. llvm-svn: 192699
2013-10-15 21:14:41 +08:00
def FILL_FW_PSEUDO : FILL_FW_PSEUDO_DESC;
def FILL_FD_PSEUDO : FILL_FD_PSEUDO_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FLOG2_W : FLOG2_W_ENC, FLOG2_W_DESC;
def FLOG2_D : FLOG2_D_ENC, FLOG2_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FMADD_W : FMADD_W_ENC, FMADD_W_DESC;
def FMADD_D : FMADD_D_ENC, FMADD_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FMAX_W : FMAX_W_ENC, FMAX_W_DESC;
def FMAX_D : FMAX_D_ENC, FMAX_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FMAX_A_W : FMAX_A_W_ENC, FMAX_A_W_DESC;
def FMAX_A_D : FMAX_A_D_ENC, FMAX_A_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FMIN_W : FMIN_W_ENC, FMIN_W_DESC;
def FMIN_D : FMIN_D_ENC, FMIN_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FMIN_A_W : FMIN_A_W_ENC, FMIN_A_W_DESC;
def FMIN_A_D : FMIN_A_D_ENC, FMIN_A_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FMSUB_W : FMSUB_W_ENC, FMSUB_W_DESC;
def FMSUB_D : FMSUB_D_ENC, FMSUB_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FMUL_W : FMUL_W_ENC, FMUL_W_DESC;
def FMUL_D : FMUL_D_ENC, FMUL_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FRINT_W : FRINT_W_ENC, FRINT_W_DESC;
def FRINT_D : FRINT_D_ENC, FRINT_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FRCP_W : FRCP_W_ENC, FRCP_W_DESC;
def FRCP_D : FRCP_D_ENC, FRCP_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FRSQRT_W : FRSQRT_W_ENC, FRSQRT_W_DESC;
def FRSQRT_D : FRSQRT_D_ENC, FRSQRT_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSAF_W : FSAF_W_ENC, FSAF_W_DESC;
def FSAF_D : FSAF_D_ENC, FSAF_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSEQ_W : FSEQ_W_ENC, FSEQ_W_DESC;
def FSEQ_D : FSEQ_D_ENC, FSEQ_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSLE_W : FSLE_W_ENC, FSLE_W_DESC;
def FSLE_D : FSLE_D_ENC, FSLE_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSLT_W : FSLT_W_ENC, FSLT_W_DESC;
def FSLT_D : FSLT_D_ENC, FSLT_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSNE_W : FSNE_W_ENC, FSNE_W_DESC;
def FSNE_D : FSNE_D_ENC, FSNE_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSOR_W : FSOR_W_ENC, FSOR_W_DESC;
def FSOR_D : FSOR_D_ENC, FSOR_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSQRT_W : FSQRT_W_ENC, FSQRT_W_DESC;
def FSQRT_D : FSQRT_D_ENC, FSQRT_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSUB_W : FSUB_W_ENC, FSUB_W_DESC;
def FSUB_D : FSUB_D_ENC, FSUB_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSUEQ_W : FSUEQ_W_ENC, FSUEQ_W_DESC;
def FSUEQ_D : FSUEQ_D_ENC, FSUEQ_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSULE_W : FSULE_W_ENC, FSULE_W_DESC;
def FSULE_D : FSULE_D_ENC, FSULE_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSULT_W : FSULT_W_ENC, FSULT_W_DESC;
def FSULT_D : FSULT_D_ENC, FSULT_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSUN_W : FSUN_W_ENC, FSUN_W_DESC;
def FSUN_D : FSUN_D_ENC, FSUN_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FSUNE_W : FSUNE_W_ENC, FSUNE_W_DESC;
def FSUNE_D : FSUNE_D_ENC, FSUNE_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FTINT_S_W : FTINT_S_W_ENC, FTINT_S_W_DESC;
def FTINT_S_D : FTINT_S_D_ENC, FTINT_S_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FTINT_U_W : FTINT_U_W_ENC, FTINT_U_W_DESC;
def FTINT_U_D : FTINT_U_D_ENC, FTINT_U_D_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def FTQ_H : FTQ_H_ENC, FTQ_H_DESC;
def FTQ_W : FTQ_W_ENC, FTQ_W_DESC;
[Mips][msa] Added the simple builtins (fadd to ftq) Includes: fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2, fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin, fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt, fsne, fsqr, fsub, ftint_s, ftq Patch by Daniel Sanders llvm-svn: 188458
2013-08-15 21:45:36 +08:00
[mips][msa] Correct definition order of ftrunc_[su], ftint_[su], and ftq. Define these three instructions in alphabetical order (like the rest of the file). No functional change. llvm-svn: 192880
2013-10-17 18:30:12 +08:00
def FTRUNC_S_W : FTRUNC_S_W_ENC, FTRUNC_S_W_DESC;
def FTRUNC_S_D : FTRUNC_S_D_ENC, FTRUNC_S_D_DESC;
def FTRUNC_U_W : FTRUNC_U_W_ENC, FTRUNC_U_W_DESC;
def FTRUNC_U_D : FTRUNC_U_D_ENC, FTRUNC_U_D_DESC;
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def HADD_S_H : HADD_S_H_ENC, HADD_S_H_DESC;
def HADD_S_W : HADD_S_W_ENC, HADD_S_W_DESC;
def HADD_S_D : HADD_S_D_ENC, HADD_S_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def HADD_U_H : HADD_U_H_ENC, HADD_U_H_DESC;
def HADD_U_W : HADD_U_W_ENC, HADD_U_W_DESC;
def HADD_U_D : HADD_U_D_ENC, HADD_U_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def HSUB_S_H : HSUB_S_H_ENC, HSUB_S_H_DESC;
def HSUB_S_W : HSUB_S_W_ENC, HSUB_S_W_DESC;
def HSUB_S_D : HSUB_S_D_ENC, HSUB_S_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def HSUB_U_H : HSUB_U_H_ENC, HSUB_U_H_DESC;
def HSUB_U_W : HSUB_U_W_ENC, HSUB_U_W_DESC;
def HSUB_U_D : HSUB_U_D_ENC, HSUB_U_D_DESC;
[mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri llvm-svn: 189467
2013-08-28 18:12:09 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def ILVEV_B : ILVEV_B_ENC, ILVEV_B_DESC;
def ILVEV_H : ILVEV_H_ENC, ILVEV_H_DESC;
def ILVEV_W : ILVEV_W_ENC, ILVEV_W_DESC;
def ILVEV_D : ILVEV_D_ENC, ILVEV_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def ILVL_B : ILVL_B_ENC, ILVL_B_DESC;
def ILVL_H : ILVL_H_ENC, ILVL_H_DESC;
def ILVL_W : ILVL_W_ENC, ILVL_W_DESC;
def ILVL_D : ILVL_D_ENC, ILVL_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def ILVOD_B : ILVOD_B_ENC, ILVOD_B_DESC;
def ILVOD_H : ILVOD_H_ENC, ILVOD_H_DESC;
def ILVOD_W : ILVOD_W_ENC, ILVOD_W_DESC;
def ILVOD_D : ILVOD_D_ENC, ILVOD_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def ILVR_B : ILVR_B_ENC, ILVR_B_DESC;
def ILVR_H : ILVR_H_ENC, ILVR_H_DESC;
def ILVR_W : ILVR_W_ENC, ILVR_W_DESC;
def ILVR_D : ILVR_D_ENC, ILVR_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def INSERT_B : INSERT_B_ENC, INSERT_B_DESC;
def INSERT_H : INSERT_H_ENC, INSERT_H_DESC;
def INSERT_W : INSERT_W_ENC, INSERT_W_DESC;
[mips][msa] Add insert.d instruction. This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200543
2014-01-31 21:31:20 +08:00
def INSERT_D : INSERT_D_ENC, INSERT_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
// INSERT_FW_PSEUDO defined after INSVE_W
// INSERT_FD_PSEUDO defined after INSVE_D
[mips] Rewrite MipsAsmParser and MipsOperand. Summary: Highlights: - Registers are resolved much later (by the render method). Prior to that point, GPR32's/GPR64's are GPR's regardless of register size. Similarly FGR32's/FGR64's/AFGR64's are FGR's regardless of register size or FR mode. Numeric registers can be anything. - All registers are parsed the same way everywhere (even when handling symbol aliasing) - One consequence is that all registers can be specified numerically almost anywhere (e.g. $fccX, $wX). The exception is symbol aliasing but that can be easily resolved. - Removes the need for the hasConsumedDollar hack - Parenthesis and Bracket suffixes are handled generically - Micromips instructions are parsed directly instead of going through the standard encodings first. - rdhwr accepts all 32 registers, and the following instructions that previously xfailed now work: ddiv, ddivu, div, divu, cvt.l.[ds], se[bh], wsbh, floor.w.[ds], c.ngl.d, c.sf.s, dsbh, dshd, madd.s, msub.s, nmadd.s, nmsub.s, swxc1 - Diagnostics involving registers point at the correct character (the $) - There's only one kind of immediate in MipsOperand. LSA immediates are handled by the predicate and renderer. Lowlights: - Hardcoded '$zero' in the div patterns is handled with a hack. MipsOperand::isReg() will return true for a k_RegisterIndex token with Index == 0 and getReg() will return ZERO for this case. Note that it doesn't return ZERO_64 on isGP64() targets. - I haven't cleaned up all of the now-unused functions. Some more of the generic parser could be removed too (integers and relocs for example). - insve.df needed a custom decoder to handle the implicit fourth operand that was needed to make it parse correctly. The difficulty was that the matcher expected a Token<'0'> but gets an Imm<0>. Adding an implicit zero solved this. Reviewers: matheusalmeida, vmedic Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D3222 llvm-svn: 205292
2014-04-01 18:35:28 +08:00
// There is a fourth operand that is not present in the encoding. Use a
// custom decoder to get a chance to add it.
let DecoderMethod = "DecodeINSVE_DF" in {
def INSVE_B : INSVE_B_ENC, INSVE_B_DESC;
def INSVE_H : INSVE_H_ENC, INSVE_H_DESC;
def INSVE_W : INSVE_W_ENC, INSVE_W_DESC;
def INSVE_D : INSVE_D_ENC, INSVE_D_DESC;
}
[mips][msa] Added insve llvm-svn: 188777
2013-08-20 17:22:54 +08:00
[mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is later expanded to appropriate insve.[wd] insns. llvm-svn: 191515
2013-09-27 20:31:32 +08:00
def INSERT_FW_PSEUDO : INSERT_FW_PSEUDO_DESC;
def INSERT_FD_PSEUDO : INSERT_FD_PSEUDO_DESC;
[mips][msa] Fix vector insertions where the index is variable Summary: This isn't supported directly so we rotate the vector by the desired number of elements, insert to element zero, then rotate back. The i64 case generates rather poor code on MIPS32. There is an obvious optimisation to be made in future (do both insert.w's inside a shared rotate/unrotate sequence) but for now it's sufficient to select valid code instead of aborting. Depends on D3536 Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3537 llvm-svn: 207640
2014-04-30 20:09:32 +08:00
def INSERT_B_VIDX_PSEUDO : INSERT_B_VIDX_PSEUDO_DESC;
def INSERT_H_VIDX_PSEUDO : INSERT_H_VIDX_PSEUDO_DESC;
def INSERT_W_VIDX_PSEUDO : INSERT_W_VIDX_PSEUDO_DESC;
def INSERT_D_VIDX_PSEUDO : INSERT_D_VIDX_PSEUDO_DESC;
def INSERT_FW_VIDX_PSEUDO : INSERT_FW_VIDX_PSEUDO_DESC;
def INSERT_FD_VIDX_PSEUDO : INSERT_FD_VIDX_PSEUDO_DESC;
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
def INSERT_B_VIDX64_PSEUDO : INSERT_B_VIDX64_PSEUDO_DESC;
def INSERT_H_VIDX64_PSEUDO : INSERT_H_VIDX64_PSEUDO_DESC;
def INSERT_W_VIDX64_PSEUDO : INSERT_W_VIDX64_PSEUDO_DESC;
def INSERT_D_VIDX64_PSEUDO : INSERT_D_VIDX64_PSEUDO_DESC;
def INSERT_FW_VIDX64_PSEUDO : INSERT_FW_VIDX64_PSEUDO_DESC;
def INSERT_FD_VIDX64_PSEUDO : INSERT_FD_VIDX64_PSEUDO_DESC;
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def LD_B: LD_B_ENC, LD_B_DESC;
def LD_H: LD_H_ENC, LD_H_DESC;
def LD_W: LD_W_ENC, LD_W_DESC;
def LD_D: LD_D_ENC, LD_D_DESC;
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def LDI_B : LDI_B_ENC, LDI_B_DESC;
def LDI_H : LDI_H_ENC, LDI_H_DESC;
def LDI_W : LDI_W_ENC, LDI_W_DESC;
[mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) Note: There's a later patch on my branch that re-implements this to select build_vector without the custom SelectionDAG nodes. The future patch avoids the constant-folding problems stemming from the custom node (i.e. it doesn't need to re-implement all the DAG combines related to BUILD_VECTOR). Changes to MIPS specific SelectionDAG nodes: * Added VSPLAT This is a special case of BUILD_VECTOR that covers the case the BUILD_VECTOR is a splat operation. * Added VSPLATD This is a special case of VSPLAT that handles the cases when v2i64 is legal llvm-svn: 191191
2013-09-23 20:02:46 +08:00
def LDI_D : LDI_D_ENC, LDI_D_DESC;
[Mips][msa] Added the simple builtins (add_a to dpsub[su], ilvev to ldi) Includes: add_a, adds_[asu], addv, addvi, andi.b, asub_[su].[bhwd], aver?_[su]_[bhwd], bclr, bclri, bins[lr], bins[lr]i, bmnzi, bmzi, bneg, bnegi, bseli, bset, bseti, c(eq|ne), c(eq|ne)i, cl[et]_[su], cl[et]i_[su], copy_[su].[bhw], div_[su], dotp_[su], dpadd_[su], dpsub_[su], ilvev, ilvl, ilvod, ilvr, insv, insve, ldi Patch by Daniel Sanders llvm-svn: 188457
2013-08-15 20:24:57 +08:00
[mips][msa] Added lsa instruction llvm-svn: 192895
2013-10-17 21:38:20 +08:00
def LSA : LSA_ENC, LSA_DESC;
[mips][msa] Add DLSA instruction. llvm-svn: 201081
2014-02-10 20:05:17 +08:00
def DLSA : DLSA_ENC, DLSA_DESC;
[mips][msa] Added lsa instruction llvm-svn: 192895
2013-10-17 21:38:20 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def MADD_Q_H : MADD_Q_H_ENC, MADD_Q_H_DESC;
def MADD_Q_W : MADD_Q_W_ENC, MADD_Q_W_DESC;
def MADDR_Q_H : MADDR_Q_H_ENC, MADDR_Q_H_DESC;
def MADDR_Q_W : MADDR_Q_W_ENC, MADDR_Q_W_DESC;
def MADDV_B : MADDV_B_ENC, MADDV_B_DESC;
def MADDV_H : MADDV_H_ENC, MADDV_H_DESC;
def MADDV_W : MADDV_W_ENC, MADDV_W_DESC;
def MADDV_D : MADDV_D_ENC, MADDV_D_DESC;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def MAX_A_B : MAX_A_B_ENC, MAX_A_B_DESC;
def MAX_A_H : MAX_A_H_ENC, MAX_A_H_DESC;
def MAX_A_W : MAX_A_W_ENC, MAX_A_W_DESC;
def MAX_A_D : MAX_A_D_ENC, MAX_A_D_DESC;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def MAX_S_B : MAX_S_B_ENC, MAX_S_B_DESC;
def MAX_S_H : MAX_S_H_ENC, MAX_S_H_DESC;
def MAX_S_W : MAX_S_W_ENC, MAX_S_W_DESC;
def MAX_S_D : MAX_S_D_ENC, MAX_S_D_DESC;
def MAX_U_B : MAX_U_B_ENC, MAX_U_B_DESC;
def MAX_U_H : MAX_U_H_ENC, MAX_U_H_DESC;
def MAX_U_W : MAX_U_W_ENC, MAX_U_W_DESC;
def MAX_U_D : MAX_U_D_ENC, MAX_U_D_DESC;
def MAXI_S_B : MAXI_S_B_ENC, MAXI_S_B_DESC;
def MAXI_S_H : MAXI_S_H_ENC, MAXI_S_H_DESC;
def MAXI_S_W : MAXI_S_W_ENC, MAXI_S_W_DESC;
def MAXI_S_D : MAXI_S_D_ENC, MAXI_S_D_DESC;
def MAXI_U_B : MAXI_U_B_ENC, MAXI_U_B_DESC;
def MAXI_U_H : MAXI_U_H_ENC, MAXI_U_H_DESC;
def MAXI_U_W : MAXI_U_W_ENC, MAXI_U_W_DESC;
def MAXI_U_D : MAXI_U_D_ENC, MAXI_U_D_DESC;
def MIN_A_B : MIN_A_B_ENC, MIN_A_B_DESC;
def MIN_A_H : MIN_A_H_ENC, MIN_A_H_DESC;
def MIN_A_W : MIN_A_W_ENC, MIN_A_W_DESC;
def MIN_A_D : MIN_A_D_ENC, MIN_A_D_DESC;
def MIN_S_B : MIN_S_B_ENC, MIN_S_B_DESC;
def MIN_S_H : MIN_S_H_ENC, MIN_S_H_DESC;
def MIN_S_W : MIN_S_W_ENC, MIN_S_W_DESC;
def MIN_S_D : MIN_S_D_ENC, MIN_S_D_DESC;
def MIN_U_B : MIN_U_B_ENC, MIN_U_B_DESC;
def MIN_U_H : MIN_U_H_ENC, MIN_U_H_DESC;
def MIN_U_W : MIN_U_W_ENC, MIN_U_W_DESC;
def MIN_U_D : MIN_U_D_ENC, MIN_U_D_DESC;
def MINI_S_B : MINI_S_B_ENC, MINI_S_B_DESC;
def MINI_S_H : MINI_S_H_ENC, MINI_S_H_DESC;
def MINI_S_W : MINI_S_W_ENC, MINI_S_W_DESC;
def MINI_S_D : MINI_S_D_ENC, MINI_S_D_DESC;
def MINI_U_B : MINI_U_B_ENC, MINI_U_B_DESC;
def MINI_U_H : MINI_U_H_ENC, MINI_U_H_DESC;
def MINI_U_W : MINI_U_W_ENC, MINI_U_W_DESC;
def MINI_U_D : MINI_U_D_ENC, MINI_U_D_DESC;
def MOD_S_B : MOD_S_B_ENC, MOD_S_B_DESC;
def MOD_S_H : MOD_S_H_ENC, MOD_S_H_DESC;
def MOD_S_W : MOD_S_W_ENC, MOD_S_W_DESC;
def MOD_S_D : MOD_S_D_ENC, MOD_S_D_DESC;
def MOD_U_B : MOD_U_B_ENC, MOD_U_B_DESC;
def MOD_U_H : MOD_U_H_ENC, MOD_U_H_DESC;
def MOD_U_W : MOD_U_W_ENC, MOD_U_W_DESC;
def MOD_U_D : MOD_U_D_ENC, MOD_U_D_DESC;
def MOVE_V : MOVE_V_ENC, MOVE_V_DESC;
def MSUB_Q_H : MSUB_Q_H_ENC, MSUB_Q_H_DESC;
def MSUB_Q_W : MSUB_Q_W_ENC, MSUB_Q_W_DESC;
def MSUBR_Q_H : MSUBR_Q_H_ENC, MSUBR_Q_H_DESC;
def MSUBR_Q_W : MSUBR_Q_W_ENC, MSUBR_Q_W_DESC;
def MSUBV_B : MSUBV_B_ENC, MSUBV_B_DESC;
def MSUBV_H : MSUBV_H_ENC, MSUBV_H_DESC;
def MSUBV_W : MSUBV_W_ENC, MSUBV_W_DESC;
def MSUBV_D : MSUBV_D_ENC, MSUBV_D_DESC;
def MUL_Q_H : MUL_Q_H_ENC, MUL_Q_H_DESC;
def MUL_Q_W : MUL_Q_W_ENC, MUL_Q_W_DESC;
def MULR_Q_H : MULR_Q_H_ENC, MULR_Q_H_DESC;
def MULR_Q_W : MULR_Q_W_ENC, MULR_Q_W_DESC;
def MULV_B : MULV_B_ENC, MULV_B_DESC;
def MULV_H : MULV_H_ENC, MULV_H_DESC;
def MULV_W : MULV_W_ENC, MULV_W_DESC;
def MULV_D : MULV_D_ENC, MULV_D_DESC;
def NLOC_B : NLOC_B_ENC, NLOC_B_DESC;
def NLOC_H : NLOC_H_ENC, NLOC_H_DESC;
def NLOC_W : NLOC_W_ENC, NLOC_W_DESC;
def NLOC_D : NLOC_D_ENC, NLOC_D_DESC;
def NLZC_B : NLZC_B_ENC, NLZC_B_DESC;
def NLZC_H : NLZC_H_ENC, NLZC_H_DESC;
def NLZC_W : NLZC_W_ENC, NLZC_W_DESC;
def NLZC_D : NLZC_D_ENC, NLZC_D_DESC;
def NOR_V : NOR_V_ENC, NOR_V_DESC;
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) llvm-svn: 191195
2013-09-23 21:22:24 +08:00
def NOR_V_H_PSEUDO : NOR_V_H_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) llvm-svn: 191195
2013-09-23 21:22:24 +08:00
def NOR_V_W_PSEUDO : NOR_V_W_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) llvm-svn: 191195
2013-09-23 21:22:24 +08:00
def NOR_V_D_PSEUDO : NOR_V_D_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(NOR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def NORI_B : NORI_B_ENC, NORI_B_DESC;
def OR_V : OR_V_ENC, OR_V_DESC;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def OR_V_H_PSEUDO : OR_V_H_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def OR_V_W_PSEUDO : OR_V_W_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def OR_V_D_PSEUDO : OR_V_D_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(OR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def ORI_B : ORI_B_ENC, ORI_B_DESC;
def PCKEV_B : PCKEV_B_ENC, PCKEV_B_DESC;
def PCKEV_H : PCKEV_H_ENC, PCKEV_H_DESC;
def PCKEV_W : PCKEV_W_ENC, PCKEV_W_DESC;
def PCKEV_D : PCKEV_D_ENC, PCKEV_D_DESC;
def PCKOD_B : PCKOD_B_ENC, PCKOD_B_DESC;
def PCKOD_H : PCKOD_H_ENC, PCKOD_H_DESC;
def PCKOD_W : PCKOD_W_ENC, PCKOD_W_DESC;
def PCKOD_D : PCKOD_D_ENC, PCKOD_D_DESC;
def PCNT_B : PCNT_B_ENC, PCNT_B_DESC;
def PCNT_H : PCNT_H_ENC, PCNT_H_DESC;
def PCNT_W : PCNT_W_ENC, PCNT_W_DESC;
def PCNT_D : PCNT_D_ENC, PCNT_D_DESC;
def SAT_S_B : SAT_S_B_ENC, SAT_S_B_DESC;
def SAT_S_H : SAT_S_H_ENC, SAT_S_H_DESC;
def SAT_S_W : SAT_S_W_ENC, SAT_S_W_DESC;
def SAT_S_D : SAT_S_D_ENC, SAT_S_D_DESC;
def SAT_U_B : SAT_U_B_ENC, SAT_U_B_DESC;
def SAT_U_H : SAT_U_H_ENC, SAT_U_H_DESC;
def SAT_U_W : SAT_U_W_ENC, SAT_U_W_DESC;
def SAT_U_D : SAT_U_D_ENC, SAT_U_D_DESC;
def SHF_B : SHF_B_ENC, SHF_B_DESC;
def SHF_H : SHF_H_ENC, SHF_H_DESC;
def SHF_W : SHF_W_ENC, SHF_W_DESC;
def SLD_B : SLD_B_ENC, SLD_B_DESC;
def SLD_H : SLD_H_ENC, SLD_H_DESC;
def SLD_W : SLD_W_ENC, SLD_W_DESC;
def SLD_D : SLD_D_ENC, SLD_D_DESC;
def SLDI_B : SLDI_B_ENC, SLDI_B_DESC;
def SLDI_H : SLDI_H_ENC, SLDI_H_DESC;
def SLDI_W : SLDI_W_ENC, SLDI_W_DESC;
def SLDI_D : SLDI_D_ENC, SLDI_D_DESC;
def SLL_B : SLL_B_ENC, SLL_B_DESC;
def SLL_H : SLL_H_ENC, SLL_H_DESC;
def SLL_W : SLL_W_ENC, SLL_W_DESC;
def SLL_D : SLL_D_ENC, SLL_D_DESC;
def SLLI_B : SLLI_B_ENC, SLLI_B_DESC;
def SLLI_H : SLLI_H_ENC, SLLI_H_DESC;
def SLLI_W : SLLI_W_ENC, SLLI_W_DESC;
def SLLI_D : SLLI_D_ENC, SLLI_D_DESC;
def SPLAT_B : SPLAT_B_ENC, SPLAT_B_DESC;
def SPLAT_H : SPLAT_H_ENC, SPLAT_H_DESC;
def SPLAT_W : SPLAT_W_ENC, SPLAT_W_DESC;
def SPLAT_D : SPLAT_D_ENC, SPLAT_D_DESC;
def SPLATI_B : SPLATI_B_ENC, SPLATI_B_DESC;
def SPLATI_H : SPLATI_H_ENC, SPLATI_H_DESC;
def SPLATI_W : SPLATI_W_ENC, SPLATI_W_DESC;
def SPLATI_D : SPLATI_D_ENC, SPLATI_D_DESC;
def SRA_B : SRA_B_ENC, SRA_B_DESC;
def SRA_H : SRA_H_ENC, SRA_H_DESC;
def SRA_W : SRA_W_ENC, SRA_W_DESC;
def SRA_D : SRA_D_ENC, SRA_D_DESC;
def SRAI_B : SRAI_B_ENC, SRAI_B_DESC;
def SRAI_H : SRAI_H_ENC, SRAI_H_DESC;
def SRAI_W : SRAI_W_ENC, SRAI_W_DESC;
def SRAI_D : SRAI_D_ENC, SRAI_D_DESC;
def SRAR_B : SRAR_B_ENC, SRAR_B_DESC;
def SRAR_H : SRAR_H_ENC, SRAR_H_DESC;
def SRAR_W : SRAR_W_ENC, SRAR_W_DESC;
def SRAR_D : SRAR_D_ENC, SRAR_D_DESC;
def SRARI_B : SRARI_B_ENC, SRARI_B_DESC;
def SRARI_H : SRARI_H_ENC, SRARI_H_DESC;
def SRARI_W : SRARI_W_ENC, SRARI_W_DESC;
def SRARI_D : SRARI_D_ENC, SRARI_D_DESC;
def SRL_B : SRL_B_ENC, SRL_B_DESC;
def SRL_H : SRL_H_ENC, SRL_H_DESC;
def SRL_W : SRL_W_ENC, SRL_W_DESC;
def SRL_D : SRL_D_ENC, SRL_D_DESC;
def SRLI_B : SRLI_B_ENC, SRLI_B_DESC;
def SRLI_H : SRLI_H_ENC, SRLI_H_DESC;
def SRLI_W : SRLI_W_ENC, SRLI_W_DESC;
def SRLI_D : SRLI_D_ENC, SRLI_D_DESC;
def SRLR_B : SRLR_B_ENC, SRLR_B_DESC;
def SRLR_H : SRLR_H_ENC, SRLR_H_DESC;
def SRLR_W : SRLR_W_ENC, SRLR_W_DESC;
def SRLR_D : SRLR_D_ENC, SRLR_D_DESC;
def SRLRI_B : SRLRI_B_ENC, SRLRI_B_DESC;
def SRLRI_H : SRLRI_H_ENC, SRLRI_H_DESC;
def SRLRI_W : SRLRI_W_ENC, SRLRI_W_DESC;
def SRLRI_D : SRLRI_D_ENC, SRLRI_D_DESC;
def ST_B: ST_B_ENC, ST_B_DESC;
def ST_H: ST_H_ENC, ST_H_DESC;
def ST_W: ST_W_ENC, ST_W_DESC;
def ST_D: ST_D_ENC, ST_D_DESC;
def SUBS_S_B : SUBS_S_B_ENC, SUBS_S_B_DESC;
def SUBS_S_H : SUBS_S_H_ENC, SUBS_S_H_DESC;
def SUBS_S_W : SUBS_S_W_ENC, SUBS_S_W_DESC;
def SUBS_S_D : SUBS_S_D_ENC, SUBS_S_D_DESC;
def SUBS_U_B : SUBS_U_B_ENC, SUBS_U_B_DESC;
def SUBS_U_H : SUBS_U_H_ENC, SUBS_U_H_DESC;
def SUBS_U_W : SUBS_U_W_ENC, SUBS_U_W_DESC;
def SUBS_U_D : SUBS_U_D_ENC, SUBS_U_D_DESC;
def SUBSUS_U_B : SUBSUS_U_B_ENC, SUBSUS_U_B_DESC;
def SUBSUS_U_H : SUBSUS_U_H_ENC, SUBSUS_U_H_DESC;
def SUBSUS_U_W : SUBSUS_U_W_ENC, SUBSUS_U_W_DESC;
def SUBSUS_U_D : SUBSUS_U_D_ENC, SUBSUS_U_D_DESC;
def SUBSUU_S_B : SUBSUU_S_B_ENC, SUBSUU_S_B_DESC;
def SUBSUU_S_H : SUBSUU_S_H_ENC, SUBSUU_S_H_DESC;
def SUBSUU_S_W : SUBSUU_S_W_ENC, SUBSUU_S_W_DESC;
def SUBSUU_S_D : SUBSUU_S_D_ENC, SUBSUU_S_D_DESC;
def SUBV_B : SUBV_B_ENC, SUBV_B_DESC;
def SUBV_H : SUBV_H_ENC, SUBV_H_DESC;
def SUBV_W : SUBV_W_ENC, SUBV_W_DESC;
def SUBV_D : SUBV_D_ENC, SUBV_D_DESC;
def SUBVI_B : SUBVI_B_ENC, SUBVI_B_DESC;
def SUBVI_H : SUBVI_H_ENC, SUBVI_H_DESC;
def SUBVI_W : SUBVI_W_ENC, SUBVI_W_DESC;
def SUBVI_D : SUBVI_D_ENC, SUBVI_D_DESC;
def VSHF_B : VSHF_B_ENC, VSHF_B_DESC;
def VSHF_H : VSHF_H_ENC, VSHF_H_DESC;
def VSHF_W : VSHF_W_ENC, VSHF_W_DESC;
def VSHF_D : VSHF_D_ENC, VSHF_D_DESC;
def XOR_V : XOR_V_ENC, XOR_V_DESC;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def XOR_V_H_PSEUDO : XOR_V_H_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def XOR_V_W_PSEUDO : XOR_V_W_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) llvm-svn: 191194
2013-09-23 20:57:42 +08:00
def XOR_V_D_PSEUDO : XOR_V_D_PSEUDO_DESC,
[mips][msa] Direct Object Emission support for VEC instructions. List of instructions: and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v. llvm-svn: 192588
2013-10-14 20:57:18 +08:00
PseudoInstExpansion<(XOR_V MSA128BOpnd:$wd,
MSA128BOpnd:$ws,
MSA128BOpnd:$wt)>;
[mips][msa] Requires<[HasMSA]> is redundant, it is also supplied via inheritance Tested with 'llvm-tblgen -print-records' which outputs identical records before and after this patch. llvm-svn: 190155
2013-09-06 21:15:05 +08:00
def XORI_B : XORI_B_ENC, XORI_B_DESC;
[Mips][msa] Added the simple builtins (madd_q to xori) Includes: madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su], msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev, pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al], sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori Patch by Daniel Sanders llvm-svn: 188460
2013-08-15 22:22:07 +08:00
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
// Patterns.
[mips][msa] Added bitconverts for vector types for big and little-endian llvm-svn: 189330
2013-08-27 17:40:30 +08:00
class MSAPat<dag pattern, dag result, list<Predicate> pred = [HasMSA]> :
Pat<pattern, result>, Requires<pred>;
[Mips][msa] Added initial MSA support. * msa SubtargetFeature * registers * ld.[bhwd], and st.[bhwd] instructions Does not correctly prohibit use of both 32-bit FPU registers and MSA together. Patch by Daniel Sanders llvm-svn: 188313
2013-08-14 04:54:07 +08:00
[mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) Changes to MIPS SelectionDAG: * Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single operation and implemented the DAG combines necessary to fold sign/zero extends into the extract. llvm-svn: 191199
2013-09-23 22:03:12 +08:00
def : MSAPat<(extractelt (v4i32 MSA128W:$ws), immZExt4:$idx),
(COPY_S_W MSA128W:$ws, immZExt4:$idx)>;
[mips] Prevent %lo relocation being used on MSA loads and stores. Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
2014-03-03 22:31:21 +08:00
def : MSAPat<(v8f16 (load addrimm10:$addr)), (LD_H addrimm10:$addr)>;
def : MSAPat<(v4f32 (load addrimm10:$addr)), (LD_W addrimm10:$addr)>;
def : MSAPat<(v2f64 (load addrimm10:$addr)), (LD_D addrimm10:$addr)>;
def ST_FH : MSAPat<(store (v8f16 MSA128H:$ws), addrimm10:$addr),
(ST_H MSA128H:$ws, addrimm10:$addr)>;
def ST_FW : MSAPat<(store (v4f32 MSA128W:$ws), addrimm10:$addr),
(ST_W MSA128W:$ws, addrimm10:$addr)>;
def ST_FD : MSAPat<(store (v2f64 MSA128D:$ws), addrimm10:$addr),
(ST_D MSA128D:$ws, addrimm10:$addr)>;
[mips][msa] Added bitconverts for vector types for big and little-endian llvm-svn: 189330
2013-08-27 17:40:30 +08:00
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
class MSA_FABS_PSEUDO_DESC_BASE<RegisterOperand ROWD,
RegisterOperand ROWS = ROWD,
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
2013-09-24 21:02:08 +08:00
InstrItinClass itin = NoItinerary> :
[mips][msa] Pseudo instructions require HasMSA too. Inherit from MSAPseudo instead of MipsPseudo There's no test case for this commit. This is because it is doubtful that the incorrect behaviour can actually trigger. When MSA is not enabled, the type legalizer should have eliminated all occurrences of patterns the affected pseudo-instruction could possibly match before instruction selection occurs. llvm-svn: 195252
2013-11-20 22:32:28 +08:00
MSAPseudo<(outs ROWD:$wd),
(ins ROWS:$ws),
[(set ROWD:$wd, (fabs ROWS:$ws))]> {
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
2013-09-24 21:02:08 +08:00
InstrItinClass Itinerary = itin;
}
[mips][msa] Direct Object Emission for 3RF instructions. Patch by Matheus Almeida llvm-svn: 191461
2013-09-27 05:31:43 +08:00
def FABS_W : MSA_FABS_PSEUDO_DESC_BASE<MSA128WOpnd>,
PseudoInstExpansion<(FMAX_A_W MSA128WOpnd:$wd, MSA128WOpnd:$ws,
MSA128WOpnd:$ws)>;
def FABS_D : MSA_FABS_PSEUDO_DESC_BASE<MSA128DOpnd>,
PseudoInstExpansion<(FMAX_A_D MSA128DOpnd:$wd, MSA128DOpnd:$ws,
MSA128DOpnd:$ws)>;
[mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics) This covers the case where fmax_a can be used to implement ISD::FABS. llvm-svn: 191296
2013-09-24 21:02:08 +08:00
[mips][msa] Added bitconverts for vector types for big and little-endian llvm-svn: 189330
2013-08-27 17:40:30 +08:00
class MSABitconvertPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC, list<Predicate> preds = [HasMSA]> :
MSAPat<(DstVT (bitconvert SrcVT:$src)),
(COPY_TO_REGCLASS SrcVT:$src, DstRC), preds>;
Fix known typos Sweep the codebase for common typos. Includes some changes to visible function names that were misspelt. llvm-svn: 200018
2014-01-25 01:20:08 +08:00
// These are endian-independent because the element size doesnt change
[mips][msa] Added bitconverts for vector types for big and little-endian llvm-svn: 189330
2013-08-27 17:40:30 +08:00
def : MSABitconvertPat<v8i16, v8f16, MSA128H>;
def : MSABitconvertPat<v4i32, v4f32, MSA128W>;
def : MSABitconvertPat<v2i64, v2f64, MSA128D>;
def : MSABitconvertPat<v8f16, v8i16, MSA128H>;
def : MSABitconvertPat<v4f32, v4i32, MSA128W>;
def : MSABitconvertPat<v2f64, v2i64, MSA128D>;
// Little endian bitcasts are always no-ops
def : MSABitconvertPat<v16i8, v8i16, MSA128B, [HasMSA, IsLE]>;
def : MSABitconvertPat<v16i8, v4i32, MSA128B, [HasMSA, IsLE]>;
def : MSABitconvertPat<v16i8, v2i64, MSA128B, [HasMSA, IsLE]>;
def : MSABitconvertPat<v16i8, v8f16, MSA128B, [HasMSA, IsLE]>;
def : MSABitconvertPat<v16i8, v4f32, MSA128B, [HasMSA, IsLE]>;
def : MSABitconvertPat<v16i8, v2f64, MSA128B, [HasMSA, IsLE]>;
def : MSABitconvertPat<v8i16, v16i8, MSA128H, [HasMSA, IsLE]>;
def : MSABitconvertPat<v8i16, v4i32, MSA128H, [HasMSA, IsLE]>;
def : MSABitconvertPat<v8i16, v2i64, MSA128H, [HasMSA, IsLE]>;
def : MSABitconvertPat<v8i16, v4f32, MSA128H, [HasMSA, IsLE]>;
def : MSABitconvertPat<v8i16, v2f64, MSA128H, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4i32, v16i8, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4i32, v8i16, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4i32, v2i64, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4i32, v8f16, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4i32, v2f64, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2i64, v16i8, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2i64, v8i16, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2i64, v4i32, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2i64, v8f16, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2i64, v4f32, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4f32, v16i8, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4f32, v8i16, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4f32, v2i64, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4f32, v8f16, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v4f32, v2f64, MSA128W, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2f64, v16i8, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2f64, v8i16, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2f64, v4i32, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2f64, v8f16, MSA128D, [HasMSA, IsLE]>;
def : MSABitconvertPat<v2f64, v4f32, MSA128D, [HasMSA, IsLE]>;
// Big endian bitcasts expand to shuffle instructions.
// This is because bitcast is defined to be a store/load sequence and the
// vector store/load instructions are mixed-endian with respect to the vector
// as a whole (little endian with respect to element order, but big endian
// elements).
class MSABitconvertReverseQuartersPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC, MSAInst Insn,
RegisterClass ViaRC> :
MSAPat<(DstVT (bitconvert SrcVT:$src)),
(COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 27),
DstRC),
[HasMSA, IsBE]>;
class MSABitconvertReverseHalvesPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC, MSAInst Insn,
RegisterClass ViaRC> :
MSAPat<(DstVT (bitconvert SrcVT:$src)),
(COPY_TO_REGCLASS (Insn (COPY_TO_REGCLASS SrcVT:$src, ViaRC), 177),
DstRC),
[HasMSA, IsBE]>;
class MSABitconvertReverseBInHPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC> :
MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
class MSABitconvertReverseBInWPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC> :
MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_B, MSA128B>;
class MSABitconvertReverseBInDPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC> :
MSAPat<(DstVT (bitconvert SrcVT:$src)),
(COPY_TO_REGCLASS
(SHF_W
(COPY_TO_REGCLASS
(SHF_B (COPY_TO_REGCLASS SrcVT:$src, MSA128B), 27),
MSA128W), 177),
DstRC),
[HasMSA, IsBE]>;
class MSABitconvertReverseHInWPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC> :
MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
class MSABitconvertReverseHInDPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC> :
MSABitconvertReverseQuartersPat<DstVT, SrcVT, DstRC, SHF_H, MSA128H>;
class MSABitconvertReverseWInDPat<ValueType DstVT, ValueType SrcVT,
RegisterClass DstRC> :
MSABitconvertReverseHalvesPat<DstVT, SrcVT, DstRC, SHF_W, MSA128W>;
def : MSABitconvertReverseBInHPat<v8i16, v16i8, MSA128H>;
def : MSABitconvertReverseBInHPat<v8f16, v16i8, MSA128H>;
def : MSABitconvertReverseBInWPat<v4i32, v16i8, MSA128W>;
def : MSABitconvertReverseBInWPat<v4f32, v16i8, MSA128W>;
def : MSABitconvertReverseBInDPat<v2i64, v16i8, MSA128D>;
def : MSABitconvertReverseBInDPat<v2f64, v16i8, MSA128D>;
def : MSABitconvertReverseBInHPat<v16i8, v8i16, MSA128B>;
def : MSABitconvertReverseHInWPat<v4i32, v8i16, MSA128W>;
def : MSABitconvertReverseHInWPat<v4f32, v8i16, MSA128W>;
def : MSABitconvertReverseHInDPat<v2i64, v8i16, MSA128D>;
def : MSABitconvertReverseHInDPat<v2f64, v8i16, MSA128D>;
def : MSABitconvertReverseBInHPat<v16i8, v8f16, MSA128B>;
def : MSABitconvertReverseHInWPat<v4i32, v8f16, MSA128W>;
def : MSABitconvertReverseHInWPat<v4f32, v8f16, MSA128W>;
def : MSABitconvertReverseHInDPat<v2i64, v8f16, MSA128D>;
def : MSABitconvertReverseHInDPat<v2f64, v8f16, MSA128D>;
def : MSABitconvertReverseBInWPat<v16i8, v4i32, MSA128B>;
def : MSABitconvertReverseHInWPat<v8i16, v4i32, MSA128H>;
def : MSABitconvertReverseHInWPat<v8f16, v4i32, MSA128H>;
def : MSABitconvertReverseWInDPat<v2i64, v4i32, MSA128D>;
def : MSABitconvertReverseWInDPat<v2f64, v4i32, MSA128D>;
def : MSABitconvertReverseBInWPat<v16i8, v4f32, MSA128B>;
def : MSABitconvertReverseHInWPat<v8i16, v4f32, MSA128H>;
def : MSABitconvertReverseHInWPat<v8f16, v4f32, MSA128H>;
def : MSABitconvertReverseWInDPat<v2i64, v4f32, MSA128D>;
def : MSABitconvertReverseWInDPat<v2f64, v4f32, MSA128D>;
def : MSABitconvertReverseBInDPat<v16i8, v2i64, MSA128B>;
def : MSABitconvertReverseHInDPat<v8i16, v2i64, MSA128H>;
def : MSABitconvertReverseHInDPat<v8f16, v2i64, MSA128H>;
def : MSABitconvertReverseWInDPat<v4i32, v2i64, MSA128W>;
def : MSABitconvertReverseWInDPat<v4f32, v2i64, MSA128W>;
def : MSABitconvertReverseBInDPat<v16i8, v2f64, MSA128B>;
def : MSABitconvertReverseHInDPat<v8i16, v2f64, MSA128H>;
def : MSABitconvertReverseHInDPat<v8f16, v2f64, MSA128H>;
def : MSABitconvertReverseWInDPat<v4i32, v2f64, MSA128W>;
def : MSABitconvertReverseWInDPat<v4f32, v2f64, MSA128W>;
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
// Pseudos used to implement BNZ.df, and BZ.df
class MSA_CBRANCH_PSEUDO_DESC_BASE<SDPatternOperator OpNode, ValueType TyNode,
[mips][msa] Made the InstrItinClass argument optional since it is always NoItinerary at the moment. No functional change llvm-svn: 190131
2013-09-06 18:55:15 +08:00
RegisterClass RCWS,
InstrItinClass itin = NoItinerary> :
[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478
2013-08-28 20:14:50 +08:00
MipsPseudo<(outs GPR32:$dst),
(ins RCWS:$ws),
[(set GPR32:$dst, (OpNode (TyNode RCWS:$ws)))]> {
bit usesCustomInserter = 1;
}
def SNZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v16i8,
MSA128B, NoItinerary>;
def SNZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v8i16,
MSA128H, NoItinerary>;
def SNZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v4i32,
MSA128W, NoItinerary>;
def SNZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllNonZero, v2i64,
MSA128D, NoItinerary>;
def SNZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyNonZero, v16i8,
MSA128B, NoItinerary>;
def SZ_B_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v16i8,
MSA128B, NoItinerary>;
def SZ_H_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v8i16,
MSA128H, NoItinerary>;
def SZ_W_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v4i32,
MSA128W, NoItinerary>;
def SZ_D_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAllZero, v2i64,
MSA128D, NoItinerary>;
def SZ_V_PSEUDO : MSA_CBRANCH_PSEUDO_DESC_BASE<MipsVAnyZero, v16i8,
MSA128B, NoItinerary>;
[mips][msa] Fix element extraction where the index is variable. Summary: This isn't supported directly so we splat the vector element and extract the most convenient copy. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://reviews.llvm.org/D3530 llvm-svn: 207524
2014-04-29 21:31:37 +08:00
// Vector extraction with variable index
def : MSAPat<(i32 (vextract_sext_i8 v16i8:$ws, i32:$idx)),
(SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
i32:$idx),
sub_lo)),
GPR32), (i32 24))>;
def : MSAPat<(i32 (vextract_sext_i16 v8i16:$ws, i32:$idx)),
(SRA (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
i32:$idx),
sub_lo)),
GPR32), (i32 16))>;
def : MSAPat<(i32 (vextract_sext_i32 v4i32:$ws, i32:$idx)),
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
i32:$idx),
sub_lo)),
GPR32)>;
def : MSAPat<(i64 (vextract_sext_i64 v2i64:$ws, i32:$idx)),
(COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
i32:$idx),
sub_64)),
GPR64), [HasMSA, IsGP64bit]>;
def : MSAPat<(i32 (vextract_zext_i8 v16i8:$ws, i32:$idx)),
(SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_B v16i8:$ws,
i32:$idx),
sub_lo)),
GPR32), (i32 24))>;
def : MSAPat<(i32 (vextract_zext_i16 v8i16:$ws, i32:$idx)),
(SRL (COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_H v8i16:$ws,
i32:$idx),
sub_lo)),
GPR32), (i32 16))>;
def : MSAPat<(i32 (vextract_zext_i32 v4i32:$ws, i32:$idx)),
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG (SPLAT_W v4i32:$ws,
i32:$idx),
sub_lo)),
GPR32)>;
def : MSAPat<(i64 (vextract_zext_i64 v2i64:$ws, i32:$idx)),
(COPY_TO_REGCLASS (i64 (EXTRACT_SUBREG (SPLAT_D v2i64:$ws,
i32:$idx),
sub_64)),
GPR64), [HasMSA, IsGP64bit]>;
def : MSAPat<(f32 (vector_extract v4f32:$ws, i32:$idx)),
(f32 (EXTRACT_SUBREG (SPLAT_W v4f32:$ws,
i32:$idx),
sub_lo))>;
def : MSAPat<(f64 (vector_extract v2f64:$ws, i32:$idx)),
(f64 (EXTRACT_SUBREG (SPLAT_D v2f64:$ws,
i32:$idx),
sub_64))>;
[mips] Generate code for insert/extract operations when using the N64 ABI and MSA. Summary: When using the N64 ABI, element-indices use the i64 type instead of i32. In many cases, we can use iPTR to account for this but additional patterns and pseudo's are also required. This fixes most (but not quite all) failures in the test-suite when using N64 and MSA together. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9342 llvm-svn: 236494
2015-05-05 18:32:24 +08:00
// Vector extraction with variable index (N64 ABI)
def : MSAPat<
(i32 (vextract_sext_i8 v16i8:$ws, i64:$idx)),
(SRA (COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG
(SPLAT_B v16i8:$ws,
(COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_lo)),
GPR32),
(i32 24))>;
def : MSAPat<
(i32 (vextract_sext_i16 v8i16:$ws, i64:$idx)),
(SRA (COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG
(SPLAT_H v8i16:$ws,
(COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_lo)),
GPR32),
(i32 16))>;
def : MSAPat<
(i32 (vextract_sext_i32 v4i32:$ws, i64:$idx)),
(COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG
(SPLAT_W v4i32:$ws,
(COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_lo)),
GPR32)>;
def : MSAPat<
(i64 (vextract_sext_i64 v2i64:$ws, i64:$idx)),
(COPY_TO_REGCLASS
(i64 (EXTRACT_SUBREG
(SPLAT_D v2i64:$ws,
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_64)),
GPR64), [HasMSA, IsGP64bit]>;
def : MSAPat<
(i32 (vextract_zext_i8 v16i8:$ws, i64:$idx)),
(SRL (COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG
(SPLAT_B v16i8:$ws,
(COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_lo)),
GPR32),
(i32 24))>;
def : MSAPat<
(i32 (vextract_zext_i16 v8i16:$ws, i64:$idx)),
(SRL (COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG
(SPLAT_H v8i16:$ws,
(COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_lo)),
GPR32),
(i32 16))>;
def : MSAPat<
(i32 (vextract_zext_i32 v4i32:$ws, i64:$idx)),
(COPY_TO_REGCLASS
(i32 (EXTRACT_SUBREG
(SPLAT_W v4i32:$ws,
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_lo)),
GPR32)>;
def : MSAPat<
(i64 (vextract_zext_i64 v2i64:$ws, i64:$idx)),
(COPY_TO_REGCLASS
(i64 (EXTRACT_SUBREG
(SPLAT_D v2i64:$ws,
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_64)),
GPR64),
[HasMSA, IsGP64bit]>;
def : MSAPat<
(f32 (vector_extract v4f32:$ws, i64:$idx)),
(f32 (EXTRACT_SUBREG
(SPLAT_W v4f32:$ws,
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_lo))>;
def : MSAPat<
(f64 (vector_extract v2f64:$ws, i64:$idx)),
(f64 (EXTRACT_SUBREG
(SPLAT_D v2f64:$ws,
(COPY_TO_REGCLASS (i32 (EXTRACT_SUBREG i64:$idx, sub_32)), GPR32)),
sub_64))>;